TWI658366B - Hardware resource expansion system and hot swap management device - Google Patents

Abstract

The hot plug management device includes a bus buffer unit, a hot plug switch and a controller. The bus buffer unit is selectively coupled to the host system of the server to manage the bus. The hot-swap switch is coupled to the bus buffer unit and the hardware expansion device. When the hot-swap management device is coupled to the substrate system of the server to manage the bus, the controller sets the hardware address of the bus buffer unit. The computing unit of the server controls the hardware expansion device through the host system management bus according to the hardware address.

Description

Hardware resource expansion system and hot plug management device

The invention relates to a hardware resource expansion system, in particular to a hardware resource expansion system capable of automatically allocating hardware addresses.

With the increasing application of cloud computing, the design of data centers also tends to classify and pool various types of resources, such as dividing resources into computing, storage, and network resources. Interconnect through a bus, such as a PCIE (Peripheral Component Interconnect Express) bus. In this way, the design of the hardware can be more flexible and easy to expand.

For example, when the storage space required by the computing server increases, the data center can purchase additional storage devices, and the server can connect to the additional storage devices through the PCIE bus to meet the storage space requirements. However, in the prior art, since the computing unit of the server needs to manage the access and exit of the PCIE storage slot through a single set of system management bus (SM Bus), the hardware address of each PCIE storage slot is They must be different to be able to be managed by the same system management bus. In practice, in order to be able to set the hardware address of the PCIE storage slot, it is necessary to manually set the pin position or set a separate circuit, which not only increases the complexity of the hardware design, but also increases the labor burden. It is not conducive to the management of the data center.

An embodiment of the present invention provides a hardware resource expansion system. The hardware resource expansion system includes a server, a first group of auxiliary signal lines, a first group of PCIE transmission lines, a first hardware expansion device, and a first hot plug management device. .

The computing unit is coupled to the host system management bus (SMBus) and a plurality of PCIE buses. A board management controller (BMC) is coupled to the computing unit and a plurality of board system management buses.

The first group of auxiliary signal lines includes a first group of system management buses and a second group of system management buses. The first group of system management buses is selectively coupled to the host system management bus, and the second group of system management buses is selectively coupled to the first substrate system management bus of the plurality of substrate system management buses. row. The first group of PCIE transmission lines is selectively coupled to a first PCIE bus of a plurality of PCIE buses.

The first hot plug management device is coupled to the first hardware expansion device and the first set of auxiliary signal lines. The first hot plug management device includes a first bus buffer unit, a first hot plug switch, and a first controller. .

The first bus buffer unit is coupled to the first set of system management bus lines of the first set of auxiliary signal lines. The first hot-swap switch is coupled to the first bus buffer unit and the first hardware expansion device. The first controller is coupled to the second group of system management bus lines, the first bus buffer unit, and the first hot-swap switch. When the second set of system management bus lines of the first set of auxiliary signal lines is coupled to the first substrate system management bus, the first controller sets the first hardware address of the first bus buffer unit. The computing unit controls the first hardware expansion device through the first group of system management bus lines of the first group of auxiliary signal lines according to the first hardware address.

Another embodiment of the present invention provides a hot plug management device. The hot plug management device includes a bus buffer unit, a hot plug switch, and a controller.

The bus buffer unit is selectively coupled to the host system of the server to manage the bus. The hot-swap switch is coupled to the bus buffer unit and the hardware expansion device. When the hot-swap management device is coupled to the substrate system of the server to manage the bus, the controller sets the hardware address of the bus buffer unit.

The computing unit of the server controls the hardware expansion device through the host system management bus according to the hardware address.

FIG. 1 is a schematic diagram of a hardware resource expansion system 100 according to an embodiment of the present invention. The hardware resource expansion system 100 includes a server 110, a first group of auxiliary signal lines 120A, a first group of PCIE transmission lines 130A, and a first hardware expansion. The device 140A and the first hot plug management device 150A.

The server 110 includes a computing unit 112 and a board management controller (BMC) 114. The computing unit 112 may be a processor with computing capabilities, including common single-core and multi-core computing processors. The computing unit 112 may be coupled to the host system management bus (SMBus) HS1 and N PCIE buses P1 to PN, where N is a positive integer greater than 1. The server 110 can manage the hardware devices coupled to the PCIE buses P1 to PN through the host system management bus HS1. For example, the PCIE buses P1 to PN can be respectively coupled to different hardware expansion devices, such as a hard disk array and a general purpose graphic processing unit (GPGPU) array. When these hardware expansion devices When coupled to the PCIE buses P1 to PN, the server 110 can use the host system management bus HS1 to confirm the status of the hardware expansion device, such as whether it is properly connected, whether it is powered on or ready to be removed, so the server 110 can According to the obtained status information, establish or disconnect communication with these hardware expansion devices through PCIE buses P1 to PN.

The substrate management controller 114 can manage other devices on the substrate of the server 110, such as a temperature sensor and a fan, so as to reduce the load on the computing unit 112 and ensure that the server 110 can operate stably. Since the baseboard management controller 114 needs to manage more devices, more system management buses are generally configured. In the embodiment of FIG. 1, the substrate management controller 114 may be coupled to the operation unit 112 and M substrate system management buses BS1 to BSM, where M is a positive integer greater than 1.

In some embodiments of the present invention, the server 110 and the external hardware expansion device may be connected through an auxiliary signal line and a PCIE transmission line. For example, in the first figure, the first set of auxiliary signal lines 120A and the first set of PCIE transmission lines may be selectively coupled to the server 110, that is, the first set of auxiliary signal lines 120A and the first set of PCIE transmission lines 130A. It can be plugged into the server 110 as required.

The first set of auxiliary signal lines 120A may be signals required to transmit and control hardware expansion devices. For example, the first set of auxiliary signal lines 120A may include a first set of system management bus lines 120A1 and a second set of system management bus lines. Line 120A2. The first group of system management bus lines 120A1 can be selectively coupled to the host system management bus HS1 along with the first group of auxiliary signal lines 120A, and the second group of system management bus lines 120A2 can follow the first group of auxiliary signals Line 120A is selectively coupled to the first substrate system management bus BS1 to the substrate system management bus BS1 to BSM.

In addition, the first group of PCIE transmission lines 130A can be selectively coupled to the first PCIE bus P1 of the PCIE buses P1 to PN.

In the first figure, although the first group of system management buses 120A1, the second group of system management buses 120A2, and the first group of PCIE transmission lines 130A are all represented by a single line segment, in practice, according to their buses Different transmission and transmission standards may actually include more than one signal line. For example, the first group of system management bus lines 120A1 may include two data lines including the data signal line and the pulse signal line required for system management bus, and the first group of PCIE transmission lines 130A may include, for example but not limited to, four Signal line.

In some embodiments of the present invention, the first group of auxiliary signal lines 120A and the first group of PCIE transmission lines 130A may be assembled into a bundle of transmission lines, and the server 110 may be based on the first group of auxiliary signal lines 120A and the first group of PCIE Corresponding interfaces are set in sequence for each signal transmission line in the transmission line 130A to facilitate user use. In this way, the user only needs to insert the assembled transmission line into the corresponding interface of the server 110 to couple the first group of system management bus lines 120A1 to the host system management bus HS1 and the second group of system management The bus line 120A2 is coupled to the first baseboard system management bus BS1, and the first group of PCIE transmission lines 130A is coupled to the first PCIE bus P1 among the PCIE buses P1 to PN.

In some embodiments of the present invention, the first set of auxiliary signal lines 120A may further include other signal lines according to the actual needs of the system, such as the reference clock signal line of PCIE and the reset signal line of PCIE.

The first hardware expansion device 140A can be used as an external hardware expansion device of the server 110 and provide hardware resources required by the server 110, such as memory storage space or computing resources. To enable the first hardware expansion device 140A to be plugged and unplugged during the continuous operation of the server 110, the first hardware expansion device 140A and the server 110 may be connected through the first hot plug management device 150A.

The first hot plug management device 150A can be coupled to the first hardware expansion device 140A and the first set of auxiliary signal lines 120A. The first hot plug management device 150A includes a first bus buffer unit 152A, a first hot plug switch 154A, and a first controller 156A.

The first bus buffer unit 152A may be a buffer unit of an integrated circuit bus (I2C), and may set and resolve a hardware address to expand the number of hardware that can be connected to the integrated circuit bus. The first bus buffer unit 152A may be coupled to the first set of system management bus lines 120A1 of the first set of auxiliary signal lines 120A.

The first hot-swap switch 154A may be coupled to the first bus buffer unit 152A and the first hardware expansion device 140A. The first controller 156A may be coupled to the second set of system management bus lines 120A2, the first bus buffer unit 152A, and the first hot-swap switch 154A of the first set of auxiliary signal lines 120A.

When the second set of system management bus lines 120A2 of the first set of auxiliary signal lines 120A is coupled to the first baseboard system management bus line BS1, the first controller 156A can manage the busbars through the second set of system management bus lines 120A2 to the baseboard. The controller 114 queries the currently available hardware address, and sets the first hardware address of the first bus buffer unit 152A according to the available hardware address provided by the baseboard management controller 114. In this way, the arithmetic unit 112 can control the first hardware expansion device 140 through the first group of system management bus lines 120A1 of the first group of auxiliary signal lines 120A according to the first hardware address. In addition, the first hot-swap management device 150A may be provided on the same substrate B1 as the first hardware expansion device 140A, and the first hot-swap management device 150A may include a pull-up resistor at the coupling point of the bus to determine the transmission line. The connection status to the bus.

In some embodiments of the present invention, the first hardware expansion device 140A may return the status parameters to the computing unit 112 through the first set of system management bus lines 120A1 of the first set of auxiliary signal lines 120A, so that the server 110 The state of the first hardware expansion device 140A can be known. For example, after connecting the first hardware expansion device 140 to the server 110 using the first auxiliary signal line 120A and the first PCIE transmission line 130A, the user can press the attention of the first hardware expansion device 140 At this time, the first hardware expansion device 140 can transmit the attention signal to the computing unit 112 via the first bus buffer unit 152A and the first set of system management bus lines 120A1 or other preset signal lines, and the computing unit 112 can establish corresponding communication through the first group of PCIE transmission lines 130A and the first PCIE bus P1.

Furthermore, if the user wants to remove the first hardware expansion device 140, he can also press the corresponding unloading attention button. At this time, the first hardware expansion device 140 can pass through the first bus buffer unit 152A and the first The group system management bus line 120A1 sends a corresponding unloading attention signal to the computing unit 112, and the computing unit 112 can correspondingly release the communication between the first group of PCIE transmission lines 130A and the first PCIE bus P1.

In this way, the server 110 can use the hardware resources of the first hardware expansion device 140A, and the first hardware expansion device 140 can also be hot-plugged while the server 110 remains in operation.

FIG. 2 is another usage scenario of the hardware resource expansion system 100. In FIG. 2, the hardware resource expansion system 100 may further include a second set of auxiliary signal lines 120B, a second set of PCIE transmission lines 130B, a second hardware expansion device 140B, and a second hot-plug management device 150B.

The second set of auxiliary signal lines 120B may include a first set of system management bus lines 120B1 and a second set of system management bus lines 120B2. The first group of system management buses 120B1 can be selectively coupled to the host system management bus HS1, the second group of system management buses 120B2 can be selectively coupled to the second substrate system management bus BS2, and the first The two sets of PCIE transmission lines 130B can be selectively coupled to the second PCIE bus P2.

The second hot plug management device 150B is coupled to the second hardware expansion device 140B and the second set of auxiliary signal lines 120B. The second hot plug management device 150B includes a second bus buffer unit 152B, a second hot plug switch 154B, and a second controller 156B.

The second bus buffer unit 152B is coupled to the first system management bus 120B1 of the second set of auxiliary signal lines 120B, and the second hot-swap switch 154B is coupled to the second bus buffer unit 152B and the second hardware expansion. Device 140B. The second controller 156B is coupled to the second set of system management buses 120B2, the second bus buffer unit 152B, and the second hot-swap switch 154B of the second set of auxiliary signal lines 120B.

When the second set of system management bus lines 120B2 of the second set of auxiliary signal lines 120B are coupled to the second substrate system management bus BS2, the second controller 156B can set the second hardware position of the second bus buffer unit 152B site.

In some embodiments of the present invention, the second controller 156B may obtain hardware from the baseboard management controller 114 that is not currently used by other hardware via the second set of system management bus lines 120B2 and the second baseboard system management bus BS2. Body address, and set the second hardware address accordingly. In this way, it is possible to ensure that the second hardware address is different from the first hardware address, so that the computing unit 112 can control the first hardware expansion device 140A and the second hardware expansion device through the host system management bus HS1. 140B without manually setting the hardware address of the hardware expansion device manually. In this way, not only is the operation more convenient, but the management efficiency can also be improved.

In summary, the hardware resource expansion system and hot plug management device provided by the embodiments of the present invention can set the corresponding hardware address by itself when the hardware expansion device is connected to the server to ensure that the server can be effective. Control each hardware expansion device separately and use the hardware resources in it. In other words, the hardware resource expansion system and the hot-swap management device of the present invention do not need to manually set the hardware address of the hardware expansion device manually, so it is more convenient in operation and can improve management efficiency. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

100‧‧‧ hardware resource expansion system

110‧‧‧Server

112‧‧‧ Computing Unit

114‧‧‧ substrate management controller

HS1‧‧‧ host system management bus

P1 to PN‧‧‧PCIE bus

BS1 to BSM ‧‧‧ substrate system management bus

120A‧‧‧The first set of auxiliary signal lines

120A1, 120B1‧‧‧‧The first group of system management bus

120A2, 120B2‧‧‧The second group of system management bus

130A‧‧‧The first group of PCIE transmission line

140A‧‧‧The first hardware expansion device

150A‧‧‧The first hot plug management device

152A‧‧‧First bus buffer unit

154A‧‧‧The first hot plug switch

156A‧‧‧First controller

120B‧‧‧Second set of auxiliary signal line

130B‧‧‧The second group of PCIE transmission line

140B‧‧‧Second Hardware Expansion Unit

150B‧‧‧Second Hot Plug Management Device

152B‧‧‧Second bus buffer unit

154B‧‧‧Second Hot Plug Switch

156B‧‧‧Second Controller

FIG. 1 is a schematic diagram of a hardware resource expansion system according to an embodiment of the present invention. Figure 2 is another usage scenario of the hardware resource expansion system of Figure 1.

Claims (5)

A hardware resource expansion system includes: a server including: a computing unit coupled to a host system management bus (SMBus) and a plurality of PCIE buses; and a board management controller (Board Management Controller (BMC), coupled to the computing unit and a plurality of baseboard system management buses; a first set of auxiliary signal lines, including: a first set of system management bus lines, selectively coupled to the host system Management bus; and a second group of system management buses, selectively coupled to a first substrate system management bus of the substrate system management buses; a first group of PCIE transmission lines, selectively coupled Connected to a first PCIE bus of the PCIE buses; a first hardware expansion device; and a first hot plug management device coupled to the first hardware expansion device and the first group of accessories The signal line includes: a first bus buffer unit coupled to the first group of system management bus lines of the first auxiliary signal line; a first hot plug switch coupled to the first bus line buffer Unit and the first hardware expansion device; and a first controller coupled to the second group of system management bus lines, the first bus buffer unit, and the first heat sink coupled to the first set of auxiliary signal lines A plug-in switch is used to set one of the first bus buffer units when the second set of system management bus lines of the first auxiliary signal line is coupled to the first substrate system management bus. The arithmetic unit controls the first hardware expansion device according to the first hardware address through the first group of system management buses of the first group of auxiliary signal lines. The hardware resource expansion system according to claim 1, wherein the first hardware expansion device and the server converge on the first group of PCIE transmission lines and the first PCIE after the first hardware address is set. Establish connection communication. The hardware resource expansion system according to claim 1, further comprising: a second set of auxiliary signal lines, including: a first set of system management bus lines, selectively coupled to the host system management bus; and A second group of system management buses is selectively coupled to a second substrate system management bus of the substrate system management buses; a second group of PCIE transmission lines is selectively coupled to the PCIEs A second PCIE bus in the bus; a second hardware expansion device; and a second hot-swap management device coupled to the second hardware expansion device and the second set of auxiliary signal lines, including: A second bus buffer unit is coupled to the first group of system management bus lines of the second auxiliary signal line; a second hot plug switch is coupled to the second bus buffer unit and the first Two hardware expansion devices; and a second controller coupled to the second set of system management bus lines, the second bus buffer unit, and the second hot-swap switch of the second set of auxiliary signal lines, The second group used as the second group of auxiliary signal lines When the system management bus line is coupled to the second substrate system management bus, a second hardware address of one of the second bus buffer units is set; wherein: the second hardware address is related to the first hardware address. And; the operation unit controls the second hardware expansion device according to the second hardware address via the first group of system management buses of the second group of auxiliary signal lines. The hardware resource expansion system according to claim 1, wherein the first set of auxiliary signal lines and the first set of PCIE transmission lines are assembled into a bundle of transmission lines. The hardware resource expansion system according to claim 1, wherein the first hardware expansion device and the first hot plug management device are disposed on a same substrate.