TWI655540B - Storage device - Google Patents

Abstract

A memory device includes a processor, a controller, and a switch. The processor is configured to control the operation of a logic circuit and generate a reset signal according to an operational state of the logic circuit when a primary reset signal is enabled. The controller generates a mask signal based on the primary reset signal and the secondary reset signal. When the mask signal is enabled, the switch does not transmit the main reset signal to the logic circuit. When the mask signal is not enabled, the switch transmits a master reset signal to the logic circuit to reset the logic circuit.

Description

Memory device

The present invention relates to a memory device, and more particularly to a memory device that can reset a logic circuit when an internal logic circuit ceases to function.

A typical electronic device has a reset switch for resetting the operating system of the electronic device. When the electronic device is down, the user can press the reset switch to turn the electronic device back on to resume normal operation. However, since the memory device in the electronic device may be performing a write operation or a read operation, when the user presses the reset switch, there is a high possibility that data is lost.

The invention provides a memory device comprising a processor, a controller and a switch. The processor is configured to control the operation of a logic circuit and generate a reset signal according to an operational state of the logic circuit when a primary reset signal is enabled. The controller generates a mask signal based on the primary reset signal and the secondary reset signal. When the mask signal is enabled, the switch does not transmit the main reset signal to the logic circuit. When the mask signal is not enabled, the switch transmits a master reset signal to the logic circuit to reset the logic circuit.

The present invention further provides a reset method for resetting a logic circuit in a memory device. The reset method of the present invention includes adjusting a count value according to a main reset signal, and causing the logic circuit to stop operating after completing a work, Where the work is the ongoing work of the logic circuit; determining whether the logic circuit stops operating; when the logic circuit does not stop operating, resetting the count value, and re-adjusting the count value; determining whether the count value is equal to a pre- Setting a value; and resetting the logic circuit when the count value is equal to the preset value.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

100A, 100B‧‧‧ memory device

110A, 110B‧‧ ‧ switch

120A, 120B‧‧‧ processor

130A, 130B‧‧‧ logic circuits

140A, 140B‧‧‧ controller

141A, 141B‧‧‧ counter

150‧‧‧Detector

151‧‧‧Low-pass filter

210, 220, 230, 240‧‧

S _M ‧‧‧mask signal

HW_RSTn‧‧‧Main reset signal

S _C ‧‧‧ control signal

S _SR ‧ ‧ reset signal

S _N ‧‧‧Notice signal

OUT ₁₅₀ , OUT _110B ‧‧‧ Output signal

VAL‧‧‧ count value

T1, T2‧‧‧ time points

S311~S315‧‧‧Steps

1A and 1B are schematic views of a memory device of the present invention.

Fig. 2 is a control timing chart of the memory device of Fig. 1B.

Figure 3 is a schematic flow chart of the reset method of the present invention.

Fig. 1A is a schematic view of a memory device of the present invention. As shown, the memory device 100A includes a switch 110A, a processor 120A, a logic circuit 130A, and a controller 140A. The switch 110A determines whether to transmit a main reset signal HW_RSTn to the processor 120A and the logic circuit 130A based on a mask signal S _M . In a possible embodiment, when the mask signal S _M is enabled, the switch 110A does not transmit the main reset signal HW_RSTn to the processor 120A and the logic circuit 130A. When the mask signal S _M is not enabled, the switch 110A transmits the main reset signal HW_RSTn to the processor 120A and the logic circuit 130A.

In a possible embodiment, the switch 110A transmits the main reset signal HW_RSTn according to the level of the mask signal S _M . For example, when the mask signal S _M is at a high level, it indicates that the mask signal S _M is enabled. Therefore, the switch 110A does not transmit the main reset signal HW_RSTn. When the mask signal S _M is at a low level, it indicates that the mask signal S _{M is} not enabled. Therefore, the switch 110A transmits the main reset signal HW_RSTn. In other embodiments, when the mask signal S _M is at a low level, it indicates that the mask signal S _M is enabled. Therefore, the switch 110A does not transmit the main reset signal HW_RSTn. When the mask signal S _M is at a high level, it indicates that the mask signal S _{M is} not enabled. Therefore, the switch 110A transmits the main reset signal HW_RSTn.

The processor 120A is used to control the operation of the logic circuit 130A. In one possible embodiment, processor 120A writes an external data into a memory (not shown) via logic circuit 130A. In a possible embodiment, the memory includes at least a read only memory (ROM) and a random access memory (RAM). In another possible embodiment, the processor 120A reads the data stored in the memory through the logic circuit 130A and provides the read data to an external device (not shown). In a possible embodiment, the external device is independent of the memory device 100A.

In the present embodiment, when the switch 110A outputs the main reset signal HW_RSTn, and the main reset signal HW_RSTn is enabled, the processor 120A generates a reset signal S _SR according to the operational state of the logic circuit 130A. For example, when the main reset signal HW_RSTn is enabled, the processor 120A issues a control signal S _{C for} instructing the logic circuit 130A to perform the work currently being performed, such as a write operation or a read operation. After receiving the control signal S _C , the logic circuit 130A completes the ongoing work and then stops operating.

In a possible embodiment, after the control signal S _{C is} issued, the processor 120A detects whether the logic circuit 130A has stopped operating every fixed time. If the logic circuit 130A has not stopped operating, the processor 120A enables the secondary reset signal _SSR . If logic circuit 130A has ceased to function, processor 120A does not enable secondary reset signal _SSR . In a possible embodiment, when the secondary reset signal S _SR is at a high level, it indicates that the secondary reset signal S _SR is enabled. Conversely, when the secondary reset signal S _SR is at a low level, it indicates that the reset signal S _{SR is} not enabled. In another possible embodiment, when the secondary reset signal S _SR is at a low level, indicating that the secondary reset signal S _SR is enabled, when the secondary reset signal S _SR is at a high level, indicating that the secondary reset signal S _{SR is} not Enable.

In other embodiments, the secondary reset signal _{SSR is} maintained at a fixed level, such as a high level or a low level. When the processor 120A enable reset signal S _SR views, views of the reset signal S _SR transient level will change, thereby making the reset signal S _SR views having at least one positive pulse (positive pulse) or at least a Negative pulse. In this example, the number of pulses is equal to the number of times the processor 120A enables the secondary reset signal _SSR .

The present invention does not limit how the processor 120A knows that the primary reset signal HW_RSTn has been enabled. In this embodiment, the processor 120A determines whether the main reset signal HW_RSTn has been enabled according to the notification signal S _N generated by the controller 140A. In another possible embodiment, the processor 120A directly receives the main reset signal HW_RSTn to determine whether the main reset signal HW_RSTn is enabled.

The present invention does not limit the level at which the main reset signal HW_RSTn is enabled. In a possible embodiment, when the main reset signal HW_RSTn is enabled, the main reset signal HW_RSTn is at a high level. When the main reset signal HW_RSTn is not enabled, the main reset signal HW_RSTn is low level. In another possible embodiment, when the main reset signal HW_RSTn is enabled, the main reset signal HW_RSTn is at a low level. When the main reset signal HW_RSTn is not enabled, the main reset signal HW_RSTn is at a high level. In some embodiments, the level at which the primary reset signal HW_RSTn is enabled may be equal to or not equal to the level at which the secondary reset signal S _SR is enabled. In other embodiments, the level at which the main reset signal HW_RSTn is enabled may be equal to or not equal to the level at which the mask signal S _M is enabled.

The controller 140A generates a mask signal S _M based on the main reset signal HW_RSTn and the secondary reset signal S _SR . For example, when the secondary reset signal S _SR is enabled, it indicates that the logic circuit 130A is operating. Since part of the operation of the logic circuit 130A cannot be interrupted, if the logic circuit 130A is directly reset, it is likely that some of the elements are malfunctioning. Therefore, when the main reset signal HW_RSTn is enabled, the controller 140A determines whether the sub reset signal S _SR is enabled. If the secondary reset signal S _SR is enabled, the controller 140A enables the mask signal S _M to not turn on the switch 110A such that the switch 110A does not transmit the primary reset signal HW_RSTn to the processor 120A and the logic circuit 130A.

However, when the secondary reset signal S _{SR is} not enabled, it indicates that the logic circuit 130A has stopped operating. Therefore, the controller 140A does not enable the masking signal S _M to turn on the switch 110A. At this time, the switch 110A transmits the main reset signal HW_RSTn to the processor 120A and the logic circuit 130A. The processor 120A and the logic circuit 130A perform a reset operation according to the main reset signal HW_RSTn. In one possible embodiment, processor 120A has a logic reset root. The logic reset circuit resets the processor 120A and the logic circuit 130A according to the main reset signal HW_RSTn.

The present invention does not limit the internal architecture of the controller 140A. In one possible embodiment, controller 140A is a counter 141A. Counter 141A may be an up counter or a down counter. When the main reset signal HW_RSTn is enabled, if the secondary reset signal S _SR is not enabled, the counter 141A gradually adjusts a count value. If the secondary reset signal S _SR is enabled, it indicates that the logic circuit 130A has not stopped the operation, and therefore, the count value of the counter 141A is reset to an initial value, so whether the logic circuit 130A can be known by the count value of the counter 141A The action has been stopped.

When the count value of the counter 141A is not equal to a predetermined value, it indicates that the logic circuit 130A has not stopped the operation, so the counter 141A enables the mask signal S _M to not turn on the switch 110A. At this time, the switch 110A does not transmit the main reset signal HW_RSTn to the processor 120A and the logic circuit 130A. However, when the count value of the counter 141A is equal to the preset value, it indicates that the logic circuit 130A has completely stopped the operation, and therefore, the counter 141A does not enable the mask signal S _M to turn on the switch 110A. At this time, the switch 110A transmits the main reset signal HW_RSTn to the processor 120A and the logic circuit 130A. When the processor 120A and the logic circuit 130A receive the main reset signal HW_RSTn, the processor 120A and the logic circuit 130A respectively perform a reset operation for initializing the processor 120A and the register inside the logic circuit 130A.

The present invention does not limit how the counter 141A adjusts the count value. For example, when the counter 141A is an up counter, the counter 141A gradually increments the count value. When the counter 141A is a lower counter, the counter 141A gradually decreases the count value.

Fig. 1B is another schematic view of the memory device of the present invention. Fig. 1B is similar to Fig. 1A except that the memory device 100B of Fig. 1B has a detector 150. The detector 150 receives the main reset signal HW_RSTn for determining whether the time when the main reset signal HW_RSTn is enabled is less than a preset time. For example, when the main reset signal HW_RSTn is enabled for less than the preset time, it indicates that the main reset signal HW_RSTn may be interfered by noise. therefore, The detector 150 does not output the main reset signal HW_RSTn to the switch 110B and the controller 140B. At this time, the switch 110B and the controller 140B are temporarily not in operation.

However, when the main reset signal HW_RSTn is enabled for not less than the preset time, the detector 150 outputs the main reset signal HW_RSTn to the switch 110B and the controller 140B. At this time, the controller 140B determines whether to turn on the switch 110B based on the secondary reset signal S _SR generated by the processor 120B. Since the operation principle of the switch 110B, the controller 140B, the processor 120B, and the logic circuit 130B is the same as that of the switch 110A, the controller 140A, the processor 120A, and the logic circuit 130A of FIG. 1A, the description thereof will not be repeated. The present invention does not limit the circuit architecture of the detector 150. As long as the circuit capable of detecting the time when the main reset signal HW_RSTn is enabled can be used as the detector 150. In a possible embodiment, the detector 150 is a low pass filter 151.

Fig. 2 is a control timing chart of the memory device of Fig. 1B. Symbol OUT ₁₅₀ represents the output signal of detector 150. Symbol OUT _110B represents the output signal of switch 110B. The symbol VAL indicates the count value of the counter 141B. For convenience of explanation, it is assumed that the counter 141B is an up counter.

During the period 210, the main reset signal HW_RSTn is at a low level, indicating that the main reset signal HW_RSTn is enabled. However, since the main reset signal HW_RSTn is enabled for less than a predetermined time, the detector 150 does not output the main reset signal HW_RSTn. In the present embodiment, the output signal of the detector 150 is maintained at a high level, but is not intended to limit the present invention. In other embodiments, when the level of the main reset signal HW_RSTn is enabled, the time when the main reset signal HW_RSTn is enabled is less than a preset time or the main reset signal HW_RSTn is not When possible, the output signal of the detector 150 is maintained at a low level.

During the period 220, the main reset signal HW_RSTn is at a low level, indicating that the main reset signal HW_RSTn is enabled. Since the main reset signal HW_RSTn is enabled for a preset time, the detector 150 outputs the main reset signal HW_RSTn at the time point T1. As shown, at time point T1, the output signal of detector 150 changes from a high level to a low level. At this time, since the detector 150 outputs the main reset signal HW_RSTn, and the main reset signal HW_RSTn is enabled, the counter 141B starts counting. In the present embodiment, the count value of the counter 141B gradually increases from 0. Since the count value of the counter 141B does not reach a predetermined value (e.g., 8), and therefore, at the time point Tl, 141B counter enable mask signal S _M, S _M such that the mask signal is at the high level. Since the mask signal S _M is enabled, the switch 110 ^B does not transmit the main reset signal HW_RSTn.

During periods 230 and 240, processor 120B determines if logic circuit 130B is down. Since the logic circuit 130B has not stopped operating, the processor 120B enables the secondary reset signal _SSR . In this embodiment, the secondary reset signal S _{SR is} maintained at a low level. When the processor 120B enables the secondary reset signal S _SR , the secondary reset signal S _SR has a positive pulse. Since the processor 120B enables the secondary reset signal S _SR twice, the secondary reset signal S _SR has two positive pulses. When the secondary reset signal S _SR has a positive pulse, the count value of the counter 141B is reset to 0, and the count value is re-incremented.

At the time point T2, since the count value of the counter 141B is equal to the preset value, the counter 141B does not enable the mask signal S _M to be masked, so the mask signal S _M changes from the high level to the low level. Since the mask signal S _{M is} not enabled, the switch 110B transmits the main reset signal HW_RSTn to the processor 120B and the logic circuit 130B. The processor 120B and the logic circuit 130B perform a reset operation according to the main reset signal HW_RSTn.

Figure 3 is a schematic flow chart of the reset method of the present invention. The reset method of the present invention is applicable to a memory device for resetting logic circuits in a memory device. First, a count value is adjusted according to a main reset signal, and the logic circuit is stopped after the current work is completed (step S311). In a possible embodiment, a counter is used to adjust the count value. In this example, when the primary reset signal is enabled, the counter begins to increase or decrease a count value. However, when the primary reset signal is not enabled, the counter does not adjust the count value.

In another possible embodiment, when the primary reset signal is enabled and the primary reset signal is enabled for less than a predetermined time, it indicates that the primary reset signal may be interfered by noise. Therefore, the counter does not adjust the count value. However, when the main reset signal is enabled for not less than the preset time, the counter increments the count value.

Next, it is judged whether or not the logic circuit is stopped (step S312). When the logic circuit has not stopped operating, the count value is reset (step S313), and the process returns to step S311 to re-adjust the count value. When the logic circuit stops operating, it is judged whether or not the count value is equal to a predetermined value (step S314). When the count value is equal to the preset value, it indicates that the logic circuit has actually stopped operating, and therefore, the logic circuit is reset (step S315). In a possible embodiment, step S315 is to initialize the data stored by the temporary register inside the logic circuit.

When the main reset signal is enabled, the count value is adjusted. However, as long as the logic circuit is still operating, the count value is reset so that the count value is equal to a start value until the logic circuit stops operating, and the reset count value is stopped. When the count value is no longer reset, the count value gradually approaches a preset value. When the count value is equal to a predetermined value, a main reset signal is issued to the logic circuit for resetting the logic circuit. this At the time, since the logic circuit has stopped operating, the operation of the logic circuit, such as the NAND flash memory, can be avoided.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (10)

A memory device includes: a processor for controlling operation of a logic circuit and determining whether a master reset signal is enabled, wherein when the master reset signal is enabled, the processor is configured according to the logic circuit The operation generates a reset signal; a controller generates a mask signal according to the reset signal; and a switch, when the mask signal is enabled, does not transmit the main reset signal to the logic circuit, when When the mask signal is not enabled, the main reset signal is transmitted to the logic circuit for resetting the logic circuit; and a detector is configured to detect when the main reset signal is enabled. When the main reset signal is enabled for less than a predetermined time, the detector does not output the main reset signal to the switch. The memory device of claim 1, wherein the processor determines whether the main reset signal is enabled according to a level of the main reset signal, when the level of the main reset signal is equal to At a specific level, the processor generates the reset signal according to the operation of the logic circuit, and when the logic circuit is in operation, the processor enables the reset signal. The memory device of claim 1, wherein the reset signal has a positive pulse when the reset signal is enabled. The memory device of claim 1, wherein the reset signal has a negative pulse when the reset signal is enabled. The memory device of claim 1, wherein the level at which the reset signal is enabled is equal to the specific level. The memory device of claim 1, wherein the reset signal The level at which it is enabled is not equal to the specific level. The memory device of claim 1, wherein the level at which the occlusion signal is enabled is equal to the specific level. The memory device of claim 1, wherein the level at which the occlusion signal is enabled is not equal to the specific level. The memory device of claim 1, wherein the processor performs a reset operation with the logic circuit when the switch transmits the main reset signal to the logic circuit. The memory device of claim 9, wherein the processor comprises: a logic reset circuit for resetting the processor and the logic circuit.