TWI654518B - Method for storing error status information and server using the same - Google Patents

Abstract

An error state storage method is performed by a server, the server comprising a processing unit, a basic input/output system, at least one peripheral device, and a chip set including at least one non-volatile memory. The method includes: the processing unit generates a processing interrupt request according to a peripheral error trigger, the peripheral error triggering is related to at least one of the at least one peripheral device being in an error state; the basic input output system is according to the processing unit Processing an interrupt request, recording status data of each of the at least one peripheral device, and performing a program stored in the non-volatile memory of the chip set, the status data including a device identification code and a pair of device identification codes Type of status. With the error state storage method, the status data of each of the at least one peripheral device can be saved to help the user find out the cause of the error of at least one of the at least one peripheral device, so that the error can be more quickly Troubleshoot.

Description

Error state storage method and server

The invention relates to a storage method and device, in particular to an error state storage method and a server.

In the course of the operation of the existing server, an error such as a peripheral device interconnection device (PCI device) may be generated, and the peripheral component interconnection device is, for example, a network card, a graphics processing card, a video acceleration card, etc., and the like An error condition is recorded in its status register when an error occurs in the peripheral component interconnect. In order to improve system reliability, a basic input/output system of the server is usually configured to perform a system management interrupt (Program Management Interruption) program to read the state temporary storage of the peripheral component interconnection device when such an error occurs. And record the error status.

However, if the user needs to perform maintenance error detection, it may not be possible to see the cause of the error at a glance only through the error state of the peripheral component interconnection device recorded by the basic input/output system. Experience judgment, or time-consuming detection of all peripheral component interconnection devices one by one, in order to find the place of error. In addition, the system management interrupt program of the basic input/output system is generally designed to clear the state data of all state registers after the basic input/output system records the error state, thereby making it difficult for the user to interact with the peripheral components in which the error occurred. The device is debugging and diagnosing the cause.

Accordingly, it is an object of the present invention to provide an error state storage method.

Therefore, the error state storage method of the present invention comprises a processing unit, at least one peripheral device, a basic input/output system, a control chip set, and a chip set electrically connected to the control chip set, and an electrical connection. a memory of the chipset, the chipset including at least one non-volatile memory and a substrate management controller, the error state storage method comprising a step (A), a step (B), a step (C), and a Step (D).

The step (A) is that the processing unit generates a processing interrupt request according to a peripheral error trigger, and the peripheral error trigger is related to at least one of the at least one peripheral device being in an error state.

The step (B) is that the basic input/output system stores the state data of each of the at least one peripheral device to the memory according to the processing interrupt request of the processing unit, the state data includes a device identification code and a pair The type of status of the identification code should be installed.

The step (C), the basic input/output system sends a data ready command via the control chipset to the substrate management controller of the chipset, the data prepared command indicating that the status data of each of the at least one peripheral device has been Write to this memory.

In the step (D), the substrate management controller prepares a command according to the data, to access state data of each of the at least one peripheral device from the memory, and write the non-volatile memory of the chip set. .

Another object of the present invention is to provide a server that can implement the error state storage method.

Thus, the server of the present invention comprises a processing unit, at least one peripheral device, a basic input/output system, a control chip set electrically connected to the basic input/output system, a chip set electrically connected to the control chip set, and an electrical connection The memory of the wafer set.

The chip set includes at least one non-volatile memory and a substrate management controller.

The processing unit generates a processing interrupt request according to a peripheral error trigger, the peripheral error triggering being related to at least one of the at least one peripheral device being in an error state.

The basic input/output system stores, according to the processing interrupt request of the processing unit, status data of each of the at least one peripheral device to the memory, the status data including a device identification code and a pair of device identification codes. The type of status.

Wherein the basic input/output system sends a data ready command via the control chipset to the substrate management controller of the chipset, the data prepared command indicating that the status data of each of the at least one peripheral device has been written to the Memory.

The baseboard management controller prepares a command according to the data to access state data of each of the at least one peripheral device from the memory and write the non-volatile memory of the chipset.

The effect of the present invention is to trigger the basic input/output system to store state data of each of the at least one peripheral device to the memory by detecting that at least one of the at least one peripheral device is in an error state, And the substrate management controller accesses the status data from the memory and stores the status data into the non-volatile memory, and the status data of each of the at least one peripheral device can be saved to help the user find the at least one periphery. At least one of the devices has a cause of error so that debugging can be performed more quickly.

Referring to FIG. 1, an embodiment of a server of the present invention includes a peripheral connection busbar 1, a peripheral device 2, a control chipset 3, a chipset 4, and a basic input/output system (Basic Input/Output System). , a memory 6, and a processing unit 7.

The peripheral connection bus 1 is, for example, a Peripheral Component Interconnect (PCI) bus, or is, for example, a high-speed Peripheral Component Interconnect Express (PCIe).

The peripheral device 2 is a peripheral device interconnecting device (PCI device) electrically connected to the peripheral connection bus bar 1 and is, for example, a network card, a graphics processing chip, a video acceleration chip, or the like. For convenience of explanation, only one peripheral device 2 is illustrated in FIG. 1 as an illustration, but the number may also be two, three, etc., and is not limited to the one shown. The peripheral device 2 has a state register (not shown), and when the device is in normal operation, the peripheral device 2 records a normal operating state in the state register, and when an operation error occurs, a record is recorded. The error status is in this status register. It should be noted that the error state mentioned in this embodiment is selected from a common bit error (PERR), a system error (SERR), and a correctable peripheral component interconnection error (correctable PCI). Error), one of the uncorrectable PCI error, a fatal PCI error.

The chip set 4 includes a peripheral device 41, a baseboard management controller 42 and a non-volatile memory 44. In the embodiment, the non-volatile memory 44 is located in the chip set 4. The substrate management controller 42 is internal, but not limited thereto. The peripheral device 41 is connected to the peripheral connection busbar 1, and is, for example, an on-board video graphics array (VGA) chip, and has a state register (not shown), the peripheral device When the operation is normal, the normal operation state is recorded in the state register, and when an operation error occurs, the error state is recorded in the state register. The baseboard management controller 42 is configured to monitor operating conditions of the server such as fan speed, supply voltage, system temperature, etc., and the non-volatile memory 44 of the baseboard management controller 42 includes a system event log (system event log) And a system log 45 for recording a device ID and a pair of device identifiers. The system log is used to record, for example, the status data of the peripheral device 2 and the peripheral device 41. The status data includes a device identification code and a status type of the pair of device identification codes, and the status category may be One of the normal operating state and the error state.

The control chipset 3 is a Platform Controller Hub (PCH), for example, a south bridge chip, and the control chip set 3 is electrically connected to the peripheral connection busbar 1, the chipset 4, and the basic input/output system. 5. When the control chip group 3 is connected to the bus bar 1 via the periphery, the state register of the peripheral device 2 and/or the state register of the peripheral device 41 are read, and the peripheral device 2 and/or When the peripheral device 41 is in the wrong state, a peripheral error trigger can be generated to indicate that any one of the peripheral devices connected to the peripheral connection busbar 1 is in the error state.

The memory 6 includes a state storage block 61. The state storage block 61 stores data for the peripheral device 41 (that is, the VGA chip) allocated to the chip set 4 in the memory 6, and can be used for the substrate management. The controller 42 accesses. The memory 6 is, for example, a dynamic random access memory (DRAM) for storing data in the peripheral device 41 (that is, the VGA chip), a second generation double data rate (DDR2) memory, or, for example, a first Three generations of double data rate (DDR3) memory.

The processing unit 7 is a central processing unit of the server, electrically connected to the peripheral connection busbar 1 and includes a north bridge wafer 71 for processing high speed signals, such as high speed peripheral component interconnection (PCIe) interface signals, etc. Also responsible for communication with the control chipset 3. The north bridge wafer 71 also has a function similar to the control chip group 3, and when it is connected to the bus bar 1 via the periphery, the peripheral device 2 and/or the state register of the peripheral device 41 are read, and the peripheral device is known. 2 and \ or when the peripheral device 41 is in the wrong state, a peripheral error trigger can be generated to indicate that any peripheral device connected to the peripheral connection busbar 1 is in the error state.

The basic input/output system 5 is electrically connected to the control chip set 3 and has a system management interrupt handler 51. When the processing unit 7 receives the peripheral error trigger from the control chip set 3, or the peripheral error trigger from the north bridge wafer 71, enters a system management mode (SMM), and transfers the system control right. The system management interrupt processing module 51 of the basic input/output system 5 determines the cause of the interruption by the system management interrupt processing module 51. The system management interrupt processing module 51 can be, for example, a program.

Referring to FIG. 2, an embodiment of the error state storage method of the present invention is executed in the server shown in FIG. 1, and the method includes the following steps.

First, in step (A), the processing unit 7 generates a processing interrupt request based on a peripheral error trigger. As described above, the peripheral error trigger is generated by the control chip group 3 or generated by the north bridge wafer 71 when the peripheral device 2 is in the error state. The processing interrupt request is a System Management Interruption (SMI). At this time, the processing unit 7 enters the System Management Mode (SMM) and transfers system control rights to the basic input/output system 5. The system manages the interrupt processing module 51.

Next, in step (E), the system management interrupt processing module 51 of the basic input/output system 5 responds to the processing interrupt request of the processing unit 7, and records the peripheral error data, that is, the peripheral error data is in the periphery of the error state. The status data of the device, and includes a device identification code and an error status of a pair of device identification codes. For example, when the peripheral device 2 operates abnormally, the peripheral error data includes the device identification code of the peripheral device 2, and the corresponding error state, such as the aforementioned homotopic error, the system error, and the correctable peripheral component mutual. A fault, a non-correctable peripheral component interconnection error, and one of the fatal peripheral component interconnection errors. In this embodiment, the size of the peripheral error data is about 12 bytes.

Next, in step (F), the system management interrupt processing module 51 of the basic input/output system 5 transmits the peripheral error data via the control wafer set 3 to the substrate management controller 42 of the wafer set 4.

Next, in step (G), the substrate management controller 42 writes the peripheral error data into the system event log 43 of the non-volatile memory 44.

Next, in step (B), the system management interrupt processing module 51 of the basic input/output system 5 stores the status data of each peripheral device in the memory 6 based on the processing interrupt request. This step (B) includes the following sub-steps.

In step (B0), the system management interrupt processing module 51 of the basic input/output system 5 records the status data of each peripheral device 2. In detail, the basic input/output system 5 scans all peripheral devices connected to the peripheral connection busbar 1 to read status data of each peripheral device (the peripheral device 2 and the peripheral device 41 in this example). And temporarily stored in the processing unit 7, for example, an external dynamic random access memory (DRAM) (not shown). For example, the peripheral device 2 operates abnormally, and the peripheral device 41 is in normal operation. The status data recorded by the basic input/output system 5 includes the device identification code of the peripheral device 2 and the corresponding error state, and the peripheral device 41. The device identification code corresponds to the normal operating state.

In step (B1), the system management interrupt processing module 51 of the basic input/output system 5 obtains a memory address data, and the memory address data is related to the address of the state storage block 61 in the memory 6. In detail, the memory address data is stored in a memory mapped I/O register (MMIO register) (not shown) of the peripheral device 41, and the memory address data is At the time of power-on, the basic input/output system allocates the address of the peripheral device 41 by using the memory address mapping technology, and the memory address data indicates the start address and access of the state storage block 61 of the memory 6. range.

Step (B2), the system management interrupt processing module 51 of the basic input/output system 5 selects the external dynamic random access memory (DRAM) of the processing unit 7 according to the memory address data (not shown). The status data of each of the peripheral devices (the peripheral device 2 and the peripheral device 41 in this example) temporarily stored in the medium is copied to the state storage block 61 of the memory 6. Preferably, the basic input/output system 5 determines whether the size of the status data is within the access range of the status storage block 61 indicated by the memory address data, and if it is within the access range, The status data is once stored in the status storage block 61 of the memory 6. If the access range is exceeded, the status storage block 61 is stored in multiple times, and each time the amount of data conforming to the access range is stored.

Next, in step (C), the system management interrupt processing module 51 of the basic input/output system 5 sends a data prepared command via the control chipset 3 to the baseboard management controller 42, the data ready command indicating each The status data of a peripheral device 2 has been written into the state storage block 61 of the memory 6.

Next, in step (D), the substrate management controller 42 of the wafer set 4 has prepared a command according to the data to access each peripheral device from the state storage block 61 of the memory 6 (in this example The status information of the peripheral device 2 and the peripheral device 41) is written into the system log 45 of the non-volatile memory 44. Preferably, the basic input/output system 5 determines whether the state data of each peripheral device (the peripheral device 2 and the peripheral device 41 in this example) has been completely copied to the memory 6 according to the size of the state data. Status storage block 61. If the result of the determination is no, returning to step (B2), the unrepeated state data is stored in the state storage block 61 of the memory 6. If the result of the determination is yes, the peripheral device 2, the periphery The status data of the status register of the device 41 is cleared.

It can be seen from the above description that the error storage method of the present invention can store the peripheral error data to the substrate management controller 42 by the system management interrupt processing module 51 of the basic input/output system 5 when an error occurs in at least one peripheral device. a system event log 43, and storing status data of each peripheral device to the memory 6, and the substrate management controller 42 stores the status data of each peripheral device to the system log 45 of the non-volatile memory 44, that is, The system management interrupt processing module 51 saves the peripheral error data and the status data of each peripheral device before the status data of each state device of the peripheral device 2 is cleared, to assist the user in determining the error when the error occurs. Whether it is triggered by a problem with other peripheral devices, so that debugging can be performed more quickly, and therefore, the object of the present invention can be achieved.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and the simple equivalent changes and modifications made by the scope of the patent application and the patent specification of the present invention are It is still within the scope of the invention patent.

1‧‧‧ peripheral connection bus

5‧‧‧Basic input and output system

2‧‧‧ peripheral devices

51‧‧‧System Management Interruption Processing Module

3‧‧‧Control chipset

6‧‧‧ memory

4‧‧‧ Chipset

61‧‧‧ State storage block

41‧‧‧ Peripheral devices

7‧‧‧Processing unit

42‧‧‧Base Management Controller

71‧‧‧ North Bridge Chip

43‧‧‧System event log

A~G‧‧‧ steps

44‧‧‧ Non-volatile memory

B0~B2‧‧‧ substeps

45‧‧‧System log

Other features and advantages of the present invention will be apparent from the embodiments of the present invention, wherein: Figure 1 is a block diagram illustrating an embodiment of the server of the present invention; and Figure 2 is a flow chart illustrating An embodiment of the error state storage method of the present invention.

Claims (9)

An error state storage method is performed by a server, the server includes a processing unit, at least one peripheral device, a basic input/output system, a control chip set electrically connected to the basic input/output system, and an electrical connection of the control chip a set of chips, and a memory electrically connected to the chip set, the chip set including at least one non-volatile memory and a substrate management controller, the error state storage method comprising: (A) the processing unit according to a periphery The error triggering generates a processing interrupt request, wherein the peripheral error triggering is related to at least one of the at least one peripheral device being in an error state; (B) the basic input output system is configured to interrupt the request according to the processing unit The status data of each of the peripheral devices is stored in the memory, the status data includes a device identification code and a status category of the pair of device identification codes; (C) the basic input/output system sends a data ready command via Controlling the chipset to the substrate management controller of the chipset, the data has prepared a command to indicate the at least The status data of each of the peripheral devices has been written to the memory; and (D) the substrate management controller has prepared a command based on the data to access each of the at least one peripheral device from the memory. State data and write to the non-volatile memory of the chipset; (E) the basic input/output system records a peripheral error data according to the processing interrupt request of the processing unit, and the peripheral error data includes a device identification code And a pair of error states that should be the device identification code; and (F) The basic input/output system transmits the peripheral error data via the control chip set to the substrate management controller of the chip set. The error state storage method of claim 1, further comprising: (G) the substrate management controller writing the peripheral error data from the basic input/output system to one of the non-volatile memory of the chipset System event log. The error state storage method according to Item 1, wherein in the step (D), the substrate management controller writes the state data of each of the at least one peripheral device to the non-volatile portion of the chip set. A system log of sexual memory. In the error state storage method of claim 1, the chipset of the server further includes a peripheral device, and the memory of the server has a peripheral device allocated to the chipset for storing data and can be used for the substrate. Managing a state storage block accessed by the controller, wherein the step (B) comprises (B0) the basic input output system recording status data of each of the at least one peripheral device, (B1) the basic input output system Obtaining a memory address data, wherein the memory address data is related to the state storage block of the memory, and (B2) the basic input/output system copies each of the at least one peripheral device according to the memory address data The status data is in the state storage block of the memory. The error state storage method of claim 1, the processing unit comprising a north bridge chip, wherein in the step (A), the peripheral error touch The hair is generated by one of the north bridge wafer of the processing unit and the control chip set. The error state storage method according to Item 1, wherein in the step (A), the processing interrupt request generated by the processing unit is a System Management Interruption (SMI), and the processing is The unit enters a System Management Mode (SMM). A server comprising: at least one peripheral device; a basic input/output system; a control chip set electrically connected to the basic input/output system; a chip set electrically connected to the control chip set and including at least one non-volatile memory And a substrate management controller; a memory that electrically connects the chip set; and a processing unit that generates a processing interrupt request according to a peripheral error trigger, the peripheral error trigger being related to at least one of the at least one peripheral device One is in an error state; wherein the basic input/output system stores the state data of each of the at least one peripheral device to the memory according to the processing interrupt request of the processing unit, the state data includes a device identification code and a pair of state types of the device identification code; wherein the basic input/output system sends a data ready command to control the chipset to the substrate management controller of the chipset via the control chip set, the data has been Preparing a command indicating that status data of each of the at least one peripheral device has been written to the memory; wherein the baseboard management controller has prepared a command based on the data to access the at least one peripheral device from the memory Each of the status data is written to the non-volatile memory of the chip set; the basic input/output system further records a peripheral error data according to the processing interrupt request of the processing unit, and the peripheral error data includes a device identification code And an error status of the pair of device identification codes; the basic input/output system transmits the peripheral error data via the control chip set to the substrate management controller of the chip set. The server of claim 7, wherein the non-volatile memory of the chipset of the server has a system event log; the baseboard management controller writes the peripheral error data from the basic input/output system The system event log into the non-volatile memory of the chipset. The server of claim 7, wherein the server chipset further comprises a peripheral device, and the memory of the server has a peripheral device assigned to the chip set for storing data and for the substrate a state storage block accessed by the controller, the non-volatile memory of the chipset of the server having a system log; the basic input output system records status data of each of the at least one peripheral device, and obtains Corresponding to the memory address data of the state storage block, the state data of each of the at least one peripheral device is copied in the state storage block of the memory; The substrate management controller writes the status data of each of the at least one peripheral device to the system log of the non-volatile memory of the chip set.