TWI653797B - Esd protected integrated circuit and esd detection circuit - Google Patents

Abstract

The present invention provides an ESD protection integrated circuit and an ESD detection circuit. The ESD protection integrated circuit includes a functional circuit coupled to the first power supply voltage and the second power supply voltage, the functional circuit including at least one functional package ball, and the ESD detection circuit coupled to the second power supply voltage, ESD The detection circuit is not coupled to the first supply voltage and is not coupled to at least one functional package ball of the functional circuit. The present invention can reduce the time cost of ESD failure analysis and can also be used to improve ESD protection during IC assembly or testing.

Description

ESD protection integrated circuit and ESD detection circuit

The present invention relates to an Electrostatic Discharge (ESD) detection circuit and an ESD protection integrated circuit (IC) to which the ESD detection circuit is applied.

Modern high-density ICs are susceptible to damage from ESDs from charged bodies (human or other), especially when charged bodies contact ICs. Electrostatic discharge can cause damage to semiconductor devices and affect the normal function of the IC.

ESD damage occurs when the amount of charge exceeds the ability to pass the electrical conduction path of the IC. Typical ESD failure mechanisms include thermal runaway caused by junction shorting in the metal-oxide-semiconductor (MOS) background and dielectric breakdown caused by gate junction short-circuit (dielectric breakdown) ).

The IC may be damaged by ESD events during manufacturing, assembly, testing, or system applications. Therefore, it is a necessary goal for IC designers to improve the ESD protection of integrated circuits during the design phase to increase ESD sensitivity.

In view of this, the present invention provides an ESD protection integrated circuit and an ESD detection circuit to solve the above problems.

According to at least one embodiment, an ESD protection integrated circuit is provided, including a functional circuit and an ESD detection circuit coupled to a first supply voltage and a second supply voltage, the functional circuit including at least one functional package ball, and The ESD detection circuit is coupled to the second supply voltage, the ESD detection circuit is not coupled to the first supply voltage and is not coupled to the at least one functional package ball of the functional circuit.

In accordance with at least one embodiment, an ESD detection circuit is provided for use in an ESD protection integrated circuit that includes a function having at least one functional package ball and coupled to a first supply voltage and a second supply voltage a circuit, the ESD detection circuit includes: at least one ESD package ball, the ESD package ball of the ESD detection circuit is not coupled to the function package ball of the function circuit and is not coupled to the first power voltage; a discharge path coupled between the ESD package ball and the second supply voltage for discharging an ESD stress event, the plurality of discharge paths having different discharge currents from each other; and an ESD indicating circuit coupled to the Between the ESD package ball and the second supply voltage, the ESD indicating circuit is in an open state associated with ESD pass or in a short circuit condition associated with an ESD failure.

The time cost of ESD failure analysis can be reduced by the present invention and can also be used to improve ESD protection during IC assembly or testing.

These and other objects of the present invention will be apparent from the following detailed description of the preferred embodiments.

100‧‧‧ESD Protection IC

110, 110A, 110B, 110C, 110D‧‧‧ ESD detection circuit

120_1, 120_N‧‧‧ circuits

120‧‧‧Functional circuit

VDD‧‧‧High power supply voltage

VSS‧‧‧Low supply voltage

210, 310, 410, 510‧‧‧ESD indicating circuit

D1, D2, D3‧‧‧ diode

P1, P2‧‧‧ discharge path

MN1, MN2, MN3‧‧‧ NMOS transistor

MP1, MP2, MP3‧‧‧ PMOS transistors

The invention will be more fully understood by reading the following detailed description and embodiments, which are illustrated by the accompanying drawings in which: FIG. 1 shows a schematic block diagram of an ESD protection IC in accordance with an embodiment of the present invention.

Figures 2 through 5 illustrate an ESD detection circuit in accordance with various embodiments of the present invention. In the following detailed description, numerous specific details are set forth in the However, it is apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments illustrated in the drawings.

The following description is of a preferred embodiment of the invention. The following examples are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the present invention. Certain terms are used throughout the specification and claims to refer to particular components. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same components by different nouns. This specification and the scope of the patent application do not use the difference of the names as the means for distinguishing the components, but the difference in function of the components as the basis for the difference. The scope of the invention should be determined with reference to the appended claims. The terms "comprising" and "including" as used in the following description and claims are intended to be interpreted as "included, but not limited to". In addition, surgery The term "coupled" means an indirect or direct electrical connection. Thus, if a device is described as being coupled to another device, it is meant that the device can be directly electrically connected to the other device or indirectly electrically connected to the other device through other means or means.

The term "substantially" or "substantially" as used herein refers to an acceptable range, and those skilled in the art can solve the technical problems to be solved and substantially achieve the desired technical effect. For example, "substantially equal" refers to a manner in which a person of ordinary skill in the art can accept a certain degree of error with "completely equal" without affecting the correctness of the result.

Figure 1 shows a functional block diagram of an ESD protection IC 100 in accordance with one embodiment of the present invention. As shown in FIG. 1, the ESD protection IC 100 includes an ESD detection circuit 110 and a function circuit 120. The ESD detection circuit 110 includes package balls (ie, ESD package balls) 0-1, . . . 0-a ("a" is an integer greater than or equal to one). The functional circuit 120 includes circuits 120-1, ... 120-N (N is an integer greater than or equal to 1). The circuit 120-1 of the functional circuit 120 includes package balls (i.e., functional package balls) 1-1, ... 1-b ("b" is an integer greater than or equal to 1). The circuit 120-N of the functional circuit 120 includes package balls N-1, . . . N-n ("n" is an integer greater than or equal to one).

As shown in FIG. 1, the package balls 0-1, ... 0-a of the ESD detection circuit 110 are not coupled to the high power supply voltage VDD. The package balls 1-1, . . . N-n of the functional circuit 120 are coupled to a high supply voltage VDD (also referred to as a first supply voltage), a signal pin, or a ground. Also, at least one of the package balls 1-1, . . . N-n of the functional circuit 120 is coupled to the high supply voltage VDD, and the other package balls may be coupled to the signal pins or to ground. Further, the package balls 0-1, . . . , 0-a of the ESD detection circuit 110 are not coupled to the package balls 1-1, . . . N-n of the function circuit 120. However, the ESD detection circuit 110 and the function circuit 120 share a low power supply voltage VSS (also referred to as a second power supply voltage).

In normal operation (ie, no ESD stress event occurs), the functional circuit 120 is Normal, and the equivalent resistance of the ESD detection circuit 110 is above the resistance threshold (eg, but not limited to, the normal equivalent resistance of the ESD detection circuit 110 can be several thousand ohms). That is, if the ESD detection circuit 110 is not impacted by an ESD stress event that is higher than the ESD protection threshold of the ESD detection circuit, the ESD detection circuit 110 is in an open state (ie, ESD pass). ).

When an ESD stress event occurs, the ESD detection circuit 110 will discharge the ESD stress event to protect the functional circuit 120. However, if the ESD stress event ESD exceeds the ESD protection threshold of the ESD detection circuit 110, the ESD detection circuit 110 will be damaged and thus the equivalent resistance of the ESD detection circuit 110 will be very low (eg, but not limited to 1 ohm). That is, if the ESD detection circuit 110 has been struck by an ESD stress event that is higher than the ESD protection threshold of the ESD detection circuit, the equivalent resistance of the ESD detection circuit 110 may be lower than the resistance threshold, and the ESD detection circuit 110 is in a short-circuit state (short State) (for example, ESD failed).

Therefore, by coupling the package ball of the ESD detection circuit 110 to the ESD test pin (not shown) for reading the equivalent resistance of the ESD detection circuit 110, it can be determined whether the ESD detection circuit 110 is damaged (due to ESD stress) The event is above the protection threshold). That is to say, if the equivalent resistance of the ESD detecting circuit 110 is higher than the resistance threshold, the ESD detecting circuit 110 is normal. If the equivalent resistance of the ESD detection circuit 110 is below the resistance threshold, the ESD detection circuit 110 is already damaged due to the very high ESD stress event.

Figures 2 through 5 illustrate an ESD detection circuit in accordance with several possible embodiments of the present invention. Refer now to Figure 2. As shown in FIG. 2, in accordance with an embodiment of the present invention, ESD detection circuit 110A includes discharge paths P1, P2 and ESD indicating circuit 210. The discharge paths P1, P2 are connected in parallel.

The discharge path P1 includes a diode D1. The diode D1 is coupled between the package ball 0-1 and the low power supply voltage VSS. The discharge path P1 discharges the negative ESD stress voltage at the ESD protection IC.

The discharge path P2 includes diodes D2 and D3 connected in series. The diode D2 is coupled between the package ball 0-1 and one end of the diode D3. The diode D3 is coupled between one end of the diode D2 and the low power supply voltage VSS. The discharge path P2 discharges the positive ESD stress voltage at the ESD protection IC. Therefore, the discharge paths P1 and P2 have discharge directions different from each other. Also, the discharge paths P1 and P2 have opposite discharge directions.

The ESD indicating circuit 210 is implemented by, for example, but not limited to, an NMOS transistor MN1. The NMOS transistor MN1 includes a first end coupled to the package ball 0-1 (such as, but not limited to, a gate), a second end and a third end each coupled to the low supply voltage VSS (such as, but not limited to, a source and Drain).

Under normal circumstances, there is no ESD stress event in the ESD protection IC. Therefore, under normal conditions, there is no discharge current on the discharge paths P1 and P2, and the ESD indicating circuit 210 is turned off. Therefore, under normal circumstances, the ESD indicating circuit 210 has a high equivalent resistance.

If the ESD stress event occurring in the ESD protection IC is lower than the protection threshold of the ESD detection circuit 110A, at least one of the discharge paths P1 and P2 conducts to discharge the ESD stress event for protection of the ESD protection IC. However, if the ESD stress event is too high and exceeds the protection threshold of the ESD detection circuit 110A, the NMOS transistor MN1 of the ESD indication circuit 210 will be damaged (even if an excessively high ESD stress event is discharged through the discharge path P1 or P2), The equivalent resistance of the NMOS transistor MN1 will be very low (ie, ESD is disabled).

Therefore, by checking the equivalent resistance of the ESD detecting circuit 110A, it can be determined whether a high ESD stress event has occurred.

Refer now to Figure 3. As shown in FIG. 3, in accordance with an embodiment of the present invention, ESD detection circuit 110B includes discharge paths P1, P2 and ESD indicating circuit 310. The discharge paths P1 and P2 can be similar to those in FIG. 2 and will not be described again here.

The ESD indicating circuit 310 is implemented by, for example, but not limited to, a plurality of cascaded NMOS transistors MN2 and MN3. NMOS transistor MN2 includes a floating first end (such as, but not limited to, a gate), a second end coupled to package ball 0-1 (such as, but not limited to, a drain), and a third coupled to NMOS transistor MN3 End (such as but not limited to source). The NMOS transistor MN3 includes a first end (such as, but not limited to, a gate) coupled to the low supply voltage VSS, a second end (such as, but not limited to, a drain) coupled to the third end of the NMOS transistor MN2, and coupled To the third end of the low supply voltage VSS (such as but not limited to a source).

Under normal circumstances, there is no ESD stress event in the ESD protection IC. Therefore, under normal conditions, there is no discharge current on the discharge paths P1 and P2, and the ESD indicating circuit 310 is turned off (i.e., the NMOS transistors MN2 and MN3 are turned off). Therefore, under normal circumstances, the ESD indicating circuit 310 has a high equivalent resistance (ie, ESD pass).

If the ESD stress event occurring in the ESD protection 1C is lower than the protection threshold of the ESD detection circuit 110B, at least one of the discharge paths P1 and P2 is electrically discharged to discharge the ESD stress event for protecting the ESD protection IC. However, if the ESD stress event is too high and exceeds the protection threshold of the ESD detection circuit 110B, the NMOS transistors MN2 and MN3 of the ESD indication circuit 310 will be damaged (even if an excessively high ESD stress event is discharged through the discharge path P1 or P2) Therefore, both the NMOS transistors MN2 and MN3 will have a drain-source short circuit. Therefore, if the ESD stress event is too high and exceeds the protection threshold of the ESD detection circuit 110B, the equivalent resistance of the NMOS transistors MN2 and MN3 will be very low (ie, ESD is disabled).

Therefore, by checking the equivalent resistance of the ESD detecting circuit 110B, it can be determined whether a high ESD stress event has occurred.

Refer now to Figure 4. As shown in FIG. 4, in accordance with an embodiment of the present invention, ESD detection circuit 110C includes discharge paths P1, P2 and ESD indicating circuit 410. The discharge paths P1 and P2 can be similar to those in FIG. 2 and will not be described again here.

The ESD indicating circuit 410 is implemented by, for example, but not limited to, a plurality of cascaded PMOS transistors MP1 and MP2. A first end of the PMOS transistor MP1 (such as but not limited to a gate) is coupled to the package ball 0-1, and a second end (such as but not limited to a drain) is coupled to the PMOS transistor MP2, the third end (eg, but Not limited to the source) is coupled to the package ball 0-1 and the first end of the PMOS transistor MP1. A first end (such as but not limited to a gate) of the PMOS transistor MP2 is floating, and a second end (such as but not limited to a drain) is coupled to the low power supply voltage VSS, the third end (such as but not limited to a source) It is coupled to the second end of the PMOS transistor MP1.

Under normal circumstances, there is no ESD stress event in the ESD protection IC. Therefore, under normal conditions, there is no discharge current on the discharge paths P1 and P2, and the ESD indicating circuit 410 is turned off (i.e., the PMOS transistors MP1 and MP2 are turned off). Therefore, under normal circumstances, the ESD indicating circuit 410 has a high equivalent resistance.

If the ESD stress event occurring in the ESD protection IC is lower than the protection threshold of the ESD detection circuit 110C, at least one of the discharge paths P1 and P2 conducts to discharge the ESD stress event for protection of the ESD protection IC. However, if the ESD stress event is too high and exceeds the protection threshold of the ESD detection circuit 110C, the PMOS transistors MP1 and MP2 of the ESD indication circuit 410 will be damaged (even if an excessively high ESD stress event is discharged through the discharge path P1 or P2) Therefore, both the PMOS transistors MP1 and MP2 will have a drain-source short circuit. So if The ESD stress event is too high and exceeds the protection threshold of the ESD detection circuit 110C, and the equivalent resistance of the PMOS transistors MP1 and MP2 will be very low.

Therefore, by checking the equivalent resistance of the ESD detecting circuit 110C, it can be determined whether a high ESD stress event has occurred.

Refer now to Figure 5. As shown in FIG. 5, in accordance with an embodiment of the present invention, ESD detection circuit 110D includes discharge paths P1, P2 and ESD indicating circuit 510. The discharge paths P1 and P2 can be similar to those in FIG. 2 and will not be described again here.

The ESD indicating circuit 510 is implemented by, for example, but not limited to, a PMOS transistor MP3. A first end of the PMOS transistor MP3 (such as but not limited to a gate) is coupled to the low supply voltage VSS, and the second end and the third end (such as but not limited to the drain and the source) are coupled to the package ball 0- 1.

Under normal circumstances, there is no ESD stress event in the ESD protection IC. Therefore, under normal conditions, there is no discharge current on the discharge paths P1 and P2, and the ESD indicating circuit 510 is disconnected. Therefore, under normal circumstances, the ESD indicating circuit 510 has a high equivalent resistance.

If the ESD stress event occurring in the ESD protection IC is lower than the protection threshold of the ESD detection circuit 110D, at least one of the discharge paths P1 and P2 conducts to discharge the ESD stress event for protection of the ESD protection IC. However, if the ESD stress event is too high and exceeds the protection threshold of the ESD detection circuit 110D, the PMOS transistor MP3 of the ESD indication circuit 510 will be damaged (even if an excessively high ESD stress event is discharged through the discharge path P1 or P2), The equivalent resistance of the PMOS transistor MP3 will be very low.

Therefore, by checking the equivalent resistance of the ESD detecting circuit 110D, it can be determined whether a high ESD stress event has occurred.

In other possible implementations of the invention, the ESD protection IC may include a protection threshold Two or more ESD detection circuits having different values from each other. For example, without limitation, the ESD protection IC can include two ESD detection circuits with protection thresholds of 125V and 250V, respectively. Therefore, when an ESD stress event of 100V occurs, both ESD detection circuits have a higher equivalent resistance. When an ESD stress event between 125V and 250V (such as but not limited to 200V) occurs, one of the ESD detection circuits has a higher equivalent resistance and the other ESD detection circuit has a low equivalent resistance. Both ESD detection circuits have lower equivalent resistance when an ESD stress event above 250V occurs.

In an embodiment of the invention, the ESD protection threshold of the ESD detection circuit may be determined based on the size of the diode of the discharge path and the proportional size of the transistor of the ESD indicating circuit. Therefore, the ESD protection threshold of the ESD detection circuit can be changed by changing the size of the diode of the discharge path or the proportional size of the transistor of the ESD indicating circuit.

In other embodiments of the invention, the ESD detection circuit may include a discharge path (ie, the ESD detection circuit does not include an ESD indication circuit), and the ESD protection threshold of the ESD detection circuit may be determined based on the size of the diode of the discharge path. Therefore, the ESD protection threshold of the ESD detection circuit can be changed by changing the size of the diode of the discharge path.

In other embodiments of the invention, the ESD detection circuit may include an ESD indicating circuit (ie, the ESD detecting circuit does not include a discharge path), and the ESD protection threshold of the ESD detecting circuit may be determined based on a proportional size of a transistor of the ESD indicating circuit. Therefore, the ESD protection threshold of the ESD detection circuit can be changed by changing the proportional size of the transistor of the ESD indicating circuit.

Embodiments of the present invention have fast ESD testing capabilities because it is possible to determine if an ESD test passes or fails by examining the equivalent resistance of the ESD detection circuit. Therefore, the present invention The time cost of ESD failure analysis can be reduced. In addition, embodiments of the invention may also be used to improve ESD protection during IC assembly or testing.

The embodiments of the present invention and its advantages are described in detail, but it is understood that various changes, substitutions and changes may be made in the invention without departing from the spirit and scope of the invention. New embodiments are derived by combining several parts of the various embodiments. The described embodiments are to be considered in all respects as illustrative and not limiting. The scope of the invention should be determined by the scope of the appended claims. Those skilled in the art will be able to make some modifications and refinements without departing from the spirit and scope of the invention.

Claims (15)

An electrostatic discharge ESD protection integrated circuit includes: a functional circuit coupled to a first power supply voltage and a second power supply voltage, the functional circuit including at least one functional package ball; and an ESD detection circuit coupled to the second power supply voltage The ESD detection circuit is not coupled to the first power supply voltage and is not coupled to the at least one functional package ball of the functional circuit; wherein the ESD detection circuit includes: a plurality of discharge paths connected in parallel for ESD The stress event is discharged; and the ESD indicating circuit, if the ESD stress event never exceeds the ESD protection threshold of the ESD detection circuit, the ESD indicating circuit is turned off to indicate ESD pass; if the ESD stress event Exceeding the ESD protection threshold of the ESD detection circuit, the ESD indication circuit is shorted to indicate ESD failure. The ESD protection integrated circuit of claim 1, wherein the first power supply voltage is higher than the second power supply voltage. The ESD protection integrated circuit of claim 1, wherein the ESD detection circuit comprises at least one ESD package ball, the ESD package ball of the ESD detection circuit not coupled to the functional package ball of the functional circuit . The ESD protection integrated circuit of claim 1, wherein, under normal circumstances, the equivalent resistance of the ESD detection circuit is higher than a resistance threshold, and the ESD detection circuit is in an on state associated with ESD pass. According to the ESD protection integrated circuit of claim 1, wherein The ESD detection circuit discharges the ESD stress event when an ESD stress event occurs; and when the ESD stress event is higher than an ESD protection threshold of the ESD detection circuit, the ESD detection circuit is damaged, and the ESD detection circuit In a short circuit condition associated with ESD failure. The ESD protection integrated circuit of claim 1, wherein the plurality of discharge paths connected in parallel are coupled between the ESD package ball of the ESD detection circuit and the second power supply voltage, the plurality of discharges The paths have different discharge currents from each other; and the ESD indicating circuit is coupled between the ESD package ball and the second supply voltage, the ESD indicating circuit being in an open state associated with ESD pass or a short circuit condition associated with an ESD failure . The ESD protection integrated circuit of claim 1, wherein the plurality of discharge paths connected in parallel are coupled between the ESD package ball of the ESD detection circuit and the second power supply voltage, the plurality of discharges The paths have different discharge currents from each other. The ESD protection integrated circuit according to claim 1, wherein the ESD indicating circuit is coupled between the ESD package ball of the ESD detecting circuit and the second power supply voltage, and the ESD indicating circuit is qualified with ESD. The associated open state or is in a short circuit condition associated with an ESD failure. An ESD detection circuit for an ESD protection integrated circuit, comprising: a functional circuit having at least one functional package ball coupled to a first supply voltage and a second supply voltage, the ESD detection circuit include: At least one ESD package ball, the ESD package ball of the ESD detection circuit is not coupled to the functional package ball of the functional circuit and is not coupled to the first power supply voltage; a plurality of discharge paths connected in parallel are coupled to the Between the ESD package ball and the second power voltage for discharging an ESD stress event, the plurality of discharge paths having different discharge currents from each other; and an ESD indicating circuit coupled to the ESD package ball and the second power source Between voltages, the ESD indicating circuit is in an open state associated with ESD pass or in a short circuit condition associated with an ESD failure; wherein the ESD indication is if the ESD stress event never exceeds an ESD protection threshold of the ESD detection circuit The circuit is turned off to indicate ESD pass; if the ESD stress event exceeds the ESD protection threshold of the ESD detection circuit, the ESD indicator circuit is shorted to indicate ESD failure. The ESD detecting circuit of claim 9, wherein the first power source voltage is higher than the second power source voltage. The ESD detecting circuit of claim 9, wherein the ESD indicating circuit has an equivalent resistance higher than a resistance threshold, and the ESD detecting circuit is in an open state associated with ESD pass. The ESD detecting circuit according to claim 9, wherein when the ESD stress event occurs, the plurality of parallel connected discharge paths discharge the ESD stress event; and when the ESD stress event is higher than When the ESD detection threshold of the ESD detection circuit is, the ESD indicates that the circuit is damaged and is in a short circuit condition associated with ESD failure. According to the ESD detection circuit described in claim 9 of the patent application scope, Wherein each of the discharge paths connected in parallel includes at least one diode coupled between the ESD package ball and the second supply voltage. The ESD detecting circuit of claim 9, wherein the ESD indicating circuit includes a transistor coupled between the ESD package ball and the second power supply voltage when an ESD protection threshold is exceeded by the ESD detecting circuit The transistor is damaged when a high ESD stress event occurs. The ESD detecting circuit according to claim 9, wherein the ESD indicating circuit includes at least two transistors coupled to the ESD package ball and the second power supply voltage, when ESD protection is performed than the ESD detecting circuit The at least two transistor drain-source shorts occur when a high threshold ESD stress event occurs.