TWI653621B - Pixel circuit and display panel using the same - Google Patents

Abstract

The invention provides a pixel circuit and a display panel using the above pixel circuit. The pixel circuit includes a first transistor, a second transistor, a third transistor, a storage capacitor, and a liquid crystal capacitor. Each of the transistors has a first end, a second end, and a control end. The first end of the first transistor is configured to receive a reference potential, and the second end of the first transistor is electrically coupled to the control end, the second end of the second transistor, and the second end of the third transistor to the first The first end of the second transistor is configured to receive the current display signal, and the control end of the second transistor and the third transistor is configured to receive the control signal, and the first end of the third transistor is electrically coupled to the second The two ends of the node, the storage capacitor and the liquid crystal capacitor are electrically coupled to the common voltage and the second node, respectively.

Description

Pixel circuit and display panel using same

The present invention relates to related art of display panels, and more particularly to a pixel circuit and a display panel using the same.

In conventional display technology, the display includes a source driver whose source driver is used to provide display data to a corresponding pixel circuit. In high-resolution applications, the drive frequency of the display increases, so the charge and discharge times for each column of pixels are reduced. However, the charging and discharging speed of the pixel depends on the charge and discharge capability of the source driver. If the driving ability of the source driver is insufficient, the pixel cannot be charged to the voltage value required for displaying the data in time, thereby causing the drawing. The prime produces the wrong grayscale value.

SUMMARY OF THE INVENTION An object of the present invention is to provide a pixel circuit which uses a current to charge a pixel circuit to achieve a desired voltage in a short time.

Another object of the present invention is to provide a display panel using the above pixel circuit.

The invention provides a pixel circuit comprising a first transistor, a second transistor, a third transistor, a storage capacitor and a liquid crystal capacitor. The first transistor has a first end, a second end and a first control end, the first end is for receiving a reference potential, and the second end is The first control end is electrically coupled to the first node; the second transistor has a third end, a fourth end, and a second control end, the third end is configured to receive the current display signal, and the fourth end is electrically coupled to the first end a node, the second control terminal is configured to receive the control signal; the third transistor has a fifth end, a sixth end, and a third control end, the fifth end is electrically coupled to the second node, and the sixth end is electrically coupled To the first node, the third control terminal is configured to receive the control signal; the storage capacitor has a seventh end and an eighth end, the seventh end receives the common voltage, the eighth end is electrically coupled to the second node; and the liquid crystal capacitor has the first The ninth end receives the common voltage, and the tenth end is electrically coupled to the second node.

The present invention further provides a display panel including a first substrate, a source driver, a gate driver, a plurality of gate lines, a plurality of data lines, and a plurality of pixels. The source driver is disposed on the first substrate for outputting the current display signal; the gate driver is disposed on the first substrate; the plurality of gate lines are disposed on the first substrate, and the gate lines are electrically coupled to the gate respectively And a plurality of data lines are disposed on the first substrate, and the data lines are electrically coupled to the source drivers, wherein the gate lines and the data lines are interlaced to form an array of pixels, and the pixels are Each includes a pixel electrode and a pixel circuit; the pixel circuit includes a first transistor having a first end, a second end, and a first control end, the first end is for receiving a reference potential, and the second end is electrically coupled Connected to the first control terminal; the second transistor has a third end, a fourth end and a second control end, the third end is electrically coupled to one of the data lines, and the fourth end is electrically coupled to the first control The second control terminal is electrically coupled to one of the gate lines; and the third transistor has a fifth end, a sixth end, and a third control end, and the fifth end is electrically coupled to the pixel electrode, The six terminals are electrically coupled to the first control end, and the third control end is electrically coupled to the first Gate line.

The pixel circuit of the invention uses the current value of the current display signal to charge the pixel, and has better driving ability than the voltage value, so that the pixel can reach the required voltage in a short time, and the liquid crystal finally needs to be needed. The data voltage value solves the problem that charging takes too long in high-resolution applications.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

10‧‧‧ display panel

11‧‧‧First substrate

12‧‧‧Source Driver

121‧‧‧Operation Conversion Unit

13‧‧ ‧ gate driver

14‧‧‧ pixel circuit

141, 142, 143‧‧‧ transistors

41‧‧‧second substrate

42‧‧‧Common electrode

43‧‧‧Display molecular layer

44‧‧‧ pixel electrodes

45‧‧‧Insulation

46‧‧‧Metal wire

GL‧‧‧ gate line

DL‧‧‧ data line

C1, C2‧‧‧ capacitor

N _A , N _B ‧‧‧ nodes

VSS‧‧‧ reference potential

IDATA‧‧‧current display signal

SCAN‧‧‧ control signal

V _COM ‧‧‧Common voltage

V _H ‧‧‧Enable level

V _L ‧‧‧ disable level

The first period of T1‧‧

Second period of T2‧‧

1 is a schematic diagram of a display panel according to an embodiment of the invention; FIG. 2 is a circuit diagram of a pixel circuit according to an embodiment of the invention; and FIG. 3 is a timing diagram of a signal of a pixel circuit according to an embodiment of the invention; 4 is a schematic diagram of equivalent capacitance of a pixel circuit in accordance with an embodiment of the present invention.

In order to make the reader easy to understand, the display panel of the present invention will be described below. 1 is a schematic diagram of a display panel according to an embodiment of the invention. As shown in FIG. 1 , the present invention provides a display panel 10 including a first substrate 11 , a source driver 12 , a gate driver 13 , and a plurality of A gate line GL, a plurality of data lines DL, and a plurality of pixels 14. The source driver 12 is disposed on the first substrate 11 for outputting the current display signal IDATA. The gate driver 13 is disposed on the first substrate 11 for outputting a gate driving signal. The plurality of gate lines GL are disposed on the first substrate 11 and electrically coupled to the gate driver 13 and the plurality of pixels 14 respectively for transmitting the gate driving signals to the corresponding pixels 14. The plurality of data lines DL are disposed on the first substrate 11 and electrically coupled between the source driver 12 and the plurality of pixels 14 respectively, wherein the data line DL is used to transmit the current display signal IDATA to the corresponding pixel. 14. The gate line GL and the data line DL may be alternately arranged to form an array of a plurality of pixels 14. In the embodiment of FIG. 1, the plurality of pixels 14 are formed into a rectangular array structure, but the invention is not limited thereto. For example, the plurality of pixels 14 may also be an array structure of honeycomb arrays. In the embodiment, the source driver 12 further includes an operation conversion unit 121 for receiving a set display voltage. The operation conversion unit 121 can determine the output current display signal IDATA according to the set display voltage. In detail, the operation conversion unit 121 performs a table lookup according to the set display voltage and outputs a corresponding current display signal IDATA according to the table lookup result, and the current display signal IDATA is greater than Set the current value corresponding to the display voltage.

Next, an implementation of the pixel circuit of the pixel 14 described above will be explained. 2 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. As shown in FIG. 2, the pixel circuit has a transistor 141, a transistor 142, a transistor 143, a storage capacitor C1, and a liquid crystal capacitor C2. The transistor 141 has a first end, a second end and a first control end. The first end is configured to receive the reference potential VSS, and the second end and the first control end are electrically coupled to the node N _A , wherein the reference potential VSS is, for example. It is logic low. The transistor 142 has a third end, a fourth end and a second control end, wherein the third end is configured to receive the current display signal IDATA, and the fourth end is electrically coupled to the node N _A and the second control end is configured to receive The control signal SCAN, the control signal SCAN is the aforementioned gate drive signal. The transistor 143 has a fifth end, a sixth end, and a third control end, wherein the fifth end is electrically coupled to the node N _B , and the sixth end is electrically coupled to the node N _A , and the third control end is used to The control signal SCAN is received, wherein the voltage of the node N _B is the set display voltage described above. The storage capacitor C1 has a seventh end and an eighth end, the seventh end receives the common voltage V _COM , and the eighth end is electrically coupled to the node N _B , wherein the voltage difference between the common voltage V _COM and the node N _B forms a cross The pressure can be rotated by the display molecules corresponding to the pixels 14, so that the pixels 14 can display corresponding gray scale values, and the display molecules are, for example, liquid crystal molecules. The liquid crystal capacitor C2 has a ninth end and a tenth end, the ninth end receives the common voltage V _COM , and the tenth end is electrically coupled to the node N _B . The current value of the current display signal IDATA is greater than the current value corresponding to the node N _B .

3 is a timing diagram of signals of an embodiment of a pixel circuit of the present invention. In FIG. 3, the same reference numerals as those in FIG. 2 are denoted as the same signals. Referring to FIG. 2 and FIG. 3 simultaneously, when operating in the first period T1, the control signal SCAN is the enabling level V _H , the transistor 141 is operating in the saturation region, and the transistors 142 and 143 are turned on. status. At this time, the voltage of the node N _A can be _inferred by IDATA = k ( V _A - VSS - V _{TH_T 1} ) ² so that the voltage of the node N _A is , the voltage of node N _B is Where V _{TH_T 1} is the threshold voltage of the transistor 141, IDATA is the current value of the current display signal, k is the saturation zone constant, and the node N _A voltage is substantially equal to the node N _B voltage.

When operating in the second period T2, the control signal SCAN is the disable level V _L , and the transistors 142 and 143 are all in a turned off state. At this time, the node N _A leaks due to the path of the transistor 142, and the voltage of the node N _A is V _A = VSS + | V _{TH_T 1} |, and the voltage of the node N _B is Therefore, the transistor 141 is automatically _turned off according to the voltage of the node N _A , where V _{TH — T 1} is the threshold voltage of the transistor 141 , IDATA is the current value of the current display signal, k is the saturation region constant, and the node N _A voltage is less than the node N _{B .} Voltage. Therefore, the transistor 141 and the transistor 142 of the present invention form a current source driven architecture, which can generate a larger current value than the conventional voltage source driven architecture, so that the pixel 14 is charged to display data in time. The voltage value reaches the predetermined gray scale value of the pixel 14. After the second period T2, that is, entering the third period, the control signal SCAN is continuously maintained at the disable level V _L , and the transistors 142 and 143 are also turned off.

4 is a schematic diagram of equivalent capacitance of a pixel circuit in accordance with an embodiment of the present invention. Referring to FIG. 1 and FIG. 4 together, the display panel 10 includes a first substrate 11, a second substrate 41, a common electrode 42, an insulating layer 45, a display molecular layer 43, a pixel circuit 14, and a pixel electrode 44, and a pixel circuit. The pixel electrode 14 is disposed on the first substrate 11 and the common electrode 42 is disposed on the second substrate 41 . In detail, the display molecular layer 43 is interposed between the first substrate 11 and the second substrate 41 such that the liquid crystal capacitor C2 is formed between the common electrode 42 and the pixel electrode 44. The transistors 141, 142 and 143 of the pixel circuit 14 are disposed on the first substrate 11 and can be electrically coupled to the pixel electrode 44. Therefore, the current display signal IDATA, the control signal SCAN and the pixel circuit 14 can input an appropriate voltage to the pixel electrode 44, and then cooperate with the common electrode 42 to form an appropriate electric field, thereby controlling the display molecule rotation direction of the display molecular layer 43. To adjust the grayscale to complete the display function. In the embodiment, the first substrate 11 further includes a metal wire 46 for transmitting the common voltage V _COM , so the storage capacitor C1 is formed between the pixel electrode 44 and the metal wire 46 . However, the present invention is not limited thereto, and the stacking manner of each layer of components may be changed according to different designs. For example, the common electrode 42 may be disposed as the first substrate 11 and the pixel electrode 44 may be disposed on the second substrate 41. Alternatively, the common electrode 42 and the pixel electrode 44 may be disposed on the same substrate. In addition, the storage capacitor C1 can also be formed by parasitic capacitance formed by other layers, such as a gate line (for transmitting a gate driving signal) and a pixel electrode.

In summary, the arithmetic conversion unit of the present invention directly supplies a current display signal to a pixel circuit, and has better driving capability than the voltage value, so that the pixel can reach the required voltage in a short time, reaching the final stage of the liquid crystal. The required data voltage value solves the problem of excessive charging time in high-resolution applications.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any one skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the patent application scope.

Claims (10)

A pixel circuit includes: a first transistor having a first end, a second end, and a first control end, the first end for receiving a reference potential, the second end and the first The control terminal is electrically coupled to a first node; a second transistor has a third end, a fourth end, and a second control end, the third end is configured to receive a current display signal, the fourth The second terminal is electrically coupled to the first node, and the second control terminal is configured to receive a control signal; a third transistor has a fifth end, a sixth end, and a third control end, the fifth end Electrically coupled to a second node, the sixth end is electrically coupled to the first node, the third control end is configured to receive the control signal, and a first storage capacitor has a seventh end and a first The eighth end receives a common voltage, the eighth end is electrically coupled to the second node; and a liquid crystal capacitor has a ninth end and a tenth end, the ninth end receiving the common voltage The tenth end is electrically coupled to the second node. The pixel circuit of claim 1, wherein when the pixel circuit is operated in a first period, the control signal is an enable level, and the second and the third transistor are turned on. When the pixel circuit operates in a second period, the control signal is disabled and the second and third transistors are turned off. The pixel circuit of claim 2, wherein the first node voltage is substantially the same as the second node voltage when the pixel circuit operates in the first period. The pixel circuit of claim 2, wherein the first node voltage is less than the second node voltage when the pixel circuit operates in the second period. A display panel includes: a first substrate; a source driver disposed on the first substrate for outputting a current display signal; a gate driver disposed on the first substrate; and a plurality of gates a line is disposed on the first substrate, and the gate lines are electrically coupled to the gate driver; the plurality of data lines are disposed on the first substrate, and the data lines are electrically coupled to the a source driver, wherein the gate lines and the data lines are interlaced to form a plurality of pixels of an array, and the pixels respectively comprise: a pixel electrode; and a pixel circuit, and the pixel The pixel circuit includes a first transistor, a second terminal, and a first control terminal. The first terminal is configured to receive a reference potential, and the second terminal is electrically coupled to the pixel. a first control terminal; a second transistor having a third end, a fourth end, and a second control end, wherein the third end is electrically coupled to one of the data lines, and the fourth end is electrically Is electrically coupled to the first control end, the second control end is electrically coupled to the one of the gates And a third transistor having a fifth end, a sixth end, and a third control end, the fifth end is electrically coupled to the pixel electrode, and the sixth end is electrically coupled to the first a control terminal, the third control terminal is electrically coupled to one of the gate lines. The display panel of claim 5, wherein when the pixel circuit is operated in a first period, the gate driver inputs a control signal to the pixel through one of the gate lines The circuit is configured to turn on the second and the third transistors, and the source driver inputs the current display signal to the pixel circuit through one of the data lines. The display panel of claim 6, wherein when the pixel circuit operates in a first period, the control signal is an enable level, and when operating in the second period, The control signal is disabled, and the second transistor and the third transistor are turned off. When the pixel circuit operates in a third period, the control signal is continuously maintained at a disable level. Second, the third transistor is turned off. The display panel of claim 5, further comprising: a second substrate; a common electrode disposed on the second substrate; and a display molecular layer sandwiched between the first substrate and the second The pixel electrode is disposed on the first substrate, wherein the pixel circuit further comprises a first storage capacitor and a liquid crystal capacitor. The display panel of claim 5, wherein the second control end is electrically coupled to the third control end. The display panel of claim 5, further comprising an operation conversion unit disposed in the source driver, wherein the operation conversion unit can receive a set display voltage and output the current display signal, wherein the setting When the voltage is displayed, the voltage of the pixel electrode is substantially the same.