TWI647703B - Memory Test Methods - Google Patents

Memory Test Methods Download PDF

Info

Publication number
TWI647703B
TWI647703B TW107101838A TW107101838A TWI647703B TW I647703 B TWI647703 B TW I647703B TW 107101838 A TW107101838 A TW 107101838A TW 107101838 A TW107101838 A TW 107101838A TW I647703 B TWI647703 B TW I647703B
Authority
TW
Taiwan
Prior art keywords
column
block
test
address
sampling
Prior art date
Application number
TW107101838A
Other languages
Chinese (zh)
Other versions
TW201933370A (en
Inventor
林立偉
蔡宗寰
鄭如傑
Original Assignee
華邦電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 華邦電子股份有限公司 filed Critical 華邦電子股份有限公司
Priority to TW107101838A priority Critical patent/TWI647703B/en
Application granted granted Critical
Publication of TWI647703B publication Critical patent/TWI647703B/en
Publication of TW201933370A publication Critical patent/TW201933370A/en

Links

Abstract

A memory test method for memory circuits. The memory circuit includes a first block and a second block, the first block and the second block having a column address and a column address. The memory testing method includes: selecting one of the column addresses as the test column according to the selection logic; selecting one of the plurality of column addresses as the test column according to the selection logic; and selecting the sampling column address of the test column according to the sampling procedure; According to the sampling procedure, the sampling column address of the test column is selected; the sampling column address of the test column of the first block is read; and the sampling column address of the test column of the first block is read; Whether the read failure rate of the first block exceeds a predetermined ratio; and when the read failure rate exceeds a predetermined ratio, the first block is marked with an input/output error.

Description

Memory test method

The present invention relates to a memory testing method, and more particularly to a memory testing method suitable for memory having an Error-correcting Code (ECC).

In general, Emerging Memory can allow error rates from one to several bits. Therefore, when a memory circuit is found to have more than one bit of I/O fail during the test, the test system still determines that the memory circuit is normal, so that the input/output error cannot be recognized. come out.

Input/output errors are persistent errors for the entire memory circuit, that is, read errors occur every time the bit is read, and input/output errors often come from peripheral circuits in the memory array. Although the technique of error correction code can still be used to restore the data stored in the memory circuit with input/output errors, the input/output error still affects the reliability of the memory circuit.

However, current memory test methods do not recognize input/output errors, so it is necessary to improve the memory test method to identify input/output errors in the look-ahead memory.

In view of the above, the present invention provides a memory testing method, which is applicable to a memory circuit, wherein the memory circuit includes a first block and a second block, wherein the first block and the second block have The plurality of column addresses and the plurality of column addresses, the memory test method includes: selecting one of the column addresses as a test column according to a selection logic; and selecting one of the plurality of column addresses as one according to the selection logic a test column; selecting a plurality of sampled column addresses of the test column according to a sampling procedure; selecting a plurality of sampled column addresses of the test column according to the sampling procedure; and sampling the above-mentioned test columns of the first block Performing a read operation on the address; performing the above read operation on the sample column address of the test column of the first block; determining whether the read failure rate of one of the read operations of the first block exceeds a predetermined value The ratio; and when the read failure rate exceeds the predetermined ratio, marking the first block to have an input/output error.

According to an embodiment of the present invention, the memory testing method further includes: when the reading failure rate does not exceed the predetermined ratio, or after the step of marking the first block having the input/output error, Performing the above-mentioned reading test on the sampling column address of the above test column of the second block; performing the above reading operation on the test column address of the test column of the second block; and determining the above reading of the second block Whether the above-mentioned read failure rate of the operation exceeds the predetermined ratio; and when the above-mentioned read failure rate exceeds the predetermined ratio, the second block is marked to have an input/output error.

According to an embodiment of the present invention, when the first block and/or the second block mark have the input/output error, the peripheral circuit of the first block and/or the second block is faulty. Making the above read failure rate Too high.

According to an embodiment of the invention, the selection logic is random.

According to an embodiment of the present invention, the sampling procedure includes: dividing the column address into a first number of plural column segments; selecting at least one of the column segments; and selecting the address of the column segment As the sampling column address; dividing the column address into a second number of complex column segments; selecting at least one of the column segments; and selecting the address of the selected column segment as the sampling column site.

According to an embodiment of the invention, the first number is equal to the second number.

According to another embodiment of the invention, the first number is not equal to the second number.

According to an embodiment of the present invention, the step of selecting at least one of the column segments further includes: selecting the column segment of the first number of the first number, wherein the column segment and the unselected column are selected The segments are spaced apart from one another.

According to an embodiment of the present invention, the step of selecting at least one of the column segments further includes: selecting the column segment of the second number of the second number, wherein the column segment and the unselected column are selected The segments are spaced apart from one another.

According to an embodiment of the present invention, the step of determining whether the read failure rate of the read test of the first block exceeds the predetermined ratio further comprises: determining whether the read failure rate of the first block is 100%; when it is judged that the above reading failure rate is 100%, the first area is marked The block has a true input/output error; and when it is judged that the above-described read failure rate is not 100%, the first block is marked with a soft input/output error.

The present invention further provides a memory testing method, which is applicable to a memory circuit, wherein the memory circuit includes a first block and a second block, wherein the first block and the second block have a plurality of columns. The address and the plurality of column addresses, the memory test method includes: selecting one of the column addresses as a test column according to a selection logic; and selecting one of the plurality of column addresses as a test field according to the selection logic; Selecting a plurality of sampling column addresses of the test column according to a sampling procedure; selecting a plurality of sampling column addresses of the test column according to the sampling procedure; and simultaneously testing the first block and the second block Performing a reading operation on the sampling column address; performing the reading operation on the sampling column address of the first block and the second block in the test column; and determining the reading operation of the memory circuit Whether the read failure rate is zero; when the above read failure rate of the memory circuit is not zero, determining the first block and/or the second Whether the above-mentioned read failure rate of the block exceeds a predetermined ratio; when the read failure rate of the first block and/or the second block exceeds the predetermined ratio, marking the first block and/or the above The second block has a true input/output error.

According to an embodiment of the present invention, when the first block and/or the second block are marked as having the above input/output error, the peripheral circuit of the first block and/or the second block is faulty. So that the above read failure rate is too high.

According to an embodiment of the invention, the selection logic is random.

According to an embodiment of the invention, the sampling procedure comprises: The column address is divided into a first number of plural column segments; at least one of the column segments is selected; the address of the selected column segment is used as the sampling column address; and the column address is divided into a second number of complex column segments; selecting at least one of the column segments; and selecting the address of the selected column segment as the sample column address.

According to an embodiment of the invention, the first number is equal to the second number.

According to another embodiment of the invention, the first number is not equal to the second number.

According to an embodiment of the present invention, the step of selecting at least one of the column segments further includes: selecting the column segment of the second number of the second number, wherein the column segment and the unselected column are selected The segments are spaced apart from one another.

According to an embodiment of the present invention, the step of selecting at least one of the column segments further includes: selecting the column segment of the second number of the second number, wherein the column segment and the unselected column are selected The segments are spaced apart from one another.

According to an embodiment of the present invention, the memory testing method further includes: when determining that the read failure rate of the first block and/or the second block does not exceed the predetermined ratio, marking the first block and / or the second block above has a soft input/output error.

According to an embodiment of the invention, the predetermined ratio is 100%.

100, 200‧‧‧ memory circuits

S41~S46‧‧‧Step procedure

110-1, 210-1‧‧‧ first block

S501~S513‧‧‧Step procedure

110-2, 210-2‧‧‧ second block

S501~S513‧‧‧Step procedure

110-N, 210-N‧‧‧ Block N

S601~S610‧‧‧Step procedure

120-1‧‧‧First input and output circuit

120-2‧‧‧Second input and output circuit

120-N‧‧‧Nth input and output circuit

10‧‧‧Test circuit

300, 600‧‧‧ memory test method

X‧‧‧ column address

Y‧‧‧ column address

A‧‧‧First column

B‧‧‧Second column

C‧‧‧third column

D‧‧‧Fourth Section

E‧‧‧first column

F‧‧‧Second column

G‧‧‧third column

H‧‧‧ fourth column

S301~S311‧‧‧Step process

1 is a block diagram of a memory circuit according to an embodiment of the present invention; FIG. 2 is a schematic diagram showing a memory array according to an embodiment of the present invention; and FIG. 3 is a view showing a memory array according to an embodiment of the present invention; A flowchart of a memory testing method according to one embodiment; FIG. 4 is a flow chart showing a sampling procedure according to an embodiment of the present invention; and FIG. 5A-5B is a diagram showing another implementation according to the present invention. A flowchart of a memory testing method as described in the example; and a sixth drawing showing a flow chart of a memory testing method according to another embodiment of the present invention.

The following description is an embodiment of the present invention. The intent is to exemplify the general principles of the invention and should not be construed as limiting the scope of the invention, which is defined by the scope of the claims.

It is noted that the following disclosure may provide embodiments or examples for practicing various features of the present invention. The specific elements and arrangements of the elements described below are merely illustrative of the spirit of the invention and are not intended to limit the scope of the invention. In addition, the following description may reuse the same component symbols or characters in various examples. However, the re-use is for the purpose of providing a simplified and clear description, and is not intended to limit the relationship between the various embodiments and/or configurations discussed below. In addition, a description of one of the features described in the following description is coupled to, coupled to, and/or formed on another feature, etc. A plurality of different embodiments may be included, including direct contact of the features, or other additional features being formed between the features, such that the features are not in direct contact.

1 is a block diagram of a memory circuit in accordance with an embodiment of the present invention. As shown in FIG. 1, the memory circuit 100 includes a first block 110-1, a second block 110-2, ..., and an Nth block 110-N. The first block 110-1, the second block 110-2, ... and the Nth block 110-N form a memory array, and the first block 110-1, the second block 110- 2, ... and each of the Nth block 110-N are respectively coupled to the corresponding first input/output circuit 120-1, second input/output circuit 120-2, ... And an Nth input and output circuit 120-N.

According to an embodiment of the invention, the memory circuit 100 is a forward-looking memory with an error correction code, including a NAND flash, a Resistive Random Access Memory (ReRAM). ), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and the like.

The memory circuit 100 is coupled to the test circuit 10, and the test circuit 10 is respectively transmitted through the first input/output circuit 120-1, the second input/output circuit 120-2, ..., and the Nth input/output circuit 120-N. Accessing the data stored in the first block 110-1, the second block 110-2, ..., and the Nth block 110-N.

According to an embodiment of the invention, the test circuit 10 is a test machine for chip probe (CP) or final test (FT), wherein the final test is post-package test, and the memory Circuit 100 and test circuit 10 are physically separated. Test circuit according to another embodiment of the present invention The 10 series is a built-in self-test (BIST) circuit of the memory circuit 100, so the test circuit 10 and the memory circuit 100 are located on the same die or wafer.

According to an embodiment of the present invention, the test circuit 10 individually reads each of the first block 110-1, the second block 110-2, ..., and the Nth block 110-N. Take the operation. According to another embodiment of the present invention, the test circuit 10 can simultaneously perform read operations on the first block 110-1, the second block 110-2, ..., and the Nth block 110-N. . This is not limited in any way.

Figure 2 is a schematic diagram showing a memory array in accordance with an embodiment of the present invention. As shown in FIG. 2, the memory array 200 includes a first block 210-1, a second block 210-2, ..., and an Nth block 210-N, and has the same column address. X and column address Y. For example, when a column address X and a column address Y are selected for reading, the first block 210-1, the second block 210-2, ..., and the Nth region are used. The corresponding bit of block 210-N is read, and the read data of N bits is output.

According to an embodiment of the present invention, the address X of the memory array 200 is from 0 to 15, and the column address Y is from 0 to 15, that is, the first block 210-1 and the second block 210. The -2, ..., and Nth blocks 210-N each have 256 memory cells. It should be noted that the number of the address X and the column address Y in this column is for illustrative purposes and is not limited in any way.

3 is a flow chart showing a memory testing method according to an embodiment of the present invention. The following description of the flowchart of FIG. 3 will be combined with FIG. 2 for detailed description. As shown in FIG. 3, first, one of the column addresses is selected as a test column according to the selection logic (step S301), and according to the selection logic One of the selection column addresses is used as a test column (step S302).

According to an embodiment of the invention, the logic is selected to be random. According to other embodiments of the invention, any selection logic can be used to select the test column and the test column. According to another embodiment of the present invention, two or more test columns and a test column may be separately selected, and only one test column and one test column are selected as the invention explanation.

According to an embodiment of the present invention, step S301 of FIG. 3 is to select a column in which the address Y of the second figure is 0 as a test column, and step S302 of FIG. 3 is to select the address of the second column X as The column of 0 is used as a test bar. According to other embodiments of the present invention, another column address Y may be selected as a test column, or another column address X may be selected as a test column, or a plurality of column addresses Y and a plurality of column addresses X may be selected as test columns and The test column, here only the column with the column address Y being 0 as the test column and the column address X being 0 is used as a test column as an example, and is not limited thereto in any way.

Returning to Fig. 3, next, based on the sampling procedure, the complex sample column address of the test column is selected (step S303). According to an embodiment of the present invention, as shown in FIG. 2, the column with the address Y of 0 is a test column, and the column address X is 0-3 and 8-11 as a complex sampling field according to the sampling procedure. site. According to the sampling procedure, the complex sample column address of the test column is selected (step S304). According to an embodiment of the present invention, as shown in FIG. 2, the column address X is 0, which is a test column, and the column address Y is selected as 0-3 and 8-11 as a complex sampling column according to the sampling procedure. site.

Figure 4 is a flow chart showing a sampling procedure according to an embodiment of the present invention. As shown in Fig. 4, first, the column address X is divided into a first number of plural column segments (step S41). As shown in the embodiment of Figure 2, the column address X The system is divided into four column sections, which are a first column section A, a second column section B, a third column section C, and a fourth column section D. According to other embodiments of the present invention, the field address X may also be divided into any number of column segments, and is not required to be equally divided, and is for illustrative purposes only, and is not limited thereto in any way.

Next, at least one of the column sections is selected (step S42). As shown in the embodiment of FIG. 2, the first column segment A and the third column segment C are selected, wherein the first column segment A and the third column segment C are selected, and the second column segment is not selected. B and the fourth column section D are spaced apart from each other. According to other embodiments of the present invention, only one of the first column segment A, the second column segment B, the third column segment C, and the fourth column segment D may be selected, or the first column may be selected. At least one of the segment A, the second column segment B, the third column segment C, and the fourth column segment D is for illustrative purposes only and is not intended to be limited in any way.

Returning to Fig. 4, the address of the selected column section is taken as the sampling column address (step S43). As shown in the embodiment of Fig. 2, the sampling column address is the column address X of the first column section A and the third column section C, that is, 0-3 and 8-11.

Next, the column address Y is divided into a second number of complex column segments (step S44). As shown in the embodiment of FIG. 2, the column address Y is divided into four column segments, which are a first column segment E, a second column segment F, a third column segment G, and a fourth column region. Section H. According to other embodiments of the present invention, the column address Y can also be divided into any number of column segments without aliquoting. According to an embodiment of the invention, the first number is the same as the second number. According to another embodiment of the invention, the first number is different from the second number. This is for illustrative purposes only and is not intended to be limiting in any way.

Returning to Fig. 4, at least one of the column sections is selected (step S45). As shown in the embodiment of FIG. 2, the first column segment E and the third column segment G are selected, wherein the first column segment E and the third column segment G are selected and the second column segment is not selected. F and the fourth column segment H are spaced apart from each other. According to other embodiments of the present invention, only one of the first column segment E, the second column segment F, the third column segment G, and the fourth column segment H may be selected, or the first column may be selected. At least one of the segment E, the second column segment F, the third column segment G, and the fourth column segment H is for illustrative purposes only and is not intended to be limiting in any way.

Returning to Fig. 4, the address of the selected column section is taken as the sampling column address (step S46). As shown in the embodiment of FIG. 2, the sample column address is the column address Y of the first column segment E and the third column segment G, that is, 0-3 and 8-11.

Returning to Fig. 3, a block is selected (step S305). The designer may first select any of the first block 210-1, the second block 210-2, ..., and the Nth block 210-N, and the first block 210 is selected first. -1 is explained in explanation and is not limited to this in any way. Next, a read operation is performed on the sampling column address of the test column of the selected first block 210-1 (step S306), and the sample column address of the test column of the selected first block 210-1 is read. The operation is taken (step S307).

When the reading operation on the first block 210-1 is completed, it is judged whether or not the reading failure rate of the reading operation of the first block 210-1 exceeds a predetermined ratio (step S308). According to an embodiment of the invention, the predetermined ratio is 70%. According to other embodiments of the invention, the designer can decide for himself what the established ratio is.

Returning to step S308, when it is judged that the read failure rate of the read operation of the first block 210-1 does not exceed the predetermined ratio, it is judged whether or not there is the next block (step S309). When you have the next block, select the next block (step S310), and returns to step S306. As shown in the embodiment of FIG. 2, since the first block 210-1 completes the read operation, the second block 210-2, ..., the Nth block 210-N is selected here. One. The designer may select the blocks in order, or select the appropriate blocks according to the requirements, and is not limited thereto in any way. Returning to step S309, when there is no next block, the memory test method 300 is ended.

Returning to step S308, when it is judged that the read failure rate of the read operation of the first block 210-1 exceeds a predetermined ratio, the block is marked with an input/output error (step S311). According to an embodiment of the present invention, when a certain block reads any sampling address and has a high read failure rate, the peripheral failure of the block represents a high read failure rate, so the flag is marked. The block has an input/output error.

5A-5B are flowcharts showing a memory testing method according to another embodiment of the present invention. As shown in FIG. 5A, steps S501 to S510 of FIG. 5A are the same as steps S301 to S310 of FIG. 3, and the details are not repeated herein.

In step S508, when it is determined that the read failure rate of the read operation of the selected first block 210-1 does not exceed the predetermined ratio, it is further determined whether the read failure rate is 100% (step S511). When it is judged that the read failure rate is 100%, the first block 210-1 of the mark selection has a true input/output error (step S512). According to an embodiment of the present invention, when it is determined that the read failure rate is 100%, the peripheral circuit representing the block can hardly read the data in the block, and the degree of confidence can confirm the area. An error occurs in the input/output circuit corresponding to the block, so it is marked as a true input/output error.

Going back to step S511, when it is determined that the read failure rate is not 100%, The first block 210-1 of the mark selection has a soft input/output error (step S513). According to an embodiment of the present invention, when the soft input/output error is marked, the input/output circuit corresponding to the block is unstable, which may cause good or bad time for each read operation, thus marking a Microsoft input/output error. .

Figure 6 is a flow chart showing a memory testing method according to another embodiment of the present invention. As shown in FIG. 6, steps S601 to S604 of FIG. 6 are the same as steps S301 to S304 of FIG. 3 and steps S501 to S504 of FIG. 5A, and the details are not repeated here.

In step S605, the sampling column address of the test column of the first block 210-1, the second block 210-2, ... and the Nth block 210-N of the second figure is simultaneously read. Take the operation. Next, the sampling operation of the sampling column address of the test block of the first block 210-1, the second block 210-2, ... and the Nth block 210-N of FIG. 2 is simultaneously performed. (Step S606).

When the test column and the read operation of the test column are completed, it is judged whether or not the read failure rate of the read operation of all the blocks of the memory circuit 100 is zero (step S607). When the read failure rate of the memory circuit 100 is zero, the read operations representing all of the blocks of the memory circuit 100 are completely normal, thus ending the memory test method 600.

When it is determined that the read failure rate of the memory circuit 100 is not zero, the first block 210-1, the second block 210-2, ..., and the Nth block 210-N are further judged. Whether the read failure rate of one exceeds a predetermined ratio (step S608). According to an embodiment of the invention, the predetermined ratio is 70%. According to another embodiment of the invention, the predetermined ratio is 100%. According to other embodiments of the invention, the established ratio is at the discretion of the designer.

When it is judged that the read failure rate of any of the first block 210-1, the second block 210-2, ..., and the Nth block 210-N exceeds a predetermined ratio, the block is marked. There is a true input/output error (step S609). According to an embodiment of the present invention, when the flag is a true input/output error, the peripheral circuit representing the block is too high, and there is a high probability that the read failure will occur.

When it is judged that the read failure rate of any of the first block 210-1, the second block 210-2, ..., and the Nth block 210-N does not exceed a predetermined ratio, the area is marked. The block has a soft input/output error (step S610). According to an embodiment of the present invention, when the soft input/output error is marked, the peripheral circuit representing the block is unstable, which often causes good or bad for each read operation.

By using the memory testing method proposed by the invention, the input/output errors of the memory block can be effectively recognized, thereby improving the reliability of the memory.

The above is an overview feature of the embodiment. Those having ordinary skill in the art should be able to use the present invention as a basis for design or adaptation to achieve the same objectives and/or achieve the same advantages of the embodiments described herein. It should be understood by those of ordinary skill in the art that the same configuration should not depart from the spirit and scope of the present invention, and various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present invention. The illustrative methods are merely illustrative of the steps, but are not necessarily performed in the order presented. The steps may be additionally added, substituted, changed, and/or eliminated, as appropriate, and are consistent with the spirit and scope of the disclosed embodiments.

Claims (14)

  1. A memory testing method is applicable to a memory circuit, wherein the memory circuit includes a first block and a second block, wherein the first block and the second block have a plurality of column addresses and a plurality of columns The address test method includes: selecting one of the column addresses as a test column according to a selection logic; selecting one of the plurality of column addresses as a test field according to the selection logic; according to a sampling procedure Selecting a plurality of sampling column addresses of the test column; selecting a plurality of sampling column addresses of the test column according to the sampling procedure; and performing a reading operation on the sampling column address of the test column of the first block; Performing the above reading operation on the sampling column address of the test column of the first block; determining whether the read failure rate of one of the reading operations of the first block exceeds a predetermined ratio; and when the reading is performed When the failure rate exceeds the above-mentioned predetermined ratio, the first block is marked as having an input/output error.
  2. The method for testing a memory according to claim 1, further comprising: when the reading failure rate does not exceed the predetermined ratio, or after the step of marking the first block having the input/output error, Performing the above-mentioned reading test on the sampling column address of the above test column of the second block; performing the above reading operation on the test column address of the test column of the second block; Determining whether the read failure rate of the read operation of the second block exceeds the predetermined ratio; and when the read failure rate exceeds the predetermined ratio, marking the second block to have an input/output error.
  3. The memory testing method of claim 2, wherein when the first block and/or the second block mark has the input/output error, the first block and/or the first The peripheral circuit failure of the second block causes the above read failure rate to be too high.
  4. The memory testing method of claim 1, wherein the sampling procedure comprises: dividing the column address into a first number of plural column segments; selecting at least one of the column segments; The address of the column segment is used as the sampling column address; the column address is divided into a second number of complex column segments; at least one of the column segments is selected; and the column segment to be selected The address is used as the above sampling column address.
  5. The memory testing method of claim 4, wherein the first number is equal to the second number.
  6. The memory testing method of claim 4, wherein the step of selecting at least one of the column sections further comprises: selecting the one of the first number of the column segments, wherein the column is selected The segments and the unselected column segments are spaced apart from each other.
  7. The method for testing a memory according to claim 4, wherein the step of selecting at least one of the foregoing column segments further comprises: And selecting the column segment of the second number of the second number, wherein the selected column segment and the unselected column segment are spaced apart from each other.
  8. The method for testing a memory according to claim 1, wherein the step of determining whether the read failure rate of the read test of the first block exceeds the predetermined ratio further comprises: determining the first area. Whether the above read failure rate of the block is 100%; when it is determined that the read failure rate is 100%, marking the first block has a true input/output error; and when determining that the read failure rate is not 100 When %, the above first block is marked with a soft input/output error.
  9. A memory testing method is applicable to a memory circuit, wherein the memory circuit includes a first block and a second block, wherein the first block and the second block have a plurality of column addresses and a plurality of columns The address test method includes: selecting one of the column addresses as a test column according to a selection logic; selecting one of the plurality of column addresses as a test field according to the selection logic; according to a sampling procedure Selecting the plurality of sampling column addresses of the above test columns; selecting the plurality of sampling column addresses of the test column according to the sampling procedure; and simultaneously sampling the sampling fields of the first block and the second block Performing a read operation on the address; performing the above read operation on the sampling column address of the first block and the second block in the test column; determining that one of the read operations of the memory circuit is read Whether the failure rate is zero; When the read failure rate of the memory circuit is not zero, determining whether the read failure rate of the first block and/or the second block exceeds a predetermined ratio; when the first block and/or Or when the read failure rate of the second block exceeds the predetermined ratio, marking the first block and/or the second block to have a true input/output error.
  10. The memory testing method according to claim 9, wherein when the first block and/or the second block are marked as having the above input/output error, the first block and/or the above The peripheral circuit failure of the second block causes the above read failure rate to be too high.
  11. The memory testing method of claim 9, wherein the sampling procedure comprises: dividing the column address into a first number of plural column segments; selecting at least one of the column segments; The address of the column segment is used as the sampling column address; the column address is divided into a second number of complex column segments; at least one of the column segments is selected; and the column segment to be selected The address is used as the above sampling column address.
  12. The memory testing method of claim 11, wherein the first number is equal to the second number.
  13. The method for testing a memory according to claim 11, wherein the step of selecting at least one of the column segments further comprises: selecting the column segment of the second number of the second number, wherein the column is selected The segments and the unselected column segments are spaced apart from each other.
  14. The method for testing a memory according to claim 11, wherein the step of selecting at least one of the column segments further comprises: selecting the column segment of the second number of the second number, wherein the column is selected The segments and the unselected column segments are spaced apart from each other.
TW107101838A 2018-01-18 2018-01-18 Memory Test Methods TWI647703B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW107101838A TWI647703B (en) 2018-01-18 2018-01-18 Memory Test Methods

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107101838A TWI647703B (en) 2018-01-18 2018-01-18 Memory Test Methods

Publications (2)

Publication Number Publication Date
TWI647703B true TWI647703B (en) 2019-01-11
TW201933370A TW201933370A (en) 2019-08-16

Family

ID=65803793

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107101838A TWI647703B (en) 2018-01-18 2018-01-18 Memory Test Methods

Country Status (1)

Country Link
TW (1) TWI647703B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7495978B2 (en) * 2000-03-29 2009-02-24 Elpida Memory, Inc. Semiconductor device and memory circuit including a redundancy arrangement
US7872941B2 (en) * 2008-07-10 2011-01-18 Hynix Semiconductor Inc. Nonvolatile memory device and method of operating the same
US20110161751A1 (en) * 2007-12-12 2011-06-30 Renesas Electronics Corporation Semiconductor integrated circuit with memory repair circuit
US20140289569A1 (en) * 2013-03-22 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor storage device, controller, and memory system
US20140289559A1 (en) * 2013-03-21 2014-09-25 Kabushiki Kaisha Toshiba Test method for nonvolatile memory
US20160293277A1 (en) * 2015-03-31 2016-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with redundant io circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7495978B2 (en) * 2000-03-29 2009-02-24 Elpida Memory, Inc. Semiconductor device and memory circuit including a redundancy arrangement
US20110161751A1 (en) * 2007-12-12 2011-06-30 Renesas Electronics Corporation Semiconductor integrated circuit with memory repair circuit
US7872941B2 (en) * 2008-07-10 2011-01-18 Hynix Semiconductor Inc. Nonvolatile memory device and method of operating the same
US20140289559A1 (en) * 2013-03-21 2014-09-25 Kabushiki Kaisha Toshiba Test method for nonvolatile memory
US20140289569A1 (en) * 2013-03-22 2014-09-25 Kabushiki Kaisha Toshiba Semiconductor storage device, controller, and memory system
US20160293277A1 (en) * 2015-03-31 2016-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with redundant io circuit

Also Published As

Publication number Publication date
TW201933370A (en) 2019-08-16

Similar Documents

Publication Publication Date Title
US6181614B1 (en) Dynamic repair of redundant memory array
US5859804A (en) Method and apparatus for real time two dimensional redundancy allocation
US5233614A (en) Fault mapping apparatus for memory
US4380066A (en) Defect tolerant memory
JP2007305267A (en) Semiconductor storage device
CN1224973C (en) Integrated circuit semiconductor device and self-repairing circuit and method for built-in storage
US6438044B2 (en) Semiconductor memory device and method of testing the same
JP3865828B2 (en) Semiconductor memory device
US20080115043A1 (en) Semiconductor memory system and signal processing system
JP2005518628A (en) Fuse concept and method of operation
US6940765B2 (en) Repair apparatus and method for semiconductor memory device to be selectively programmed for wafer-level test or post package test
JP2005182866A (en) Device and method for testing semiconductor, method for manufacturing semiconductor, and semiconductor memory
KR20160148347A (en) Self repair device and method
US7308621B2 (en) Testing of ECC memories
JP2005285270A (en) Semiconductor device and testing method
KR20050058224A (en) Semiconductor storage device
CN1612265B (en) The semiconductor memory device
JPH11312396A (en) Multibit semiconductor memory device and error correcting method for the same
US7698608B2 (en) Using a single bank of efuses to successively store testing data from multiple stages of testing
GB2265031A (en) Row redundancy circuit for a semiconductor memory device.
US6259637B1 (en) Method and apparatus for built-in self-repair of memory storage arrays
US6118710A (en) Semiconductor memory device including disturb refresh test circuit
US7178072B2 (en) Methods and apparatus for storing memory test information
KR20120051606A (en) System and method of tracking error data within a storage device
JP5085446B2 (en) 3D memory device