TWI643455B - Apparatus and methods for controlling radio frequency switches - Google Patents

Abstract

Apparatus and methods for controlling radio frequency (RF) switches are disclosed. Apparatus and methods for controlling an RF switch are provided herein. In some configurations, an RF system includes: a charge pump for generating a charge pump voltage; an RF switch; a quasi-shifter for turning the RF switch on or off; and a quasi-shift Control circuit for controlling the level shifter. The charge pump receives a mode signal for enabling or disabling the charge pump. Additionally, the level shifter portion receives power from the charge pump voltage and controls the RF switch based on a switch enable signal. The level shifter control circuit receives the mode signal and biases the bias voltage to the level shifter based on a state change based on a state of the mode signal.

Description

Apparatus and method for controlling an RF switch

Embodiments of the invention relate to electronic systems, and in particular to switch controllers for radio frequency switches.

Radio frequency (RF) switches can be included in a variety of electronic systems. In an example, an RF system can include an antenna for receiving and/or transmitting RF signals. However, there may be several components in the RF system that may require access to the antenna. For example, an RF system may include different transmission or reception paths associated with different frequency bands, different communication standards, and/or different power modes, and each path may require access to the antenna at certain instances of time. Thus, the RF system can include RF switches that can be used to electrically connect the antenna to a particular transmission or reception path of the RF system, thereby allowing multiple components to access the antenna. The performance of the RF switch can be important because the RF switch can introduce noise and/or insertion loss.

In certain embodiments, the present invention is directed to a radio frequency (RF) system. The RF system includes: a charge pump configured to generate a charge pump voltage; a first RF switch; a first level shifter configured to control the first based on a first switch enable signal An RF switch; and a quasi-shifter control circuit. The charge pump is configured to receive an operational mode to enable the charge pump in a first state and to disable one of the charge pump mode signals in a second state. The first level shifter is configured to receive power in part from the charge pump voltage. The level shifter control circuit is configured to receive the mode signal and to bias the first level shifter with a bias voltage. The level shifter control circuit is further configured to control a voltage level of the bias voltage based on a state of the one of the mode signals. In some embodiments, the level shifter control circuit is further configured to control the voltage level of the bias voltage to track the charge pump voltage when the mode signal is in the first state. In several embodiments, the level shifter control circuit is further configured to control the voltage level of the bias voltage to a DC voltage when the mode signal is in the second state. In some embodiments, the level shifter comprises a plurality of n-type metal oxide semiconductor (NMOS) stacked transistors, the plurality of NMOS stacked transistors comprising a gate biased by a bias voltage. According to several embodiments, the level shifter further includes a plurality of p-type metal oxide semiconductor (PMOS) stacked transistors, the plurality of PMOS stacked transistors including a gate biased by a low power supply voltage, One of the plurality of PMOS-stacked transistors, the first PMOS-stacked transistor and one of the plurality of NMOS-stacked transistors, are electrically connected in series between a high power supply voltage and a charge pump voltage. According to various embodiments, the level shifter control circuit includes a stacked reference circuit configured to generate one of the stacked reference voltages relative to the charge pump voltage change, the level shifter control circuit configured to be in the mode The signal controls one of the voltage levels of the bias voltage to the spliced reference voltage when in the first state. In some embodiments, the level shifter control circuit includes a parallel operation when the mode signal is in the first state to electrically connect the spliced reference voltage to one of the bias voltage NMOS transistors and a PMOS transistor. According to various embodiments, the splicing reference circuit includes a voltage divider electrically coupled between a high power supply voltage and a charge pump voltage, the voltage divider being configured to generate a spliced reference voltage. According to some embodiments, the voltage divider comprises a plurality of diode-connected transistors electrically connected in series. In several embodiments, the level shifter control circuit includes a standby control circuit configured to control one of the charge pump voltage levels to a low power supply voltage when the mode signal is in the second state. According to several embodiments, the standby control circuit is further configured to control a voltage level of one of the first switch control signals to a low power supply voltage when the mode signal is in the second state. In some embodiments, the RF system further includes a second RF switch and is configured to control a second level shifter of the second RF switch based on a second switch enable signal, the level shifter control circuit Further configured to bias the second level shifter with a bias voltage. In certain embodiments, the present invention is directed to a method of radio frequency switch control. The method includes: generating a charge pump voltage using a charge pump; enabling the charge pump when a mode signal is in a first state; and deactivating the charge pump when the mode signal is in a second state; The charge pump voltage is supplied to a first level shifter; a first RF switch is controlled based on shifting a first switch enable signal using a first level shifter level; biasing is applied using a bias voltage And a voltage level of one of the bias voltages based on a state of the mode signal; In some embodiments, controlling the voltage level of the bias voltage based on the state of the mode signal includes controlling the voltage level of the bias voltage to track the charge pump voltage when the mode signal is in the first state. According to several embodiments, the method of further controlling the voltage level of the bias voltage based on the state of the mode signal further comprises controlling the voltage level of the bias voltage to a DC voltage when the mode signal is in the second state. In various embodiments, applying a bias voltage to the level shifter using a bias voltage includes biasing a plurality of transistor gates of the level shifter with a bias voltage. In several embodiments, the method further includes controlling one of the voltage pump voltage levels to a low power supply voltage when the mode signal is in the second state. In some embodiments, the method further includes: partially supplying power to the second level shifter using the charge pump voltage; controlling one based on shifting a second switch enable signal using a second level shifter level a second RF switch; and biasing the second level shifter with a bias voltage. In certain embodiments, the present invention is directed to a power amplifier system. The power amplifier system includes: a charge pump configured to generate a charge pump voltage; a power amplifier configured to generate an amplified RF signal; an antenna; an RF switch electrically coupled to the power amplifier One of the outputs is coupled to the antenna; and a switch controller includes a level shifter configured to control the RF switch based on a switch enable signal. The power pump is further configured to receive operable to activate the charge pump in a first state and to deactivate one of the charge pump mode signals in a second state. The level shifter is further configured to receive power in part from the charge pump voltage. The switch controller further includes a level shifter control circuit configured to receive the mode signal and biased to the level shifter using a bias voltage. The level shifter control circuit is further configured to control a voltage level of the bias voltage based on a state of the one of the mode signals. In several embodiments, the level shifter control circuit is further configured to control the voltage level of the bias voltage to track the charge pump voltage when the mode signal is in the first state. In certain embodiments, the present invention is directed to an RF switching system. The RF switching system includes: a first RF switch configured to turn on or off based on a first switch control signal; a one-bit shifter control circuit configured to receive a mode signal and generate a a bias voltage; and a quasi-shifter that is powered by a high power supply voltage and by a charge pump voltage. The level shifter control circuit is configured to control a voltage level of the bias voltage based on a state of the one of the mode signals. The level shifter is powered by a high power supply voltage and by a charge pump voltage, and the power shifter is configured to receive a switch enable signal and the bias voltage. The level shifter is configured to shift the switch enable signal to generate the first switch control signal when the mode signal is in the first state. In some embodiments, the level shifter control circuit controls the voltage level of the bias voltage to track the charge pump voltage when the mode signal is in the first state. In several embodiments, the level shifter control circuit controls the voltage level of the bias voltage to a high power supply voltage when the mode signal is in the second state. In various embodiments, the level shifter includes a plurality of NMOS stacked transistors, the plurality of NMOS stacked transistors including a gate biased by a bias voltage. According to several embodiments, the level shifter further includes a plurality of PMOS stacked transistors, the plurality of PMOS stacked transistors including a gate biased by a low power supply voltage, and the plurality of PMOS stacked transistors One of the first PMOS stacked transistor and one of the plurality of NMOS stacked transistors is electrically coupled in series between the high power supply voltage and the charge pump voltage. In some embodiments, the level shifter control circuit includes a splicing reference circuit configured to generate one of the spliced reference voltages relative to the charge pump voltage change, the level shifter control circuit configured to When the mode signal is in the first state, one of the voltage levels of the bias voltage is controlled to the overlap reference voltage. In various embodiments, the level shifter control circuit includes parallel operation to electrically connect the spliced reference voltage to one of the bias voltage NMOS transistors and a PMOS transistor when the mode signal is in the first state. In some embodiments, the splicing reference circuit includes a voltage divider electrically coupled between the high power supply voltage and the charge pump voltage, the voltage divider being configured to generate a spliced reference voltage. According to several embodiments, the voltage divider comprises a plurality of diode-connected transistors electrically connected in series. In several embodiments, the RF switching system further includes a charge pump configured to generate a charge pump voltage, the charge pump configured to turn off when the mode signal is in the second state. In various embodiments, the level shifter control circuit includes a standby control circuit configured to control a voltage level of one of the charge pump voltages to a low power supply voltage when the mode signal is in the second state. According to several embodiments, the standby control circuit is further configured to control a voltage level of one of the first switch control signals to a low power supply voltage when the mode signal is in the second state. In some embodiments, the RF switching further includes a second RF switch that is turned "on" or "off" based on a second switch control signal. The first RF switch is configured as a series switch and the second RF switch is configured as a parallel switch. The level shifter is further configured to shift the switch enable signal to generate a second switch control signal when the mode signal is in the first state. In certain embodiments, the present invention is directed to a method of radio frequency switch control. The method includes using a charge pump to generate a charge pump voltage having a voltage level that is less than a voltage level of a low power supply voltage. The method further includes: supplying a quasi-shifter using a high power supply voltage and a charge pump voltage; using a quasi-shifter control circuit to generate a bias voltage; using the level shifter control circuit Controlling a voltage level of the bias voltage based on a state of a mode signal; using the bias voltage to bias the level shifter; when the mode signal is in a first state, using The level shifter shifts a switch enable signal to generate a first switch control signal; and uses the first switch control signal to control a first RF switch. In some embodiments, controlling the voltage level of the bias voltage based on the state of the mode signal includes controlling the voltage level of the bias voltage to track the charge pump voltage when the mode signal is in the first state. In various embodiments, controlling the voltage level of the bias voltage based on the state of the mode signal further includes controlling the voltage level of the bias voltage to a high power supply voltage when the mode signal is in the second state. In several embodiments, biasing the bias level to the level shifter using a bias voltage comprises applying a plurality of gates of the NMOS stacked transistor biased to the level shifter using a bias voltage. According to several embodiments, the method further includes generating a splicing reference voltage relative to one of the charge pump voltage changes, and controlling one of the voltage levels of the bias voltage to the splicing reference voltage when the mode signal is in the first state. In various embodiments, the method further includes turning off the charge pump when the mode signal is in the second state. In several embodiments, the method further includes electrically connecting the charge pump voltage to the low power supply voltage when the mode signal is in the first state. In some embodiments, the method further includes controlling a voltage level of the first switch control signal to a low power supply voltage when the mode signal is in the second state. In certain embodiments, the present invention is directed to a wireless device. The wireless device includes: a power amplifier configured to generate an amplified RF signal; an antenna; a first NMOS switch transistor electrically coupled between the output of the power amplifier and the antenna, the first One gate of the NMOS switch transistor is configured to receive a first switch control signal; a charge pump configured to generate a charge pump voltage; and a quasi-shifter control circuit configured to receive a mode signal and generating a bias voltage, the level shifter control circuit configured to control a voltage level of the bias voltage based on a state of the mode signal; and a quasi-shifter Powered by a high power supply voltage and the charge pump voltage. The level shifter is configured to receive a switch enable signal and the bias voltage, and the level shifter is configured to shift the switch enable when the mode signal is in the first state A signal is generated to generate the first switch control signal. In some embodiments, the level shifter control circuit controls the voltage level of the bias voltage to track the charge pump voltage when the mode signal is in the first state. In various embodiments, the level shifter controls the voltage level of the bias voltage to a high power supply voltage when the mode signal is in the second state. In several embodiments, the level shifter control circuit includes a standby control circuit configured to control a voltage level of one of the charge pump voltages to a low power supply voltage when the mode signal is in the first state. In several embodiments, the standby control circuit is further configured to control a voltage level of one of the first switch control signals to a low power supply voltage when the mode signal is in the second state. In some embodiments, the wireless device further includes a second NMOS switch transistor electrically coupled between the output of the power amplifier and a low power supply voltage. One of the gates of the second NMOS switch transistor is configured to receive a second switch control signal, the level shifter being further configured to shift the switch enable signal to generate a signal when the mode signal is in the first state The second switch control signal.

The headings, if any, provided herein are for convenience only and do not necessarily affect the scope or meaning of the invention. A radio frequency (RF) switching circuit can include a series switch between the input and output of the RF switching circuit and a parallel switch between the input and a low power supply voltage (such as ground). In addition, the series switch and the parallel switch can be turned on or off in a complementary manner. A low impedance path from the input to the output of the RF switching circuit is provided when the series switch is turned on or off and the parallel circuit is turned off or off. Additionally, when the series switch is turned off and the parallel switch is turned on, the series switch operates at high impedance to block conduction between the input and output and the parallel switch operates at low impedance to provide an input terminal. A RF switching circuit can be powered in part using a negative voltage generator such as a charge pump. For example, a charge pump can be used to generate a negative charge of a gate voltage for biasing one or more n-type metal oxide semiconductor (NMOS) switching transistors (when operating in a closed state) Pump voltage. Controlling the gate voltage of an NMOS switch transistor to a voltage below a low power supply voltage increases the off-state impedance, which enhances isolation and/or improves harmonic performance in multi-band applications. In some configurations, a negative voltage generator can be disabled or turned off in a standby mode. For example, a charge pump can operate using a clock signal generated by an oscillator that can dissipate quiescent current and/or generate noise. To prevent the charge pump from degrading system performance during standby, the charge pump can be deactivated in standby mode. Although deactivating the charge pump during standby can reduce power consumption and/or noise, deactivating the charge pump during standby can also undesirably cause the output voltage of the charge pump to float, thereby causing the gate of some RF switches. The voltage is controlled unpredictably. It may be desirable to control the gate voltage of the RF switch even when operating in the standby mode. For example, controlling the gate voltage of the RF switch during standby can help maintain isolation between multiple RF bands and/or circuits. Apparatus and methods for controlling an RF switch are provided herein. In some configurations, an RF system includes: a charge pump for generating a charge pump voltage; an RF switch; a quasi-shifter for turning the RF switch on or off; and a bit shift A bit control circuit for controlling the level shifter. The charge pump receives one of the mode signals for enabling or disabling the charge pump. Additionally, the level shifter portion receives power from the charge pump voltage and controls the RF switch based on a switch enable signal. The level shifter control circuit receives the mode signal and biases the voltage to the level shifter using one of the state changes based on one of the mode signals. The charge pump is enabled in one of the first states of the mode signal and is deactivated in one of the mode signals in the second state. For example, the first state can indicate a normal mode of operation and the second state can indicate a standby mode. In some configurations, the level shifter control circuit controls the voltage level of the bias voltage such that when the mode signal is in the first state, the bias voltage tracks the charge pump voltage and causes the mode signal to be in the second state The medium time bias voltage has a substantially constant or constant voltage. Configuring the level shifter control circuit in this manner to generate a bias voltage can assist in the level shifting operation of the level shifter. For example, in some configurations, a high power supply voltage and a charge pump voltage are used to power the level shifter. Additionally, the level shifter includes a plurality of stacked transistors having gates biased by a bias voltage generated by the level shifter control circuit. When the mode signal is in a first state, the level shifter control circuit generates a bias voltage to have a tracking charge pump voltage to assist in the level shifter level shift switch enable signal to a high power supply voltage and charge The pump voltage is associated with one of the voltage domains of one of the voltage domains. However, when the mode signal is in a second state, the level shifter control circuit controls the bias voltage to a fixed voltage. In some embodiments, the level shifter control circuit also controls the charge pump voltage to a low power supply voltage (eg, ground) during the second mode, thereby assisting the level shifter to turn off in the second mode. RF switch. Thus, when the RF system is operating in one of the primary or normal modes of operation associated with the first state of the mode signal, the level shifter operates using a high power supply voltage and a charge pump voltage. In one example, when the mode signal is in the first state, the level shifter operates between a high power supply voltage of about +2.5 V and a negative charge pump voltage of about -2.0 V. Additionally, when the RF system is operating in one of the standby modes associated with the second state of the mode signal, the level shifter control circuit controls the charge pump voltage and the bias voltage such that the level shifter turns off the RF switch. In an example, the level shifter control circuit controls the charge pump voltage to a low power supply voltage of about 0 V when the mode signal is in the second state. While a variety of exemplary voltage levels have been provided, any suitable voltage level can be used. The level shifter described herein can be used to generate a switch control signal that has a desired voltage level when a charge pump is enabled and when the charge pump is deactivated. Therefore, the gate voltage of the RF switch can be appropriately controlled in both the main mode and the standby mode. Controlling the RF switch in this manner enhances RF isolation and/or otherwise enhances performance. 1 is a schematic diagram of one embodiment of an integrated circuit (IC) 10. The IC 10 is shown to receive a first or low power supply voltage V₁ One of the first pins 5a and receiving a second or high power supply voltage V₂ One of the second pins 5b. In addition, the illustrated IC 10 further includes a switch 12, a charge pump 22, and a switch controller 23. Although not shown in FIG. 1 for clarity of the drawings, the IC 10 typically includes additional pins and circuitry. Charge pump 22 can be used to generate less than a low power supply voltage V₁ One of the voltage levels is one of the voltage levels of the charge pump voltage. Switch controller 23 receives a charge pump voltage that can be used in part to control switch 12. For example, the illustrated IC 10 can represent a front end module (FEM) and/or an antenna switch module (ASM), and the switch 12 can include an n-type metal oxide semiconductor (NMOS) switching transistor. The NMOS switch transistor includes a gate that is biased to a voltage level of one of the charge pump voltages when turned off. Controlling the gate voltage of an NMOS switch transistor to a voltage lower than one of the low power supply voltages in the off state increases the off state impedance, which enhances isolation in multi-band applications. When the NMOS switch transistor is operated in an on state, the NMOS switch transistor can be biased to, for example, a high power supply voltage V₂ Any suitable voltage level for the voltage level. In some configurations, high power supply voltage V₂ One of the regulated voltages may be generated by a wafer or an off-chip regulator. Use a regulator to generate a high power supply voltage V₂ It can help control the NMOS switch transistor to operate in an open state having a voltage level relative to temperature, voltage voltage level, and/or relatively constant current load. In some configurations, a silicon-on-insulator (SOI) program is used to fabricate IC 10, and switch 12 can include an SOI transistor. However, there are other configurations available. 2 is a schematic block diagram of one embodiment of a wireless device 11. The exemplary wireless device 11 depicted in FIG. 2 may represent a multi-band and/or multi-mode device such as a multi-band/multi-mode mobile phone. In the illustrated configuration, the wireless device 11 includes a switch 12, a transceiver 13, an antenna 14, a power amplifier 17, a control component 18, a computer readable medium 19, a processor 20, a battery 21, A charge pump 22 and a switch controller 23. The transceiver 13 can generate RF signals for transmission via the antenna 14. Additionally, transceiver 13 can receive input RF signals from antenna 14. It should be understood that various functions associated with the transmission and reception of RF signals can be achieved by one or more components, collectively represented in FIG. 2 as transceivers 13. For example, a single component can be configured to provide both transmission and reception functions. In another example, the transmission and reception functions may be provided by separate components. Similarly, it should be understood that a variety of antenna functions associated with the transmission and reception of RF signals can be achieved by one or more components, collectively represented in FIG. 2 as antenna 14. For example, a single antenna can be configured to provide both transmission and reception functions. In another example, transmission and reception functions may be provided by separate antennas. In yet another example, different antennas can be utilized to provide different frequency bands associated with wireless device 11. In FIG. 2, one or more output signals from transceiver 13 are depicted as being provided to antenna 14 via one or more transmission paths 15. In the example shown, different transmission paths 15 may represent output paths associated with different frequency bands and/or different power outputs. For example, the two exemplary power amplifiers 17 shown may represent amplification associated with different power output configurations (eg, low power output and high power output) and/or amplification associated with different frequency bands. Although FIG. 2 illustrates the configuration using one of the two transmission paths 15, the wireless device 11 can be adapted to include more or fewer transmission paths 15. The power amplifier 17 can be used to amplify, for example, Global System for Mobile (GSM) signals, coded multiple access (CDMA) signals, W-CDMA signals, wireless local area network (WLAN) signals, Long Term Evolution (LTE) signals, and/or Or a variety of RF signals for EDGE signals. In FIG. 2, one or more detected signals from antenna 14 are depicted as being provided to transceiver 13 via one or more receive paths 16. In the example shown, different receive paths 16 may represent paths associated with different frequency bands. Although FIG. 2 illustrates the configuration using one of the four receive paths 16, the wireless device 11 can be adapted to include more or fewer receive paths 16. To facilitate switching between the receive path and the transmit path, switch 12 can be configured to electrically connect antenna 14 to a selected transmit or receive path. Thus, switch 12 can provide several switching functions associated with operation of one of wireless devices 11. In some configurations, switch 12 can include providing for association with, for example, switching between different frequency bands, switching between different power modes, switching between transmission modes and reception modes, or the like. Several switches of function. Switch 12 can also provide additional functionality including filtering and/or duplexing of the signals. Charge pump 22 can be used to generate a charge pump voltage that can be used in wireless device 11 for a variety of purposes. For example, in some configurations, the charge pump voltage generated by charge pump 22 can be provided to switch controller 23 and partially for biasing switch 12. 2 shows that in some configurations, a control component 18 can be provided for controlling various operations associated with operation of switch 12, power amplifier 17, charge pump 22, switch controller 23, and/or other operational components. control function. In some configurations, control component 18 generates a mode signal and/or one or more switch enable signals that are provided to switch controller 23. Thus, control component 18 can be used to operate switch controller 23 in a standby mode at certain times. When operating in the standby mode, control component 18 can disable or turn off charge pump 22 using the mode signal. In some configurations, a processor 20 can be configured to facilitate the implementation of the various programs described herein. The processor 20 can operate using computer program instructions. These computer program instructions can be provided to the processor 20. In some configurations, the computer program instructions can also be stored in a computer readable memory 19 that can direct the processor 20 or other programmable data processing device to operate in a particular manner. Battery 21 can be used in any suitable battery in wireless device 11, including, for example, a lithium ion battery. In some configurations, one of the battery voltages generated by battery 21 is adjusted to produce a portion for controlling a high power supply voltage of one of switches 12. 3 is a schematic block diagram of one embodiment of a power amplifier system 40. The illustrated power amplifier system 40 includes an RF switching circuit 27 that includes a series switching transistor 25 and a parallel switching transistor 26. The illustrated power amplifier system 40 further includes a charge pump 22, a switch controller 23, a directional coupler 24, a power amplifier bias circuit 30, a power amplifier 32, and a transceiver 33. The illustrated transceiver 33 includes a baseband processor 34, an I/Q modulator 37, a mixer 38, and an analog-to-digital converter (ADC) 39. Although not shown in FIG. 3 for clarity, transceiver 33 may include circuitry associated with receiving signals via one or more receive paths. The baseband signal processor 34 can be used to generate an in-phase (I) signal and a quadrature phase (Q) signal that can be used to represent a sine wave or a signal having a desired amplitude, frequency, and phase. For example, an I signal can be used to represent one of the sinusoidal in-phase components and a Q signal can be used to represent one of the sine waves that can be equivalent to one of the sine waves. In some embodiments, the I and Q signals can be provided to the I/Q modulator 37 in a digital format. The baseband processor 34 can be any suitable processor configured to process a baseband signal. For example, baseband processor 34 can include a digital signal processor, a microprocessor, a programmable code, or any combination thereof. Moreover, in some embodiments, two or more baseband processors 34 may be included in power amplifier system 40. I/Q modulator 37 can be configured to receive I and Q signals from baseband processor 34 and process the I and Q signals to produce an RF signal. For example, the I/Q modulator 37 can include a DAC that is configured to convert the I and Q signals into an analog format, a mixer that is used to upconvert the I and Q signals to a radio frequency; And a signal combiner for combining the upconverted I and Q signals into one of RF signals suitable for amplification by power amplifier 32. In some embodiments, I/Q modulator 37 can include one or more filters configured to filter the frequency content of the signals processed therein. Power amplifier bias circuit 30 can receive an enable signal ENABLE from base frequency processor 34 and can use the enable signal ENABLE to generate one or more bias signals for power amplifier 32. Power amplifier 32 can receive RF signals from I/Q modulator 37 of transceiver 33. The switch controller 23 can turn the series switch transistor 25 and the parallel switch transistor 26 on and off in a complementary manner. For example, the switch controller 23 can be used to turn on the series switch transistor 25 and turn off the parallel switch transistor 26 such that the power amplifier 32 provides an amplified RF signal to the antenna 14 through the series switch transistor 25. Additionally, the switch controller 23 can be used to turn off the series switch transistor 25 and turn on the parallel switch transistor 26 to provide a high impedance path between the output of the power amplifier 32 and the antenna 14, while providing the terminal to the power amplifier. Output. To control the state of one of the RF switching circuits 27, the switch controller 23 can receive a switch enable signal (not shown in FIG. 3) from any suitable circuit, such as the control assembly 18 of FIG. The directional coupler 24 can be positioned between the output of the power amplifier 32 and the source of the series switching transistor 25, thereby allowing one of the power amplifiers 32 of the power amplifier 32 that does not include the insertion loss of the series switching transistor 25. The sensed output signal from directional coupler 24 can be provided to a mixer 38 that can multiply the sensed output signal by a reference signal having a controlled frequency for down-frequency shift sensing The frequency content of the output signal is used to produce a signal that is shifted down. The down-shifted signal can be provided to an ADC 39 that can convert the down-shifted signal into a digital format suitable for processing by the baseband processor 34. By including a feedback path between the output of power amplifier 32 and baseband processor 34, baseband processor 34 can be configured to dynamically adjust the I and Q signals to optimize operation of power amplifier 40. For example, configuring power amplifier system 40 in this manner can help control power added efficiency (PAE) and/or linearity of power amplifier 32. In the illustrated configuration, power pump 22 provides a charge pump voltage to switch controller 23 for controlling series switching transistor 25 and parallel switching transistor 26. In some configurations, the charge pump voltage is used to bias the series switching transistor 25 and/or the parallel switching transistor 26 when the series switching transistor 25 and/or the parallel switching transistor 26 are off. Gate voltage. For example, charge pump 22 can generate a negative charge pump voltage for turning off one of series-connected switching transistor 25 and/or parallel switching transistor 26. While the switch controller 23 is illustrated as generating switch control signals for the two transistors, the switch controller 23 can be adapted to control more or fewer switch control transistors. For example, a switch controller can receive a plurality of switch enable signals and generate a plurality of switch control signals for controlling different RF switching circuits.Overview of examples of switch controllers Apparatus and methods for controlling radio frequency (RF) switches are disclosed. In some configurations, a switch controller includes a quasi-shifter control circuit and a quasi-shifter. The level shifter control circuit generates a bias voltage for biasing the level shifter and controls the bias voltage to a different voltage level based on a state of a mode signal. Powered by a high power supply voltage and a charge pump voltage to the level shifter. When the mode signal is in a first state, the level shifter level shifts a switch enable signal to generate one or more switch control signals for one or more RF switches. Additionally, the level shifter control circuit generates a bias voltage to have a tracking charge pump voltage to assist in the level shifter level shift switch enable signal voltage level. However, when the mode signal is in a second state, one of the charge pump voltages can be deactivated. Thus, the level shifter control circuit can control the bias voltage to a fixed voltage level and can control the charge pump voltage and one or more switch control signals to turn off the RF switch. Thus, when the mode signal is in a first state, the level shifter level shifts the switch enable signal to generate one of the voltage levels associated with a high power supply voltage and/or a charge pump voltage or Multiple switch control signals. In addition, when the mode signal is in a second state, the level shifter control circuit can control the charge pump voltage and one or more level shifters to a voltage level of a low power supply voltage to turn off the RF switch. . Thus, the switch controller can be used to control the RF switch to the desired voltage level even when operating in the second state. 4 is a schematic block diagram of one embodiment of a switch controller 50. The switch controller 50 includes a one-position shifter 51 and a one-bit shifter control circuit 52. As shown in FIG. 4, the level shifter 51 receives a switch enable signal SW._EN And generating a switch control signal SW that can be used to turn on or off an RF switch (eg, an NMOS transistor)_CTL . In some configurations, the level shifter 51 produces two or more switch control signals. For example, in some configurations, the level shifter 51 can generate a non-inverting switch control signal for controlling a series RF switch (eg, the series switching transistor 25 of FIG. 3) and for An inverted switch control signal is controlled by one of the parallel RF switches (e.g., the parallel switch transistor 26 of FIG. 3). However, there are other configurations available. The illustrated level shifter 51 includes an NMOS stacked transistor 56 and a PMOS stacked transistor 57. In some configurations, each of the NMOS stacked transistors 56 is paired with one of the PMOS stacked transistors 57, and each pair of transistors is stacked in series or disposed at a high power supply voltage V.₂ With a charge pump voltage V_CP between. As shown in FIG. 4, one of the bias voltages V is generated by the level shifter control circuit 52._BIAS Biased to NMOS stacked transistor 56 and using a low power supply voltage V₁ The PMOS stacked transistor 57 is biased. The level shifter control circuit 52 receives one of the plurality of states operable to include a first state and a second state. In addition, the level shifter control circuit 52 controls the bias voltage V based on the state of the mode signal MODE._BIAS One of the voltage levels. The illustrated level shifter control circuit 52 includes a charge pump voltage V_CP One of the voltage levels together changes one of the stacked reference voltages to overlap the reference circuit 61. In some configurations, the level shifter control circuit 52 can control the bias voltage V when the mode signal MODE is in the first state._BIAS To the splicing reference voltage. In addition, when the mode signal MODE is in the second state, the level shifter control circuit 52 can control the bias voltage V._BIAS To such as high power supply voltage V₂ One of the voltage levels or any other suitable DC voltage is substantially a fixed voltage. The level shifter control circuit 52 further includes a one of the standby control circuits 62 that assists in providing control when the mode signal MODE is in the second state. In some configurations, the level shifter control circuit 52 can control the charge pump voltage V when the mode signal MODE is in the second state._CP One of the voltage levels. For example, when operating in the standby mode, the generation of the charge pump voltage V can be disabled._CP Charge pump, and can float the charge pump voltage V_CP . In some embodiments, the standby control circuit 62 can use the low power supply voltage V when the mode signal MODE is in the second state.₁ Control charge pump voltage V_CP . In some configurations, the standby control circuit 62 can also be used to control the voltage level of one or more of the switch control signals during standby. For example, the standby control circuit 62 can be used to control the switch control signal SW during standby._{C TL} Voltage level to low power supply voltage V₁ . Although FIG. 4 illustrates one configuration in which the switch controller 50 includes a one-position shifter, the switch controller 50 can be adapted to include an additional level shifter. In these configurations, a one-bit shifter control circuit can be shared by all or part of the level shifter. FIG. 5 is a circuit diagram of one embodiment of a one-bit shifter 70. The level shifter 70 includes first to fourth NMOS level shifting transistors 71 to 74, first to first NMOS stacked transistors 81 to 84, and first to fourth PMOS stacked transistors 91 to 94. The first to fourth PMOS levels shift the transistors 101 to 104, a first inverter 107, and a second inverter 108. The level shifter 70 receives a switch enable signal SW_EN And a bias voltage V_BIAS And generating a non-inverting switch control signal SW_CTL And an inverting switch control signal SW_CTLB . As shown in FIG. 5, the first NMOS level shifting transistor 71, the first NMOS stacked transistor 81, the first PMOS stacked transistor 91, and the first PMOS level shifting transistor 101 are stacked or arranged in series. High power supply voltage V₂ With charge pump voltage V_CP between. In addition, the second NMOS level shifting transistor 72, the second NMOS stacked transistor 82, the second PMOS stacked transistor 92, and the second PMOS level shifting transistor 102 are stacked on the high power supply voltage V.₂ With charge pump voltage V_CP between. In addition, the third NMOS level shifting transistor 73, the third NMOS stacked transistor 83, the third PMOS stacked transistor 93, and the third PMOS level shifting transistor 103 are stacked on the high power supply voltage V.₂ With charge pump voltage V_CP between. In addition, the fourth NMOS level shifting transistor 74, the fourth NMOS stacked transistor 84, the fourth PMOS stacked transistor 94, and the fourth PMOS level shifting transistor 104 are stacked on the high power supply voltage V.₂ With charge pump voltage V_CP between. Use bias voltage V_BIAS Biasing the gates of the first to fourth NMOS stacked transistors 81 to 84, and using a low power supply voltage V₁ The gates of the first to fourth PMOS stacked transistors 91 to 94 are biased. The gate of the first NMOS level shifting transistor 71 and the gate of the third NMOS level shifting transistor 73 are electrically connected to the drain of the second NMOS level shifting transistor 72. In addition, the gate of the second NMOS level shifting transistor 72 and the gate of the fourth NMOS level shifting transistor 74 are electrically connected to the drain of the third NMOS level shifting transistor 73. Use high power supply voltage V₂ And low power supply voltage V₁ Power is supplied to the first inverter 107 and the second inverter 108. In addition, the first inverter 107 includes a receiving switch enable signal SW_EN One input and the switch enable signal SW_EN An inverted version is provided to the input of the second inverter 108, to the gate of the second PMOS level shift transistor 102 and to the gate of the fourth PMOS level shift transistor 104. The second inverter 108 includes a switch enable signal SW_EN One non-inverted version is provided to the gate of the first level shift PMOS transistor 101 and to the gate of the third level shift PMOS transistor 103. The level shifter 70 of FIG. 5 illustrates one embodiment of one of the level shifters that can be used in the switch controller 50 of FIG. However, other configurations of the level shifter can be used in accordance with the teachings herein. Referring to FIG. 4 and FIG. 5, when the mode signal MODE is in the first state, the level shifter 70 illustrated in FIG. 5 can set the switch enable signal SW._EN Self and high power supply voltage V₂ And low power supply voltage V₁ Associate one of the voltage domain levels to shift to a high power supply voltage V₂ And charge pump voltage V_CP Associated with one of the voltage domains. For example, when the switch enable signal SW_EN Non-inverting switch control signal SW when logic high_CTL Can have approximately equal to a high power supply voltage V₂ One of the voltage levels, the voltage level and the inverting switch control signal SW_CTLB Can have approximately equal charge pump voltage V_CP One of the voltage levels is a voltage level. In addition, when the switch enable signal SW_EN Non-inverting switch control signal SW when logic is low_CTL Can have approximately equal charge pump voltage V_CP One of the voltage levels, the voltage level and the inverting switch control signal SW_CTLB Can have approximately equal to a high power supply voltage V₂ One of the voltage levels is a voltage level. Bias voltage V_BIAS There is one of the voltage levels based on one of the state changes of the mode signal MODE. For example, when the mode signal MODE is in the first state, the bias voltage V_BIAS The voltage level can be generated by a stacked reference circuit and can dynamically track the charge pump voltage V_CP . Configure the bias voltage V in this way_BIAS Can help in the presence of charge pump voltage V_CP The gates of the NMOS stacked transistors 81 to 84 are biased during the level shifting operation of the level shifter 70 in the event of a change and/or settling. However, when the mode signal MODE is in the second state, the charge pump voltage V can be turned off._CP The charge pump. In addition, the level shifter control circuit 52 can control the bias voltage V._BIAS To such as high power supply voltage V₂ One of the voltages is a fixed voltage level. Therefore, the bias voltage V_BIAS The voltage level can be changed based on a state of the mode signal MODE. With continued reference to Figures 4 and 5, in some configurations, the level shifter control circuit 52 is configured to control the charge pump voltage V during standby._CP Voltage level and non-inverting switch control signal SW_CTL And inverting switch control signal SW_CTLB The voltage level. For example, when the mode signal MODE is in the second state, the level shifter control circuit 52 is configured to use the low power supply voltage V.₁ Control charge pump voltage V_CP Voltage level and non-inverting switch control signal SW_CTL And inverting switch control signal SW_CTLB The voltage level. Additional details of the level shifter 70 can be as previously described. 6 is a circuit diagram of one embodiment of a one-bit shifter control circuit 120. The level shifter control circuit 120 includes a stack reference circuit 61, a standby control circuit 62, a first inverter 135, a first PMOS level shifter control transistor 121, and a second PMOS level. The shifter control transistor 122, an NMOS level shifter control transistor 123, first to fourth NMOS body bias transistors 131 to 134, a first inverter 135 and a second inverter 136 . The level shifter control circuit 120 generates a bias voltage V based on the state of the mode signal MODE_BIAS . The level shifter control circuit 120 of FIG. 6 illustrates one embodiment of a level shifter control circuit that can be used in the switch controller 50 of FIG. However, other configurations of the level shifter control circuit can be used in accordance with the teachings herein. The splicing reference circuit 61 receives the mode signal MODE and the charge pump voltage V_CP . In addition, the splicing reference circuit 61 generates a spliced reference voltage V based on one of the states of the mode signal MODE_CASREF . In some configurations, when the mode signal MODE is in the first state, the reference voltage V is spliced_CASREF Dynamic tracking of charge pump voltage V_CP One of the voltage levels. In addition, when the mode signal MODE is in the second state, the splicing reference circuit 61 can generate the spliced reference voltage V_CASREF To have approximately equal to the low power supply voltage V₁ One of the voltage levels. However, there are other configurations available. Use high power supply voltage V₂ And low power supply voltage V₁ Power is supplied to the first inverter 135 and the second inverter 136. The first inverter 135 includes an input of the receive mode signal MODE and provides an inverted version of the mode signal to the input of the second inverter 136 to the gate of the first PMOS level shifter control transistor 121. And to one of the standby control circuits 62. The second inverter 136 further includes providing a non-inverted version of the mode signal MODE to the gate of the second PMOS level shifter control transistor 122 to the gate of the NMOS level shifter control transistor 123. And to one of the standby control circuits 62. The first PMOS level shifter control transistor 121 and the second PMOS level shifter control transistor 122 and the NMOS level shifter control transistor 123 can be used to control the bias voltage V._BIAS The voltage level. For example, when the mode signal MODE is logic high, the first PMOS level shifter control transistor 121 and the NMOS level shifter control transistor 123 can be turned on to control the bias voltage V._BIAS The voltage level is approximately equal to the splicing reference voltage V_CASREF . Configuring the level shifter control circuit 120 to include parallel operation to control the bias voltage V_BIAS One PMOS transistor and one NMOS transistor can help provide a robust electrical connection across a program, supply voltage, and/or temperature variation. In addition, when the mode signal MODE is logic low, the second PMOS level shifter controls the transistor 122 to control the bias voltage V._BIAS The voltage level is approximately equal to the high power supply voltage V₂ . The first to fourth NMOS body bias transistors 131 to 134 are operable to bias the bodies of the first PMOS level shifter control transistor 121 and the second PMOS level shifter control transistor 122. As shown in FIG. 6, the first NMOS body bias transistor 131 and the second NMOS body bias transistor 132 are electrically connected in series to the spliced reference voltage V._CASREF With bias voltage V_BIAS The third NMOS body bias transistor 133 and the fourth NMOS body bias transistor 134 are electrically connected in series to the bias voltage V._BIAS With high power supply voltage V₂ between. In addition, the gate of the second NMOS body bias transistor 132 is electrically connected to the spliced reference voltage V._CASREF The gate of the third NMOS body bias transistor 133 is electrically connected to the high power supply voltage V₂ And the gates of the first NMOS body bias transistor 131 and the fourth NMOS body bias transistor 134 are electrically connected to the bias voltage V_BIAS . Configuring the NMOS body bias transistors 131 to 134 in this manner can help bias the body of the first PMOS level shifter control transistor 121 and the second PMOS level shifter control transistor 122 to prevent parasitic The drain-to-body and/or source-to-body diodes become forward biased during various operating conditions. When the mode signal MODE is in the first state (normal operation mode), a charge pump (not shown in FIG. 6) can be used to control the charge pump voltage V._CP . When the mode signal MODE is in the second state (standby state), the standby control circuit 62 can be used to control the charge pump voltage V._CP Up to approximately equal to the low power supply voltage V₁ . In some configurations, the standby control circuit 62 can also be used to control one or more switch control signals (such as the switch control signal SW) when the mode signal MODE is in the second state._CT One of the states. FIG. 7 is a circuit diagram of one embodiment of a spliced reference circuit 150. The splicing reference circuit 150 includes first to seventh NMOS voltage divider transistors 151 to 157, a first NMOS control transistor 161, a second NMOS control transistor 162, a PMOS control transistor 163, and an inverter. 165 and a bypass capacitor 167. The splicing reference circuit 150 of FIG. 7 includes one embodiment of a splicing reference circuit that may be included in a level shifter control circuit such as the level shifter control circuit 120 of FIG. However, other configurations of the spliced reference circuit can be used in accordance with the teachings herein. First to seventh NMOS voltage divider transistors 151 to 157 at charge pump voltage V_CP With high power supply voltage V₂ The electrical connection is made in series with the PMOS control transistor 163. As shown in FIG. 7, the first to seventh NMOS voltage divider transistors 151 to 157 are each connected via a diode and at a high power supply voltage V.₂ With charge pump voltage V_CP It is configured as a voltage divider. Although one example of a voltage divider is illustrated, a voltage divider can be implemented in other ways including, for example, using more or fewer transistors and/or configuration using other electrical components such as resistors. Use high power supply voltage V₂ And power supply voltage V₁ Power is supplied to the inverter 165. The inverter 165 includes one input of the reception mode signal MODE and provides an inverted version of the mode signal to the PMOS control transistor 163 and one of the gates of the first NMOS control transistor 161 and the second NMOS control transistor 162. . When the mode signal MODE is logic high, the first NMOS control transistor 161 and the second NMOS control transistor 162 can be turned off and the PMOS control transistor 163 can be turned on. Additionally, the first through seventh NMOS voltage divider transistors 151 through 157 are operable to generate approximately equal to V_CP +4/7*(V₂ -V_CP Stacked reference voltage V_CASREF One of the voltage dividers. Therefore, the reference voltage V is spliced_CASREF The charge pump voltage V can be dynamically tracked in the first state of one of the mode signals MODE_CP . However, when the mode signal MODE is logic low, the first second NMOS control transistor 161 and the second NMOS control transistor 162 can be turned on and the PMOS control transistor 163 can be turned off. In this configuration, the splicing reference voltage V can be controlled_CASREF Low power supply voltage V₁ The voltage level. The illustrated configuration includes a drain electrically connected to the PMOS control transistor 163 and a spliced reference voltage V_CASREF A bypass capacitor 167 between. Including bypass capacitor 167 can help reduce the overlap reference voltage V_CASREF The noise. FIG. 8 is a circuit diagram of one embodiment of a standby control circuit 180. The standby control circuit 180 includes an NMOS charge pump voltage control transistor 183, a first NMOS standby control transistor 181, a second NMOS standby control transistor 182, a PMOS stacked transistor 191, and an NMOS stacked transistor 192. A first PMOS standby control transistor 193, a second standby control transistor 194, first to third NMOS switch control transistors 201 to 203, and first to third NMOS switches control the stacked transistors 211 to 213. Standby control circuit 180 of FIG. 8 illustrates one embodiment of a standby control circuit that may be included in a level shifter control circuit, such as level shifter control circuit 120 of FIG. However, other configurations of the standby control circuit can be used in accordance with the teachings herein. The first NMOS standby control transistor 181, the PMOS stacked transistor 191, and the first PMOS standby control transistor 193 are electrically connected in series to the charge pump voltage V._CP With high power supply voltage V₂ between. In addition, the second NMOS standby control transistor 182, the NMOS stacked transistor 192, and the second standby control transistor 194 are electrically connected in series to the charge pump voltage V._CP With high power supply voltage V₂ between. The gate of the first NMOS standby control transistor 181 is electrically connected to the drain of the second NMOS standby control transistor 182, and the gate of the second NMOS standby control transistor 182 is electrically connected to the first NMOS standby control transistor 181. Bungee jumping. In addition, the gate of the PMOS stacked transistor 191 is electrically connected to the low power supply voltage V.₁ And the gate of the NMOS stacked transistor 192 is electrically connected to the bias voltage V_BIAS . In addition, the gate of the first PMOS standby control transistor 193 is electrically connected to the mode signal MODE, and the gate of the second PMOS standby control transistor 194 is electrically connected to the inverted mode signal MODEB. NMOS charge pump voltage control transistor 183 includes electrical connection to charge pump voltage V_CP One source and body, electrically connected to a low power supply voltage V₁ One of the drains is electrically connected to one of the gates of the first NMOS standby control transistor 181. When the mode signal MODE is logic high, the NMOS charge pump charge control transistor 183 can be turned off and a charge pump can generate the charge pump voltage V._CP To have less than a low power supply voltage V₁ One of the voltage levels is a voltage level. However, when the mode signal MODE is logic low, the NMOS charge pump voltage control transistor 183 can be turned on, and the standby control circuit 180 can control the charge pump voltage V._CP To have approximately equal to the low power supply voltage V₁ One of the voltage levels is a voltage level. Therefore, the standby control circuit 180 can be used to prevent the charge pump voltage V_CP Float during standby mode. In the illustrated configuration, the standby control circuit 180 is illustrated as including a first switch control signal SW_CTL1 a second switch control signal SW_{CTL 2} And a third switch control signal SW_{CTL 3} The associated switch controls the transistor. The first to third switch control signals SW may be generated by level shifters associated with different switches_CTL1 To SW_CTL3 . While one of the configurations associated with the three switch control signals is shown, the standby control circuit 180 can be adapted to provide standby control for more or fewer switch control signals. The gates of the first to third NMOS switch control transistors 201 to 203 are electrically connected to the drain of the first NMOS standby control transistor 181. In addition, the first to third NMOS switches control the gates of the stacked transistors 211 to 213 to be electrically connected to the bias voltage V._BIAS . The first NMOS switch control transistor 201 and the first NMOS switch control stack transistor 211 are electrically connected in series. Similarly, the second NMOS switch control transistor 202 and the second NMOS switch control the stacked transistor 212 are electrically connected in series, and the third NMOS switch control transistor 203 and the second NMOS switch control the stacked transistor 213 are connected in series. connection. When the mode signal MODE is logic high, the first to third NMOS switch control transistors 201 to 203 may be turned off and the standby control circuit 180 should not control the first to third switch control signals SW_CTL1 To SW_CTL3 . Configuring the standby control circuit 180 in this manner can prevent the standby control circuit 180 from interfering with controlling the first to third switch control signals SW during normal operation._CTL1 To SW_{CTL 3} The operation of the voltage level level shifter. However, when the mode signal MODE is logic low, the switch controller is operable in a standby mode, and the standby control circuit 180 can control the first to third switch control signals SW_CTL1 To SW_CTL3 Each of them is approximately equal to a low power supply voltage V₁ . 9 is a schematic block diagram of one of RF systems 200 in accordance with an embodiment. The RF system 200 includes a charge pump 22, a first RF switch 201a, a second RF switch 201b, a third RF switch 201c, and a switch controller 203. Although RF system 200 is depicted as including three RF switches, RF system 200 can be adapted to include more or fewer RF switches. The charge pump 22 receives a mode signal MODE and generates a charge pump voltage V_CP . The charge pump 22 is enabled in one of the first states of the mode signal MODE and the charge pump 22 is deactivated in one of the second states of the mode signal MODE. For example, the first state may indicate one of the RF system 200 normal operating modes and the second state may indicate one of the RF system 200 standby modes. The switch controller 203 receives the mode signal MODE and a first switch enable signal SW_EN1 a second switch enable signal SW_{EN 2} And a third switch enable signal SW_{EN 3} . In addition, the switch controller 203 generates a first switch control signal SW for controlling one of the first RF switches 201a._CTL1 For controlling one of the second RF switch 201b, the second switch control signal SW_{CTL 2} And a third switch control signal SW for controlling one of the third RF switches 201c_{CTL 3} . The illustrated switch controller 203 includes a one-bit shifter control circuit 252, a first level shifter 251a, a second level shifter 251b, and a third level shifter 251c. The level shifter control circuit 252 can operate in a manner similar to that of the level shifter control circuit 52 of FIG. In addition, the level shifters 251a to 251c can operate in a manner similar to that of the level shifter 51 of FIG. Although the illustrated switch controller includes three level shifters, the switch controller can include more or fewer level shifters. Additional details of the RF system 200 can be as previously described. FIG. 10A is a schematic diagram of an embodiment of a package module 300. Figure 10B is a schematic illustration of one of the cross sections of the package module 300 of Figure 10A taken along line 10B-10B. The package module 300 includes an IC or die 301, a surface mount component 303, a wire bond 308, a package substrate 320, and an encapsulation structure 340. The package substrate 320 includes a pad 306 formed of a conductor disposed therein. Additionally, die 301 includes pad 304 and wire bond 308 has been used to electrically connect pad 304 of die 301 to pad 306 of package substrate 301. As shown in FIGS. 10A and 10B, the die 301 includes a charge pump 22, a switch controller 23, and a switch 12, which may be as previously described. The package substrate 320 can be configured to receive a plurality of components, such as die 301 and surface mount component 303, which can include, for example, surface mount capacitors and/or inductors. As shown in FIG. 10B, the display package module 300 includes a plurality of contact pads 332 disposed on a side of the package module 300 opposite the side for mounting the die 301. Configuring the packaged module 300 in this manner can help connect the packaged module 300 to a circuit board such as one of the wireless devices. The exemplary contact pads 332 can be configured to provide RF signals, bias signals, (several) low power voltages, and/or high power voltage(s) to the die 301 and/or surface mount component 303. As shown in FIG. 10B, the electrical connection between the contact pads 332 and the die 301 can be facilitated by the connection 333 through the package substrate 320. Connection 333 may represent an electrical path formed through package substrate 320, such as a connection associated with a via and conductor of a multilayer laminate package substrate. In some embodiments, the package module 300 can also include one or more package structures to, for example, provide protection and/or facilitate handling of the package module 300. The package structure can include a overmold or encapsulation structure 340 formed over the package substrate 320 and the components disposed thereon and the die(s). It will be understood that while package module 300 is described with respect to the context of electrical connections based on wire bonds, one or more features of the present invention may also be implemented in other package configurations including, for example, flip chip configurations.application Some of the embodiments described above have been provided in connection with wireless devices or mobile phones. However, the principles and advantages of the embodiments can be applied to any other system or device having the need for a control circuit for a radio frequency switch. These switching controllers can be implemented in a variety of electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, parts of consumer electronics, electronic test equipment, and the like. Examples of electronic devices may also include, but are not limited to, memory chips, memory modules, circuits of optical networks or other communication networks, and disk drive circuits. Consumer electronics products may include, but are not limited to, a mobile phone, a telephone, a television, a computer monitor, a computer, a handheld computer, a PDA, a microwave oven, a refrigerator, a car, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a video camera, a camera, a digital camera, a portable memory A body wafer, a washer, a clothes dryer, a washer/dryer, a photocopier, a facsimile device, a scanner, a multifunction peripheral, a wristwatch, a clock, and the like. Additionally, the electronic device can include an unfinished product. Conclusion Unless the context clearly requires otherwise, the phrase "comprise", "comprising" and the like should be understood as an inclusive rather than an exclusive or exhaustive. Meaning, meaning "including, but not limited to". The phrase "coupled" as used herein generally means that two or more elements are directly connected or connected by one or more intermediate elements. Similarly, the term "connected" as used herein generally means that two or more elements are directly connected or connected by one or more intermediate elements. In addition, the words "in this article", "above", "below" and similar meanings when used in this application refer to this application as a whole and not to any specific part of the application. . Where the context allows, the use of the singular or negative number of the above-described embodiments may also include negative or singular numbers, respectively. The word "or" refers to a list of two or more items that cover all of the following interpretations of the word: any of the items in the list, all of the items in the list, and the list Any combination of items. In addition, unless specifically stated otherwise or unless understood within the context of the context as used, such as "can", "could", "might", "can", "Conditional language as used herein, such as (eg) / (for example), "such as" and the like, is generally intended to convey that certain embodiments include (and other embodiments do not include) certain features, components and/or status. Therefore, this conditional language is generally not intended to imply that such features, elements, and/or states are required in any manner for one or more embodiments or one or more embodiments must be included for use with or without The logic of the decision, whether or not such features, elements and/or states are included or executed in any particular embodiment. The above description of the embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although the specific embodiments and examples of the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as will be appreciated by those skilled in the art. For example, although a program or block is presented in a given order, alternative embodiments may perform a routine having steps or a system with blocks in a different order, and may be deleted, moved, added, subdivided, combined And/or modify some programs or blocks. Each of these procedures or blocks can be implemented in a number of different ways. In addition, although programs or blocks are sometimes shown in series, they may alternatively be performed in parallel, or such programs or blocks may be executed at different times. The teachings of the present invention provided herein can be applied to other systems and need not be the systems described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. Although certain embodiments of the invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. Of course, the novel methods and systems described herein may be embodied in a variety of other forms and, in addition, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the invention. The scope of the claims and the equivalents thereof are intended to cover such forms or modifications as fall within the scope and spirit of the invention.

5a‧‧‧First pin

5b‧‧‧second pin

10‧‧‧Integrated Circuit (IC)

10B-10B‧‧‧ line

11‧‧‧Wireless devices

12‧‧‧ switch

13‧‧‧ transceiver

14‧‧‧Antenna

15‧‧‧Transmission path

16‧‧‧Receiving path

17‧‧‧Power Amplifier

18‧‧‧Control components

19‧‧‧ Computer readable media

20‧‧‧ processor

21‧‧‧Battery

22‧‧‧Charge pump

23‧‧‧Switch controller

24‧‧‧Directional coupler

25‧‧‧Series Switching Transistor

26‧‧‧Parallel Switching Transistor

27‧‧‧RF (RF) switching circuit

30‧‧‧Power amplifier bias circuit

32‧‧‧Power Amplifier

33‧‧‧ transceiver

34‧‧‧Baseband processor

37‧‧‧I/Q Modulator

38‧‧‧ Mixer

39‧‧‧ Analog to Digital Converter (ADC)

40‧‧‧Power Amplifier System

50‧‧‧Switch controller

51‧‧‧ position shifter

52‧‧‧ level shifter control circuit

56‧‧‧n type metal oxide semiconductor (NMOS) stacked transistor

57‧‧‧p-type metal oxide semiconductor (PMOS) stacked transistor

61‧‧‧Stack reference circuit

62‧‧‧ Standby control circuit

70‧‧‧ position shifter

71‧‧‧First n-type metal oxide semiconductor (NMOS) level shift transistor

72‧‧‧Second n-type metal oxide semiconductor (NMOS) level shifting transistor

73‧‧‧ Third n-type metal oxide semiconductor (NMOS) level shifting transistor

74‧‧‧ Fourth n-type metal oxide semiconductor (NMOS) level shift transistor

81‧‧‧First n-type metal oxide semiconductor (NMOS) stacked transistor

82‧‧‧Second n-type metal oxide semiconductor (NMOS) stacked transistor

83‧‧‧ Third n-type metal oxide semiconductor (NMOS) stacked transistor

84‧‧‧Fourth n-type metal oxide semiconductor (NMOS) stacked transistor

91‧‧‧First p-type metal oxide semiconductor (PMOS) stacked transistor

92‧‧‧Second p-type metal oxide semiconductor (PMOS) stacked transistor

93‧‧‧ Third p-type metal oxide semiconductor (PMOS) stacked transistor

94‧‧‧ Fourth p-type metal oxide semiconductor (PMOS) stacked transistor

101‧‧‧First p-type metal oxide semiconductor (PMOS) level shift transistor

102‧‧‧Second p-type metal oxide semiconductor (PMOS) level shift transistor

103‧‧‧ Third p-type metal oxide semiconductor (PMOS) level shift transistor

104‧‧‧ Fourth p-type metal oxide semiconductor (PMOS) level shift transistor

107‧‧‧First Inverter

108‧‧‧Second inverter

120‧‧‧ level shifter control circuit

121‧‧‧First p-type metal oxide semiconductor (PMOS) level shifter control transistor

122‧‧‧Second p-type metal oxide semiconductor (PMOS) level shifter control transistor

123‧‧‧n type metal oxide semiconductor (NMOS) level shifter control transistor

131‧‧‧First n-type metal oxide semiconductor (NMOS) body bias transistor

132‧‧‧Second n-type metal oxide semiconductor (NMOS) body bias transistor

133‧‧‧ Third n-type metal oxide semiconductor (NMOS) body bias transistor

134‧‧‧4th n-type metal oxide semiconductor (NMOS) body bias transistor

135‧‧‧First Inverter

136‧‧‧Second inverter

150‧‧‧Stack reference circuit

151‧‧‧First n-type metal oxide semiconductor (NMOS) voltage divider transistor

152‧‧‧Second n-type metal oxide semiconductor (NMOS) voltage divider transistor

153‧‧‧ Third n-type metal oxide semiconductor (NMOS) voltage divider transistor

154‧‧‧ Fourth n-type metal oxide semiconductor (NMOS) voltage divider transistor

155‧‧‧ Fifth n-type metal oxide semiconductor (NMOS) voltage divider transistor

156‧‧‧6th n-type metal oxide semiconductor (NMOS) voltage divider transistor

157‧‧‧ seventh n-type metal oxide semiconductor (NMOS) voltage divider transistor

161‧‧‧First n-type metal oxide semiconductor (NMOS) controlled transistor

162‧‧‧Second n-type metal oxide semiconductor (NMOS) controlled transistor

163‧‧‧p-type metal oxide semiconductor (PMOS) control transistor

165‧‧‧Inverter

167‧‧‧Bypass capacitor

180‧‧‧ Standby control circuit

181‧‧‧First n-type metal oxide semiconductor (NMOS) standby control transistor

182‧‧‧Second n-type metal oxide semiconductor (NMOS) standby control transistor

183‧‧‧n type metal oxide semiconductor (NMOS) charge pump voltage controlled transistor

191‧‧‧p-type metal oxide semiconductor (PMOS) stacked transistor

192‧‧‧n type metal oxide semiconductor (NMOS) stacked transistor

193‧‧‧First PMOS Standby Control Cell

194‧‧‧Second standby control transistor

200‧‧‧ Radio Frequency (RF) System

201‧‧‧First n-type metal oxide semiconductor (NMOS) switch control transistor

201a‧‧‧First Radio Frequency (RF) Switch

201b‧‧‧second radio frequency (RF) switch

201c‧‧‧ Third Radio Frequency (RF) Switch

202‧‧‧Second n-type metal oxide semiconductor (NMOS) switch control transistor

203‧‧‧ Third n-type metal oxide semiconductor (NMOS) switch control transistor

211‧‧‧First n-type metal oxide semiconductor (NMOS) switch control stacked transistor

212‧‧‧Second n-type metal oxide semiconductor (NMOS) switch control stacked transistor

213‧‧‧ Third n-type metal oxide semiconductor (NMOS) switch control stacked transistor

251a‧‧‧first position shifter

251b‧‧‧second position shifter

251c‧‧‧ third position shifter

252‧‧‧ Position shifter control circuit

300‧‧‧Package Module

301‧‧‧Integrated Circuit (IC) / Grain

303‧‧‧Surface mount components

304‧‧‧ pads

306‧‧‧ pads

308‧‧‧Wire joints

320‧‧‧Package substrate

332‧‧‧Contact pads

333‧‧‧Connect

340‧‧‧encapsulated structure

1 is a schematic diagram of one embodiment of an integrated circuit (IC). 2 is a schematic block diagram of one embodiment of a wireless device. 3 is a schematic block diagram of one embodiment of a power amplifier system. 4 is a schematic block diagram of one embodiment of a switch controller. Figure 5 is a circuit diagram of one embodiment of a one-bit shifter. Figure 6 is a circuit diagram of one embodiment of a one-bit shifter control circuit. Figure 7 is a circuit diagram of one embodiment of a stacked reference circuit. Figure 8 is a circuit diagram of one embodiment of a standby control circuit. 9 is a schematic block diagram of one of the radio frequency systems in accordance with an embodiment. Figure 10A is a schematic illustration of one embodiment of a packaged module. Figure 10B is a schematic illustration of one of the cross-sections of the packaged module of Figure 10A taken along line 10B-10B.

Claims (20)

A radio frequency system comprising: a quasi-shifter operable to provide a level shift to an input signal, the level shifter being biased by a bias voltage and coupled by a supply voltage a charge pump voltage supply; a charge pump configured to provide the charge pump voltage and receive a mode signal operative to enable the charge pump in a first state and deactivate in a second state a charge pump; and a quasi-shifter control circuit configured to control the bias voltage to track the charge pump voltage when the mode signal is in the first state, and when the mode signal is at the The supply voltage is used to control the bias voltage in the two states. The radio frequency system of claim 1, further comprising one of the radio frequency switches controlled by the level shifter. The radio frequency system of claim 1, wherein the level shifter control circuit is further configured to control a voltage level of the charge pump voltage to a ground voltage when the mode signal is in the second state. The radio frequency system of claim 1, wherein the level shifter comprises at least one stacked transistor, the at least one stacked transistor having a gate controlled by the bias voltage. The radio frequency system of claim 4, wherein the level shifter control circuit includes a voltage divider configured to generate a voltage difference between the supply voltage and the charge pump voltage A stack of reference voltages is configured, the level shifter control circuit being configured to control the bias voltage using the stacked reference voltage when the mode signal is in the first state. The radio frequency system of claim 5, wherein the level shifter control circuit comprises operating in parallel when the mode signal is in the first state to electrically connect the splicing reference voltage to one of the bias voltages n-type metal An oxide semiconductor transistor and a p-type metal oxide semiconductor transistor. The radio frequency system of claim 5, wherein the voltage divider comprises a plurality of diode-connected transistors electrically connected in series. A packaged module for a radio frequency system, the packaged module comprising: a package substrate; and an integrated circuit attached to the package substrate, the integrated circuit including an operable circuit to provide a level shift to An input level shifter configured to receive a bias voltage of one of the level shifters and receive power from a supply voltage and a charge pump voltage, the product The body circuit further includes a charge pump configured to provide the charge pump voltage and receive a mode signal operative to enable the charge pump in a first state and to stop in a second state Using the charge pump, and a quasi-shifter control circuit, the level shifter control circuit is configured to control the bias voltage to track the charge pump voltage when the mode signal is in the first state, And using the supply voltage to control the bias voltage when the mode signal is in the second state. The packaged module of claim 8, wherein the integrated circuit further comprises an RF switch controlled by the level shifter. The packaged module of claim 8, wherein the level shifter control circuit is further configured to control a voltage level of the charge pump voltage to a ground voltage when the mode signal is in the second state. The packaged module of claim 8, wherein the level shifter comprises at least one stacked transistor, the at least one stacked transistor having a gate controlled by the bias voltage. The packaged module of claim 11, wherein the level shifter control circuit includes a voltage divider configured to be based on a voltage difference between the supply voltage and the charge pump voltage To generate a spliced reference voltage, the level shifter control circuit is configured to control the bias voltage using the spliced reference voltage when the mode signal is in the first state. The packaged module of claim 12, wherein the level shifter control circuit includes parallel operation when the mode signal is in the first state to electrically connect the spliced reference voltage to one of the bias voltages n A metal oxide semiconductor transistor and a p-type metal oxide semiconductor transistor. The packaged module of claim 12, wherein the voltage divider comprises a plurality of diode-connected transistors electrically connected in series. A method of level shifting in a radio frequency system, the method comprising: using a charge pump to generate a charge pump voltage, including enabling the charge pump when a mode signal is in a first state, and when the mode signal Disabling the charge pump in a second state; using a supply voltage and the charge pump voltage to power the one-bit shifter; using a bias voltage to bias the level shifter; a shifter control circuit to generate the bias voltage, including controlling the bias voltage to track the charge pump voltage when the mode signal is in the first state, and using the mode signal when the mode signal is in the second state Supplying a voltage to control the bias voltage; and using the level shifter to shift an input signal level. The method of claim 15, further comprising using the level shifter to control an RF switch. The method of claim 15, further comprising using the level shifter control circuit to control a voltage level of the charge pump voltage to a ground voltage when the mode signal is in the second state. The method of claim 15, further comprising using the bias voltage to control one of the gates of the at least one stacked transistor of the level shifter. The method of claim 18, wherein generating the bias voltage comprises using a voltage divider to generate a splicing reference voltage based on a voltage difference between the supply voltage and the charge pump voltage, And using the splicing reference voltage to control the bias voltage when the mode signal is in the first state. The method of claim 19, further comprising using the parallel combination of one of an n-type metal oxide semiconductor transistor and a p-type metal oxide semiconductor transistor when the mode signal is in the first state A reference voltage is connected to the bias voltage.