TWI643069B - Dynamic management of flash memory - Google Patents

Abstract

In a dynamic management method of NAND flash memory, a write command is first received from a host. Next, it is determined whether the NAND flash memory has passed the initial stage of its life. If the NAND flash memory is still in its early life, the first portion of the NAND flash memory is taken as the SLC cache memory. If the NAND flash memory has passed its initial life, the second portion of the NAND flash memory is taken as the SLC cache memory. The second portion is smaller than the first portion. The data is written to the SLC cache according to the write command.

Description

Dynamic management of flash memory

The invention relates to dynamic management of flash memory, in particular flash memory.

The flash memory can be classified into SLC (single-level chip) flash memory and MLC (multiple-level chip) flash memory. MLC flash memory is usually TLC (triple-level chip) flash memory. Writing data to the SLC flash memory is faster than writing the data to the TLC flash memory, because the burst write mode can be used to write data to the SLC cache. However, the density of SLC flash memory storage data is less than the density of TLC flash memory storage data. Therefore, NAND flash memory is usually planned into two regions, namely SLC and TLC, to achieve both the speed of writing and the density of storage.

Referring to FIG. 4, a host 10 uses a solid state hard disk 32. The solid state hard disk 32 has a NAND flash memory 34. The NAND flash memory 34 is planned as two flash memories, one being the SLC flash memory 36 and the other being the MLC (multiple-level chip) flash memory 38. Conventionally, the size of the storage space of the SLC flash memory 36 and the size of the storage space of the TLC flash memory 38 are fixed.

In a common use of cache memory, data is first written to the SLC cache memory 36 in burst write mode. Then, when the storage space of the SLC cache memory 36 is about to be used up, the data is moved from the SLC cache memory 36 to TLC flash memory 38.

However, limited by the storage space and over-provision of the NAND flash memory 34, the storage space of the SLC cache memory 36 typically only occupies a small portion of the storage space of the NAND flash memory 34. By convention, the storage space of the SLC cache memory 36 is typically less than 3% of the storage space of the NAND flash memory 34. Therefore, the burst write mode can only last for a short period of time, and then the speed of writing data to the flash memory is greatly reduced. In the process of moving larger files or executing benchmark tools, the speed of writing data is often greatly reduced.

In view of the above-mentioned problems of the prior art, it is an object of the present invention to provide a dynamic management method for a flash memory that combines speed and life.

To achieve the above object, the dynamic management method of the flash memory includes the step of receiving a write command from a host. Next, it is determined whether the NAND flash memory has passed the initial stage of its life. If the NAND flash memory is still in its early life, the first portion of the NAND flash memory is taken as the SLC cache memory. If the NAND flash memory has passed its initial life, the second portion of the NAND flash memory is taken as the SLC cache memory, wherein the second portion is smaller than the first portion. Finally, the data is written to the SLC cache according to the write command.

10‧‧‧Host

12‧‧‧ Solid State Drive

14‧‧‧NAND flash memory

16‧‧‧SLC cache memory

18‧‧‧TLC flash memory

32‧‧‧ Solid State Drive

34‧‧‧NAND flash memory

36‧‧‧SLC cache memory

38‧‧‧TLC flash memory

S10‧‧‧ host write command

S12‧‧‧FTL processing write instructions

S14‧‧‧Average erasure times>Threshold?

S16‧‧‧ takes the first part of NAND flash memory as SLC cache memory

S18‧‧‧ takes the second part of NAND flash memory as SLC cache memory

S20‧‧‧Write data from host to SLC

1 is a block diagram of a data storage device managed by the method of the present invention; and FIG. 2 is a flow chart showing a dynamic management method of the data storage device shown in FIG. 1; Figure 3 shows a comparison of the performance of a data storage device managed by the method of the present invention with the performance of a data storage device managed by a conventional method; and Figure 4 is a block diagram of a data storage device managed by a conventional method.

Hereinafter, a preferred embodiment of the dynamic management method of the flash memory of the present invention will be further described with reference to the related drawings. In order to facilitate the understanding of the present invention, the same elements are denoted by the same reference numerals.

As shown in Fig. 1, a host 10 is connected to a solid state hard disk 12. The solid state drive 12 has a NAND flash memory 14. The NAND flash memory 14 is programmed into two flash memories, one being the SLC flash memory 16 and the other being the TLC flash memory 18. According to the present invention, the storage space of the SLC flash memory 16 and the storage space of the TLC flash memory 18 are dynamically adjusted. Therefore, the size of the storage space for dynamically adjusting the SLC flash memory 16 and the size of the storage space of the TLC flash memory 18 are all variable.

As shown in FIG. 2, at S10, the host 10 issues a write command and transmits data.

At S12, the write command is processed by a flash translation layer (FTL) and a backend (BE) instruction is generated.

At S14, the backend instruction is received by a backend, and it is checked whether the average erase count (AEC) is greater than a pre-set threshold. If the average erasure number is not greater than the threshold, the flow goes to S16, otherwise the flow goes to S18.

At S16, the storage space of the SLC cache memory 16 is set to The storage space of the NAND flash memory 14 is about 33%. Then, the flow goes to S20.

At S18, the storage space of the SLC cache memory 16 is set to about 1% of the storage space of the NAND flash memory 14. Then, the flow goes to S20.

At S20, the backend is used to write data to the SLC cache memory 16. In the burst write mode, at the high speed, the back end writes the data contained in the write command to the SLC cache memory 16.

As shown in FIG. 3, if the storage space of the SLC cache memory 16 is set to 33% of the storage space of the NAND flash memory 14, the burst write time is long, due to the storage of the SLC cache memory 16. big space. If the storage space of the SLC cache memory 16 is set to 1% of the storage space of the NAND flash memory 14, the burst write time is short, and the storage space of the SLC cache memory 16 is small.

In the above flow, S14 is performed to determine whether or not the solid state hard disk 12 has passed its initial life. AEC not greater than the threshold indicates that the solid state drive 12 is still in its early life and it can still serve for a long time. Therefore, the solid state hard disk 12 can be used as much as possible, and an appreciable portion (for example, 33%) of the NAND flash memory 14 is set as the SLC cache memory 16. AEC greater than the threshold indicates that the solid state drive 12 has passed its initial life and it can serve for a short time. Therefore, excessive use of the solid state hard disk 12 is avoided, and a small portion (for example, 1%) of the NAND flash memory 14 is set as the SLC cache memory 16. Such a design is to strike a balance between the performance (mainly speed) and lifetime of the solid state drive 12.

The above description is only for the preferred embodiment of the present invention, and is intended to clarify the features of the present invention, and is not intended to limit the scope of the embodiments of the present invention. Changes that are well known to those skilled in the art are still within the scope of the invention.

Claims (4)

A dynamic management method for NAND flash memory, comprising the steps of: receiving a write command from a host (10); determining whether the NAND flash memory (14) has passed its initial life; if the NAND flash memory The body (14) is still in the early stage of life, then taken in the NAND flash memory (14) 33% is treated as the first part as the SLC cache memory (16); if the NAND flash memory (14) passes the initial stage of its lifetime, the second part of the NAND flash memory (14) is taken as The SLC cache memory (16), wherein the second portion is smaller than the first portion; and writing data to the SLC cache memory (16) according to the write command. The method of claim 1, wherein the step of determining whether the NAND flash memory (14) has passed its initial life comprises the steps of: determining whether the average erase count is greater than a pre-set threshold . The method of claim 1, wherein the step of determining whether the NAND flash memory (14) has passed its initial life comprises the following steps: processing with a flash memory conversion layer This write command. The method of claim 1, wherein the second portion of the NAND flash memory (14) is 1% of the NAND flash memory (14).