TWI642057B - Method for operating non-volatile memory device and applications thereof - Google Patents

Abstract

A method of operating a Non-Volatile Memory (NVM) component, comprising the steps of: first performing a first write operation, the first write operation comprising: at least for a non-volatile memory component A resistance switching memory cell applies a first write pulse having a first electrical property. A first verify pulse having a verify voltage is then applied to the at least one variable resistive memory cell. And applying a first set pulse to the at least one variable resistive memory cell before or after the first verify pulse. The first set pulse has a second electrical set voltage opposite to the first electrical property; and the absolute value of the set voltage is substantially less than or equal to the absolute value of the verify voltage.

Description

Method for operating non-volatile memory components and its application

The present disclosure relates to a method of operating a Non-Volatile Memory (NVM) component and an application device therefor. In particular, there is a method of operating a memory element including a variable resistance memory cell and an application device therefor.

A non-volatile memory component that has the property of not losing information stored in the memory unit when the power is removed. Currently widely used is a Charge Trap Flash (CTF) memory component that uses a charge trap. However, as the accumulation density of memory components increases, the critical size and pitch of the components shrink, and the charge storage type flash memory device faces its physical limit and cannot operate.

A variable-resistance memory device (for example, a variable-resistance random access memory device) uses a resistance of a variable-resistance memory cell as a information storage The basis for the interpretation of the state. It is superior to other flash memories in terms of device density, power consumption, stylization/erasing speed or three-dimensional space stacking characteristics. Therefore, it has become one of the memory components that have received much attention in the industry.

A programming operation of a typical variable resistance memory device, comprising applying a write pulse to a plurality of selected variable resistance memory cells in a variable resistance random access memory device to make a variable The resistance distribution of the resistive memory cell is changed from a first resistance distribution state (for example, a low resistance distribution state) to a second resistance distribution state (a high value resistance distribution state). A verification operation is performed to verify whether the resistance distribution of the written variable resistance memory cell is converted into the second resistance distribution state. In order for the verification operation to be effectively implemented, it is necessary to have a resistance window sufficient to distinguish the two kinds of resistance distribution states.

Therefore, there is a need to provide a method of operating a non-volatile memory component and an application thereof to solve the problems faced by the prior art.

One embodiment of the present specification is directed to a method of operating a non-volatile memory component. The method of operating the non-volatile memory component includes first performing a first write operation, the first write operation comprising: applying a first charge to the at least one variable resistive memory cell of the non-volatile memory component The first write pulse of sex. A first verify pulse having a verify voltage (V _ver ) is then applied to the at least one variable resistive memory cell. And applying a first set pulse to the at least one variable resistive memory cell before or after the first verify pulse. Wherein, the first set pulse has a second electrical opposite set voltage ( _Vset ) opposite to the first electrical property; and the absolute value of the set voltage is substantially less than or equal to the absolute value of the verify voltage (| _Vset | |V _ver |).

One embodiment of the present specification is directed to a non-volatile memory component. The non-volatile memory component includes: at least one variable resistance memory cell and a controller. The controller is electrically coupled to the at least one variable resistive memory for performing a first write operation on the at least one variable resistive memory cell. The first write operation includes the step of first applying a first write pulse having a first electrical property to the at least one variable resistive memory cell. A first verify pulse having a verify voltage (V _ver ) is then applied to the at least one variable resistive memory cell. And applying a first set pulse to the at least one variable resistive memory cell before or after the first verify pulse. Wherein, the first set pulse has a second electrical opposite set voltage ( _Vset ) opposite to the first electrical property; and the absolute value of the set voltage is substantially less than or equal to the absolute value of the verify voltage (| _Vset | |V _ver |).

A method of fabricating a non-volatile memory device, comprising: forming at least one variable resistance memory cell; and forming a variable resistance memory cell electrically connected controller for performing a variable resistance memory cell A write operation. The first write operation includes the step of first applying a first write pulse having a first electrical property to the at least one variable resistive memory cell. A first verify pulse having a verify voltage (V _ver ) is then applied to the at least one variable resistive memory cell. And applying a first set pulse to the at least one variable resistive memory cell before or after the first verify pulse. Wherein, the first set pulse has a second electrical opposite set voltage ( _Vset ) opposite to the first electrical property; and the absolute value of the set voltage is substantially less than or equal to the absolute value of the verify voltage (| _Vset | |V _ver |).

In accordance with the above, embodiments of the present specification provide a method of operating a non-volatile memory component and an application thereof, at least one of non-volatile memory components during a write operation of a non-volatile memory component. The variable resistive memory cell applies at least one write pulse and one verify pulse. At least one set pulse is applied to the variable resistive memory cell before or after the verify pulse. The set pulse has a set voltage opposite to the write pulse electrical polarity, and the set voltage absolute value is less than or equal to the verification value of the verify pulse. The variable resistance memory cell will have a resistance value greater than a preset resistance value after the write operation. After a period of time, the resistance distribution state does not return to the previous wider resistance distribution state, and the portion is smaller than the preset resistance value. Further, the problem that the variable resistance memory cell writing operation is unstable can be solved.

100‧‧‧Non-volatile memory components

101‧‧‧Variable Resistive Memory Cell

158‧‧ ‧ class decoder

159‧‧‧Sequence selection line

160‧‧‧ Stereo Memory Array

161‧‧ ‧ row decoder

162‧‧‧ word line

163‧‧‧ column decoder

164‧‧‧ bit line

165‧‧ ‧ busbar

166‧‧‧Sense Amplifier and Data Input Structure

167‧‧‧ data bus

168‧‧‧Voltage supply

169‧‧‧ bias configuration state machine

171‧‧‧ data input line

172‧‧‧ data output line

174‧‧‧Other circuits

408‧‧‧Complex pulse

200, 200', 300, 400, 404, 405, 406, 407, 500, 600, 604, 605, 606, 607‧‧‧ write operations

201, 301, 401, 501, 504, 505, 506, 507, 601‧‧‧ write pulses

202, 302, 402, 402', 502, 602‧‧‧ set pulse

203, 203', 303, 403, 403', 503, 603, 608‧‧‧ verification pulse

701, 702, 702', 801, 802, 802', 901, 902, 902', 902", 902'''‧‧‧ resistance value cumulative distribution curve

S21‧‧‧ provides non-volatile memory components

S22‧‧‧ Applying a write pulse to a variable resistance memory cell

S23‧‧‧ Applying a set pulse to a variable resistance memory cell

S24‧‧‧ Apply a verification pulse to the variable resistance memory cell to verify whether the resistance value of the variable resistance memory cell reaches a preset threshold

S31‧‧‧ provides non-volatile memory components

S32‧‧‧ Applying a write pulse to a variable resistance memory cell

S33‧‧‧ Apply a verification pulse to the variable resistance memory cell to verify whether the resistance value of the variable resistance memory cell reaches a preset threshold

S34‧‧‧ Applying a set pulse to a variable resistance memory cell

S41‧‧‧ provides non-volatile memory components

S42‧‧‧ Applying a write pulse to a variable resistance memory cell

S43‧‧‧ Applying a set pulse to a variable resistance memory cell

S44‧‧‧ Apply a verification pulse to the variable resistance memory cell to verify whether the resistance value of the variable resistance memory cell reaches a preset threshold

S45‧‧‧ Apply another write pulse to the variable resistance memory cell

S51‧‧‧ provides non-volatile memory components

S52‧‧‧ Applying a write pulse to a variable resistance memory cell

S53‧‧‧ Apply a verification pulse to the variable resistance memory cell to verify whether the resistance value of the variable resistance memory cell reaches a preset threshold

S54‧‧‧ Applying a set pulse to a variable resistance memory cell

S55‧‧‧ Apply another write pulse to the variable resistance memory cell

S61‧‧‧ provides non-volatile memory components

S62‧‧‧ Applying a write pulse to a variable resistance memory cell

S63‧‧‧ Apply a verification pulse to the variable resistance memory cell to verify whether the resistance value of the variable resistance memory cell is greater than a preset threshold

S64‧‧‧ Apply another write pulse to the variable resistance memory cell

S65‧‧‧ Applying a set pulse to a variable resistance memory cell

S60A‧‧‧Segment write operation

S60B‧‧‧Send write operation

V _pgm , V _pgm1 , V _pgm2 , V _pgm3 , V _pgm4 , V _pgm5 ‧‧‧ write voltage

V _ver , V _ver '‧‧‧ verification voltage

V _set ‧‧‧Set voltage

K‧‧‧ default threshold

The above-described embodiments and other objects, features and advantages of the present invention will become more apparent from the aspects of the invention. The embodiment shows a circuit block diagram of a non-volatile memory element; FIG. 2A is a flow chart of the operation method of the non-volatile memory element according to an embodiment of the present specification; FIG. 2B is a description according to the present specification. An embodiment of the present invention uses the method of FIG. 2A to perform a write operation of a non-volatile memory element; and FIG. 2C uses a second embodiment according to another embodiment of the present specification. Method for performing a write operation on a non-volatile memory element; FIG. 3A is a flow chart of a method for operating a non-volatile memory element according to an embodiment of the present specification; FIG. 3B The operation timing diagram of the writing operation of the non-volatile memory element by the method described in FIG. 3A is shown; FIG. 4A is a non-volatile memory element according to an embodiment of the present specification. Operation method flow chart; FIG. 4B is an operation timing diagram illustrated by a method of writing a non-volatile memory element by using the method of FIG. 4A according to an embodiment of the present specification; FIG. 4C is another operation according to the present specification. An embodiment shows an operation timing diagram for writing a non-volatile memory element by the method of FIG. 4A; FIG. 5A is a non-volatile memory element according to an embodiment of the present specification. FIG. 5B is an operation timing diagram showing a non-volatile memory element writing operation according to an embodiment of the present specification by using the method of FIG. 5A; FIG. 6A is a diagram according to the present specification. A flow chart of a method for operating a non-volatile memory element according to an embodiment of the present invention; FIG. 6B is a diagram showing a write operation of a non-volatile memory element by the method of FIG. 6A according to an embodiment of the present specification. Operation timing diagram; Figure 7A shows the non-volatile memory component performing the write operation shown in Figure 5B after a certain time interval, using the method described in Figure 5A, after a certain time interval, the variable resistor Cumulative Distribution Function (CDF) diagram of the memory cell; Figure 7B shows the method of writing a non-volatile memory component by a method provided in a comparative example and after a specific time interval After that, the resistance distribution cumulative distribution of the variable resistance memory cell; FIG. 8A shows the writing operation of the non-volatile memory component in FIG. 6B by using the method described in FIG. 6A and The cumulative distribution function diagram of the resistance value of the variable resistance memory cell after a certain time interval; FIG. 8B shows the writing operation of the non-volatile memory component by a method provided by a comparative example After a specific time interval, the resistance distribution cumulative distribution of the variable resistance memory cells; the 9A to 9D diagrams are based on the methods described in Figures 5A and 5B, respectively, at -0.3V, -0.5V, a set voltage _Vset of -0.7V and -1.0V, a write operation of the non-volatile memory element 100, a cumulative distribution of resistance values of the variable resistance memory cell after a certain time interval; and a tenth figure according to A cross-sectional view of a variable resistance memory cell structure of a Resistive Random Access Memory (ReRAM) cell according to an embodiment of the present specification.

The present specification discloses a method for operating a non-volatile memory element and an application device thereof, which can solve the problem that the writing operation of the prior art is unstable. The above-described embodiments, as well as other objects, features and advantages of the present invention will become more apparent and understood. However, it must be noted that these specific embodiments and methods are not intended to limit the invention. Other embodiments of the invention may be practiced with other features, elements, methods, and parameters. The preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the invention. Equivalent modifications and variations will be made without departing from the spirit and scope of the invention. In the different embodiments and the drawings, the same elements will be denoted by the same reference numerals.

Please refer to FIG. 1 . FIG. 1 is a circuit block diagram of a non-volatile memory device 100 according to an embodiment of the present specification. In some embodiments of the present specification, the non-volatile memory component 100 can be a memory component having a plurality of variable resistive memory cells 101. For example, the non-volatile memory element 100 may be a resistive random access memory including a stereo memory array 160 composed of a plurality of variable resistance memory cells 101 on an integrated circuit substrate. , ReRAM) unit. Each of the variable resistance memory cells 101 (as shown in FIG. 10) may include a resistance conversion layer 101a between the first electrode 101b and the second electrode 101c. Among them, resistance conversion Layer 101a includes a high-k dielectric material, a binary metal oxide, or a transition metal oxide. The first electrode 101b and the second electrode 101c may include a conductive material such as germanium (Si), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), copper (Cu), or the like. Suitable materials.

In the present embodiment, the non-volatile memory component 100 includes a row decoder 161 coupled to a plurality of word lines 162 and configured along the row lines in the memory array 160. A column decoder 163 is coupled to a plurality of bit lines 164 disposed along the column lines in the memory array 160 for reading and writing from the variable resistive memory cells in the memory array 160. data. The address is provided by the bus 165 to the column decoder 163, the row decoder 161, and the level decoder 158. Sensing amplifiers and data-in structures 166 are coupled via data bus 167 and column decoder 163. The input/output port of the non-volatile memory element 100, or the data input by other sources inside or outside the non-volatile memory element 100, is supplied to the sensing through a data-in 171. The amplifier and data entry structure 166. In addition, the non-volatile memory component 100 also includes other circuits 174, such as a general purpose processor or a special purpose application circuit, or a system-on-a system. -chip) An integrated module that is functionally supported by a programmable resistance cell array. The data from the sense amplifier and data input structure 166 is transmitted through a data-out line 172. The input/output ports to the non-volatile memory element 100, or other data destination addresses to the inside or outside of the non-volatile memory element 100.

The non-volatile memory component 100 also includes a controller electrically coupled to the variable resistive memory cell 101 in the memory array 160. In the present embodiment, the controller is a bia arrangement state machine 169 to control the bias configuration of the voltage supply 168 to generate or provide a read or write voltage for the variable resistance memory. Cell 101 performs a read or write operation. In some embodiments of the present specification, the controller may be implemented using special purpose logic circuitry. In another embodiment, the controller includes a general purpose processor for executing a computer program to control the operation of an element (e.g., variable resistive memory cell 101) in the same integrated circuit. In yet another embodiment, the controller can be implemented using a combination of special purpose logic circuitry and general purpose processors.

In some embodiments of the book, non-volatile memory component 100 is a resistive random access memory cell that utilizes a plurality of different operations for data storage. In the "forming" operation, a "forming" voltage is applied to the first electrode 101b and the second electrode 101c of the variable resistive memory cell 101 to provide a sufficiently high "forming" voltage to the resistive switching layer. A conductive portion is produced in 101a. In one embodiment, the conductive portion includes one or more conductive strips to provide a conductive path, thereby causing the resistive switching layer 101a to exhibit an "on" or low resistance state. The conductive path may be related to the arrangement of defects (e.g., oxygen) vacancies in the resistance conversion layer 101a. In some embodiments, only a "formation" voltage can be applied to the variable resistive memory cell 101. Once the conductive path is formed, it will remain There is a resistance conversion layer 101a.

After the "formation" operation, a "program operations" operation can be performed to disconnect or reconnect the conductive paths by a small or different voltage. The "write" operation can include a "set" operation or a "reset" operation.

In the "setting" operation, the variable resistance memory cell 101 is applied with a sufficiently high "set" voltage to reconnect the conductive paths in the resistance conversion layer 101a, thereby causing the resistance conversion layer 101a to exhibit "on" or low. Resistance state.

In the "reset" operation, the variable resistance memory cell 101 is applied with a sufficiently high "reset" voltage to disconnect the conductive path in the resistance conversion layer 101a, thereby causing the resistance conversion layer 101a to "close". Or high resistance state. The magnitude of the resistance value of the resistance conversion layer 101a can be changed by applying different voltages to the first electrode 101b and the second electrode 101c. Among them, the high resistance value and the low resistance value can represent the digital signals of "1" and "0", respectively, for storing data.

Please refer to FIG. 2A and FIG. 2B . FIG. 2A is a flow chart of a method for operating the non-volatile memory element 100 according to an embodiment of the present specification. 2B is an operational timing diagram of the write operation 200 of the non-volatile memory element 100 in accordance with another embodiment of the present specification using the method of FIG. 2A. In some embodiments of the present specification, the write operation 200 of the non-volatile memory element 100 includes the following steps: first, the non-volatile memory element 100 as shown in FIG. 1 is provided (as depicted in step S21). Show).

Next, a write pulse 201 having a first electrical property is applied to at least one of the variable resistive memory cells 101 of the non-volatile memory device 100 (as shown in step S22). For example, in the present embodiment, the write pulse 201 may have a substantial positive write voltage of 1.6V V _pgm; and having a pulse width between the real value is between 500 nanoseconds (nanosecond, ns) to 3000 nanoseconds .

Then, a set pulse 202 is applied to the variable resistive memory cell 101 (as shown in step S23). Wherein, the set pulse 202 has a second electrical property opposite to the first electrical property. For example, in some embodiments of the present specification, the set pulse 202 may have a set voltage _Vset having a value substantially between -0.3V and -1.0V; having a real value between 1 microsecond (μs) to 3 The pulse width between microseconds. The absolute value of the set voltage Vset absolute value of the set pulse 202 is smaller than the absolute value of the write voltage V _{pgm of the} write pulse 201 (|V _set |<|V _pgm |). In the present embodiment, the set pulse 202 may have a set voltage _{Vset of} substantially -0.5 V, and the pulse width is preferably about 1 microsecond.

Subsequently, a verification pulse 203 having a verification voltage V _ver is applied to the variable resistance memory cell 101 (as shown in step S24) to verify whether the resistance value of the variable resistance memory cell 101 reaches a preset threshold value ( Prediction criteria). In some embodiments of the present specification, the verification voltage V _ver absolute value of the verification pulse 203 is substantially greater than or equal to the set voltage V _set absolute value of the set pulse 202 (|V _set | |V _ver |); and the pulse width of the verify pulse 203 is much smaller than the pulse width of the set pulse 202. For example, in the present embodiment, the verify pulse 203 may have a positive verify voltage V _ver . Wherein the verification voltage V _{ver is} substantially 0.5 V, and the true value of the pulse width of the verification voltage V _ver is between 50 nanoseconds (ns) and 100 nanoseconds, and in one embodiment, preferably 80 nanoseconds.

In the verification process, when the resistance value of the variable resistance memory cell 101 reaches the preset threshold (Yes), the write operation 200 is ended. When the resistance value of the variable resistance memory cell 101 fails to be greater than the preset threshold value (NO), the process returns to step S22; and steps S22, S23, and S24 are repeated once more. That is, the write pulse 201 (step S22), the set pulse 202 (step S23), and the verify pulse 203 (step S24) are applied to the variable resistive memory cell 101 until the resistance value of the variable resistive memory cell 101. Reach the preset threshold. In the present embodiment, after the write operation 200 applies the first verification pulse 203 to the variable resistance memory cell 101, the resistance value of the variable resistance memory cell 101 has reached the preset threshold value, and ends. Write operation 200. Therefore, the write operation 200 applies only one write pulse 201, one set pulse 202, and one verify pulse 203 to the variable resistive memory cell 101 in total.

After the write operation 200, the resistance value of the variable resistance memory cell 101 is greater than the preset resistance value, and after a period of time, the resistance distribution state of the variable resistance memory cell 101 does not return to the previous wider The resistance distribution state causes the resistance value of the partial variable resistance memory cell 101 to be smaller than the preset resistance value. In turn, the problem of unstable write operation can be solved.

It should be noted that in other embodiments of the present specification, the verify pulse 203 may have an electrical opposite to the write pulse 201. For example, please refer to FIG. 2C, which is an operational timing diagram of a non-volatile memory element write operation 200' according to another embodiment of the present specification using the method of FIG. 2A. The operation timing diagram shown in FIG. 2C is substantially similar to that shown in FIG. 2B , except that the verification pulse 203 ′ used in the write operation 200 ′ of FIG. 2C has electrical properties with the write pulse 201 . The opposite negative voltage. In the present embodiment, the verification voltage V _ver ' of the verification pulse 203' is substantially -0.5V. Although both the verify pulse 203' and the set pulse 202 have the opposite polarity to the write pulse 201, the absolute values of the voltages of both are smaller than the absolute value of the write voltage _{Vpgm of the} write pulse 201. However, since the pulse width of the verify pulse 203' is much smaller than the pulse width of the set pulse 202. Therefore, the verify pulse 203' and the set pulse 202 can still be distinguished by the pulse width and the voltage magnitude.

Please refer to FIG. 3A and FIG. 3B . FIG. 3A is a flow chart of a method for operating the non-volatile memory element 100 according to an embodiment of the present specification. FIG. 3B is a timing chart showing the operation of the write operation 300 to the non-volatile memory device 100 by the method described in FIG. 3A. In some embodiments of the present specification, the write operation 300 of the non-volatile memory element 100 includes the following steps: first providing the non-volatile memory element 100 as depicted in FIG. 1 (as depicted in step S31) Show).

Next, a write pulse 301 having a first electrical property is applied to at least one of the variable resistive memory cells 101 of the non-volatile memory device 100 (as shown in step S32). For example, in the present embodiment, the write pulse 301 may have a forward write voltage _{Vpgm of} substantially 16V; and a pulse width with a real value between 500 nanoseconds and 3000 nanoseconds.

Then, a verification pulse 303 having a verification voltage V _ver is applied to the variable resistance memory cell 101 (as shown in step S33) to verify whether the resistance value of the variable resistance memory cell 101 reaches a predetermined threshold value. In the present embodiment, the verify pulse 303 may have a forward verify voltage V _ver (eg, 0.5 V) that is substantially less than the write voltage V _pgm of the write pulse 301; and has a real value between 50 nanoseconds and 100 nanoseconds. The pulse width between. In one embodiment, the pulse width of the verify pulse 303 is preferably 80 nanoseconds.

In the verification process, when the resistance value of the variable resistive memory cell 101 reaches the preset threshold (Yes), the process proceeds to step S34, the set pulse 302 is applied to the variable resistive memory cell 101, and then the write operation 300 is ended. . Conversely, when the resistance value of the variable resistive memory cell 101 fails to reach the preset threshold (NO), the process returns to step S33, and the write pulse 301 is applied to the variable resistive memory cell 101 again (step S32). The pulse 303 is verified (step S33). Steps S32 and S33 are repeatedly performed until the resistance value of the variable resistive memory cell 101 reaches a preset threshold value. Thereafter, the set pulse 302 is applied to the variable resistive memory cell 101, and the write operation 300 is terminated. The set pulse 302 has a negative set voltage _{Vset that is} electrically opposite to the write pulse 301; the set voltage _Vset absolute value of the set pulse 302 is substantially less than or equal to the verify voltage absolute value of the verify pulse 303 (| _Vset | |V _ver |); and the pulse width of the verify pulse 303 is much smaller than the pulse width of the set pulse 302.

In the present embodiment, after the write operation 300 applies the first verification pulse 303 to the variable resistive memory cell 101, steps S32 and S33 are repeatedly performed. Therefore, the write operation 300 applies the secondary write pulse 301, the secondary set pulse 302, and the primary set pulse 302 to the variable resistive memory cell 101 in total. After the write operation 300, the resistance value of the variable resistance memory cell 101 is greater than The resistance value is preset, and after a period of time, the resistance distribution state of the variable resistance memory cell 101 does not return to the previous wider resistance distribution state, and the resistance value of the partial variable resistance memory cell 101 is smaller than this. The preset resistance value. In turn, the problem of unstable write operation can be solved.

Please refer to FIG. 4A and FIG. 4B . FIG. 4A is a flow chart of a method for operating the non-volatile memory element 100 according to an embodiment of the present specification. 4B is an operational timing diagram of the write operation 400 of the non-volatile memory device 100 in accordance with another embodiment of the present specification using the method of FIG. 4A. In some embodiments of the present specification, the write operation 400 of the non-volatile memory element 100 includes the following steps: first providing the non-volatile memory element 100 as depicted in FIG. 1 (as depicted in step S41) Show).

Next, a write pulse 401 having a first electrical property is applied to at least one of the variable resistive memory cells 101 of the non-volatile memory device 100 (as shown in step S42). For example, in the present embodiment, the write pulse 401 may have a forward write voltage V _{pgm1 of} substantially 16V; the pulse width of the write pulse 401 may be between 500 nanoseconds and 3000 nanoseconds.

Then, a set pulse 402 is applied to the variable resistive memory cell 101 (as shown in step S43). For example, in some embodiments of the present specification, the set pulse 402 can have a negative set voltage _Vset having a value substantially between -0.3V and -1.0V, and a real value between 1 microsecond and 3 microseconds. The pulse width between. Further, the _set value V _set absolute value of the set pulse 402 is smaller than the absolute value of the write voltage V _{pgm1 of the} write pulse 401 (|V _set |<|V _pgm1 |). In the present embodiment, the set pulse 402 can have a negative set voltage _{Vset of} substantially 0.5V, and preferably a pulse width of about 1 microsecond.

Subsequently, a verification pulse 403 having a verification voltage V _ver is applied to the variable resistance memory cell 101 (as shown in step S44) to verify whether the resistance value of the variable resistance memory cell 101 reaches a predetermined threshold value. When the resistance value of the variable resistive memory cell 101 reaches the preset threshold (Yes), the write operation 400 is ended. In the embodiment of the present specification, the absolute value of the verification voltage V _ver of the verification pulse 403 is substantially greater than the absolute value of the set voltage V _set of the set pulse 402 (|V _ver |>|V _set |); and the pulse of the verification pulse 403 The width is much smaller than the pulse width of the set pulse 402. For example, in the present embodiment, the verify pulse 403 has a positive verify voltage V _{ver of} substantially 0.5 V and a pulse width of between 50 nanoseconds and 100 nanoseconds.

In the verification process of step S44, if the resistance value of the variable resistive memory cell 101 has not reached the preset threshold (NO), the process proceeds to step S45. Another write pulse (e.g., write pulse 404) having a first electrical property is applied to the variable resistive memory cell 101. In the present embodiment, the write voltage V _{pgm2 of the} write pulse 404 may be substantially greater than the write voltage V _{pgm1 of the} write pulse 401. Thereafter, step S43 and step S44 are performed again to apply the set pulse 402 and the verify pulse 403 to the variable resistive memory cell 101. Steps S45, S43, and S44 are repeated until the resistance value of the variable resistive memory cell 101 reaches the preset threshold (Yes), and the write operation 400 is ended.

In the present embodiment, after the write operation 400 applies the first verification pulse 403 to the variable resistive memory cell 101, the step S45, the step S43, and the step S44 are repeated four times. Therefore, the write operation 400 applies a total of four write pulses 404, 405, 406, and 407, five set pulses 402, and five verify pulses 403 (as shown in FIG. 4B) to the variable resistive memory cell 101. The write voltages V _pgm2 , V _pgm3 , V _{pgm4 ,} and V _pgm5 of the write pulses 404, 405, 406, and 407 provided in step S45 are substantially larger than the write voltage V _{pgm1 of the} write pulse 401. The write voltage values V _pgm1 , V _pgm2 , V _pgm3 , V _{pgm4 ,} and V _pgm5 are sequentially increased.

It should be noted that when the verify pulse 403' can have the same electrical properties as the set pulse 402' (ie, both have negative electrical properties), the verify pulse 403' and the set pulse 402' can be combined to form a composite pulse 408. For example, please refer to FIG. 4C. FIG. 4C is an operation timing diagram of the non-volatile memory element writing operation 400' according to another embodiment of the present specification by the method of FIG. 4A. The operation timing diagram of the write operation 400' illustrated in FIG. 4C is substantially similar to the operation timing diagram of the write operation 400 illustrated in FIG. 4B, and the difference lies only in the verification used by the write operation 400'. The pulse 403' has a negative verify voltage _Vver ' that is substantially opposite to the write pulse 401, and the negative verify voltage _Vver ' is substantially lower than the negative set voltage _{Vset of the} set pulse 402'. In addition, there is no time interval between the verification pulse 403' and the set pulse 402', and a zigzag continuous composite pulse 408 as shown in FIG. 4C can be combined.

Please refer to FIG. 5A and FIG. 5B . FIG. 5A is a flow chart of a method for operating the non-volatile memory element 100 according to an embodiment of the present specification. FIG. 5B is a timing diagram of a write operation illustrated by the write operation 500 of the non-volatile memory device 100 by the method of FIG. 5A according to an embodiment of the present specification. Figure. In some embodiments of the present specification, the write operation 500 of the non-volatile memory element 100 includes the following steps: first providing the non-volatile memory element 100 as depicted in FIG. 1 (as depicted in step S51) Show).

Next, a write pulse 501 having a first electrical property is applied to at least one of the variable resistive memory cells 101 of the non-volatile memory device 100 (as shown in step S52). For example, in the present embodiment, the write pulse 501 may have a forward write voltage V _{pgm1 of} substantially 16V; the pulse width of the write pulse 501 may be between 500 nanoseconds and 3000 nanoseconds.

Thereafter, a verification pulse 503 having a verification voltage V _ver is applied to the variable resistance memory cell 101 (as shown in step S53) to verify whether the resistance value of the variable resistance memory cell 101 reaches a predetermined threshold value. In the present embodiment, the verify pulse 503 may have a forward verify voltage V _ver (eg, 0.5 V) that is substantially less than the write pulse 501; and has a pulse width with a real value between 50 nanoseconds and 100 nanoseconds.

In the verification process of step S53, when the resistance value of the variable resistive memory cell 101 reaches the preset threshold (Yes), the write operation 500 proceeds to step S54: the set pulse 502 is applied to the variable resistive memory cell 101, after which That is, the write operation 500 is ended. In the present embodiment, the set pulse 502 can have a negative set voltage _{Vset of} substantially -0.5V with a pulse width of about 1 microsecond.

Conversely, when the resistance value of the variable resistive memory cell 101 has not reached the preset threshold (NO), the write operation 500 proceeds to step S55: applying the first electrical property to the variable resistive memory cell 101. Another write pulse (eg, write pulse 504). In some embodiments of the present specification, the write voltage _{Vpgm2 of the} write pulse 504 may be substantially greater than the write voltage _{Vpgm1 of the} write pulse 501. Thereafter, the verification pulse 503 is applied once to the variable resistance memory cell 101 (step S53). Steps S55 and S53 are repeatedly performed until the resistance value of the variable resistive memory cell 101 reaches a preset threshold value. When the resistance value of the variable resistive memory cell 101 reaches the preset threshold value, the set pulse 502 is applied to the variable resistive memory cell 101 (step S54), that is, the write operation 500 is ended.

In the present embodiment, after the write operation 500 applies the first verification pulse 503 to the variable-resistance memory cell 101, the steps S55, S53, and S54 are repeated four times. Therefore, the write operation 500 applies a total of five write pulses 501, 504, 505, 506, and 507 five times of the verify pulse 503 and one set pulse 502 (as shown in FIG. 5B) to the variable resistive memory cell 101. The write voltages V _pgm2 , V _pgm3 , V _{pgm4 ,} and V _{pgm5 of the} write pulses ₅₀₄ , ₅₀₅ , ₅₀₆ , and 507 provided in step S55 are substantially larger than the write voltage V _{pgm1 of the} write pulse 501. The write voltage values V _pgm1 , V _pgm2 , V _pgm3 , V _{pgm4 ,} and V _pgm5 are sequentially increased.

Please refer to FIG. 6A and FIG. 6B . FIG. 6A is a flow chart of a method for operating the non-volatile memory element 100 according to an embodiment of the present specification. 6B is an operational timing diagram of the write operation 600 of the non-volatile memory element 100 in accordance with another embodiment of the present specification using the method of FIG. 6A. In some embodiments of the present specification, the write operation 600 of the non-volatile memory element 100 includes the steps of first providing the non-volatile memory element 100 as depicted in FIG. 1 (as depicted in step S61). Show). Next, for non-volatile memory At least one variable resistance memory cell 101 of the body element 100 performs a front-end write operation S60A. Thereafter, a set pulse 602 is applied to the variable resistance memory cell 101 (as shown in step S65). Subsequently, a subsequent write operation S60B is performed.

The preceding write operation S60A includes the step of first applying a write pulse 601 having a first electrical property to the variable resistive memory cell 101 (as shown in step S62). Thereafter, a verification pulse 603 having a verification voltage V _ver is applied to the variable resistance memory cell 101 (as shown in step S63) to verify whether the resistance value of the variable resistance memory cell 101 reaches a predetermined threshold value.

In the present embodiment, the write pulse 601 may have a forward write voltage V _{pgm1 of} substantially 16V; the pulse width of the write pulse 601 may be between 500 nanoseconds and 3000 nanoseconds. The verify pulse 603 can have a positive verify voltage V _ver (eg, 0.5 V) that is substantially less than the write pulse 601; and has a pulse width with a real value between 50 nanoseconds and 100 nanoseconds.

If it is verified in step S63 that the resistance value of the variable resistive memory cell 101 has not reached the preset threshold (NO), the process proceeds to step S64. Another write pulse (e.g., write pulse 604) having a first electrical property is applied to the variable resistive memory cell 101. The write voltage _{Vpgm2 of the} write pulse 604 can be substantially greater than the write voltage _{Vpgm1 of the} write pulse 401. Thereafter, step S63 is performed again to apply a verification pulse 603 to the variable resistance memory cell 101. Steps S64 and S63 are repeated until the resistance value of the variable resistive memory cell 101 reaches the preset threshold value (Yes), and the previous stage write operation S60A is completed.

In the present embodiment, the previous stage write operation S60A repeats the second steps S64 and S63. Therefore, the preceding write operation S60A applies a total of three write pulses 601, 604, and 605 and three verify pulses 603 (as shown in FIG. 6B) to the variable resistive memory cell 101. The write voltages V _pgm2 and V _pgm3 of the write pulses 604 and 605 provided in step S64 are substantially larger than the write voltage V _{pgm1 of the} write pulse 601 and are successively increased.

Then, the process proceeds to step S65, and a set pulse 602 is applied to the variable resistive memory cell 101 to apply a set pulse 602 to the variable resistive memory cell 101. Wherein, the set pulse 602 has a second electrical property opposite to the first electrical property. The _set value V _set absolute value of the set pulse 602 is less than or equal to the absolute value of the verification voltage V _{ver of the} verification pulse 603 (|V _set | |V _ver |). Moreover, the pulse width of the set pulse 602 is much larger than the pulse width of the verify pulse 603. In the present embodiment, the set pulse 602 has a negative set voltage _Vset having a value of substantially -0.5 V and a pulse width of about 1 microsecond.

Subsequently, the subsequent stage write operation S60B is performed, and then the write operation 600 is ended. In the present embodiment, the subsequent write operation S60B includes applying the secondary write pulses 606 and 607 and the secondary verify pulse 608 to the variable resistive memory cell 101 (as shown in FIG. 6B). The write voltages of the write pulses 606 and 607 are substantially the same as the write voltages V _pgm2 and V _{pgm3 of the} write pulses 601 and 604; and the verify voltage of the verify pulse 608 is substantially the same as the verify voltage V _{ver of the} verify pulse 603. Since the implementation of the subsequent write operation S60B is substantially the same as the previous write operation S60A. Therefore, it is not described here.

Please refer to FIG. 7A and FIG. 7B. FIG. 7A illustrates the non-volatile memory device 100 as shown in FIG. 5B by using the method described in FIG. 5A. The resistance value of the variable resistive memory cell 101 is cumulatively distributed as a function of the write operation 500 and after a certain time interval. FIG. 7B is a diagram showing a cumulative distribution of resistance values of the variable resistance memory cell 101 after a non-volatile memory element 100 is written by a method provided by a comparative example and after a certain time interval. The write operation procedure used in the write operation 500 and the comparative example used in this embodiment is substantially the same as the operation parameter, except that the write operation method used in the comparative example omits step S54, and is not correct. The variable resistance memory cell 101 applies a set pulse 502.

As can be seen from the results of FIGS. 7A and 7B, after the write operation in the present embodiment and the comparative example, the resistance value distribution state of the variable resistance memory cell 101 can be respectively distributed from the first resistance value state (with resistance). The value cumulative distribution function curve 701 represents an offset to the second resistance value distribution state (represented by the resistance value cumulative distribution curve 702 and 702', respectively), and the resistance value of the variable resistance memory cell 101 exceeds a preset threshold value. K (for example, 87K-ohm). After a certain period of time (for example, after a time interval of about 1 second), the resistance of most of the variable resistive memory cells 101 remains maintained above the preset threshold K. However, the resistance value of a small portion of the variable resistance memory cell 101 is again restored to a state previously smaller than the preset threshold K.

In this embodiment, after the writing operation 500 is performed by the method described in FIGS. 5A and 5B, the resistance value of the variable resistance memory cell 101 is lower than the preset threshold K after a certain time interval. , substantially less than 1% (for example, about 0.6%) (as shown in FIG. 7A); and the write operation 500' is performed by the method of the comparative example, after a certain time interval, the variable resistance memory The probability that the resistance value of the cell 101 is lower than the preset threshold K is about 2% (as shown in FIG. 7B). The operation of the non-volatile memory device 100 by the methods described in FIGS. 5A and 5B is shown to effectively eliminate the instability of the write operation and greatly improve the performance of the non-volatile memory device 100.

Please refer to FIG. 8A and FIG. 8B. FIG. 8A illustrates the writing operation 600 of the non-volatile memory device 100 as shown in FIG. 6B by using the method described in FIG. 6A, after a certain period of time. After the interval, the resistance value cumulative resistance distribution graph of the variable resistance memory cell 101. FIG. 8B is a diagram showing the cumulative distribution of resistance values of the variable resistance memory cell 101 after a certain time interval has been performed by performing a write operation on the non-volatile memory device 100 by the method provided in a comparative example. The write operation procedure and the operation parameters used in the write operation 600 and the comparative example used in this embodiment are substantially the same as the operation parameters, except that the write operation method used in the comparative example omits the step S65, and the variable resistor is not applied. The memory cell 101 applies a set pulse 602.

As can be seen from the results of FIGS. 8A and 8B, in the present embodiment and the comparative example, after the writing operation, the resistance value distribution state of the variable resistance memory cell 101 can be respectively distributed by the first resistance value state (with resistance). The value cumulative distribution function curve 801 represents an offset to the second resistance value distribution state (represented by the resistance value cumulative distribution curve 802 and 802', respectively), and the resistance value of the variable resistance memory cell 101 exceeds a preset threshold value. K (for example, 87K-ohm). After a certain period of time (for example, after a time interval of about 1 second), the resistance value of most of the variable resistive memory cells 101 remains maintained above the preset threshold K. But a small part of the variable resistor The resistance value of the memory cell 101 is again restored to a state that was previously less than the preset threshold K.

In the present embodiment, the writing operation 600 is performed by the method described in FIGS. 6A and 6B, and after a certain time interval, the resistance value of all the variable resistance memory cells 101 is still lower than the preset threshold. The value K (as shown in FIG. 8A); and the writing operation of the comparative example method, after a certain time interval, the resistance value of the variable resistance memory cell 101 is lower than the preset threshold K It is about 2% (as shown in Figure 8B). The operation of the non-volatile memory device 100 by the methods described in FIGS. 6A and 6B is shown to effectively eliminate the instability of the writing operation and greatly improve the performance of the non-volatile memory device 100.

It is also worth noting that in the foregoing embodiment of the present specification, setting the set voltage _{Vset of the} pulse is one of the important factors for eliminating the instability of the write operation. For example, please refer to Figures 9A to 9D. Figures 9A to 9D are based on the methods described in Figures 5A and 5B, with -0.3V, -0.5V, -0.7V, and -1.0V, respectively. The set voltage _{Vset is} subjected to a write operation 500 to the non-volatile memory element 100, and after a certain period of time, the resistance value of the variable resistive memory cell 101 is cumulatively distributed.

It can be observed from Fig. 9A to Fig. 9D that after the writing operation 500 is performed on the nonvolatile memory element 100 with the set voltage _Vset of -0.3V, -0.5V, -0.7V, and -1.0V, it is variable. The resistance value distribution state of the resistive memory cell 101 can be shifted from the first resistance value distribution state (represented by the resistance value cumulative distribution function curve 901) to the second resistance value distribution state (the resistance value cumulative distribution function curve 902, respectively). , 902 ', 902" and 902 ′′′), and the resistance value of the variable resistance memory cell 101 exceeds a preset threshold K (for example, 87 K-ohm). After a certain time interval, the variable resistor The probability that the resistance value of the memory cell 101 is lower than the preset threshold K is 0.7%, 0, 1%, and 2%, respectively. The display voltage _{Vset of -0.5V is} used to perform the non-volatile memory element 100. The operation 500 is written to eliminate the effect of the unstable operation of the write operation (as shown in FIG. 9B), and the write operation 500 is performed on the non-volatile memory device 100 by using the set voltage _{Vset of} -0.3 V. To eliminate the effects of unstable write operations (as shown in Figure 9A), better than -0.7V and -1.0V Set voltage V _set to the non-volatile memory device 100 to perform a write operation 500 writes the effect of eliminating the instability (e.g., FIGS. 9C and 9D of FIG depicted).

In accordance with the above, embodiments of the present specification provide a method of operating a non-volatile memory component and an application thereof, at least one of non-volatile memory components during a write operation of a non-volatile memory component. The variable resistive memory cell applies at least one write pulse and one verify pulse. At least one set pulse is applied to the variable resistive memory cell before or after the verify pulse. The set pulse has a set voltage opposite to the write pulse electrical polarity, and the set voltage absolute value is less than or equal to the verification value of the verify pulse. The variable resistance memory cell will have a resistance value greater than a predetermined resistance value after the write operation. After a period of time, the resistance distribution state does not return to the previous wider resistance distribution state, and the portion is smaller than the preset resistance value. Further, the problem that the variable resistance memory cell writing operation is unstable can be solved.

Although the present specification has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (17)

A method of operating a Non-Volatile Memory (NVM) component, comprising: performing a first write operation, comprising: at least one variable resistive memory cell of the non-volatile memory component (resistance switching) a first write pulse having a first electrical property; applying a first verify pulse having a verify voltage (V _ver ) to the variable resistive memory cell; before the first verify pulse or And applying a first set pulse to the variable resistance memory cell, the first set pulse comprising a set voltage ( _Vset ) having a second electrical property opposite to the first electrical property and substantially less than the verifying voltage An absolute value (|V _set | |V _ver |); applying a second write pulse having the first electrical property to the variable resistive memory cell; and applying a second verify pulse to the variable resistive memory cell. The method of operating a non-volatile memory element according to claim 1, wherein the verification voltage has the first electrical property or the second electrical property. The method of operating a non-volatile memory device according to claim 1, wherein the first set pulse is applied to the variable resistive memory cell after the second verify pulse. The method of operating a non-volatile memory element according to claim 3, wherein the variable resistive memory cell has a predetermined greater than a predetermined threshold after applying the second verifying pulse. a resistance value; and after applying the first set pulse, after a time interval, the resistance value is not less than the preset value. The method of operating a non-volatile memory device according to claim 1, wherein the first set pulse is applied after the first write pulse, before the first verify pulse; and the second set pulse After the second write pulse is applied, before the second verify pulse. The method for operating a non-volatile memory element according to claim 5, wherein the first verification pulse has the second electrical property; and the first verification pulse and the first set pulse are combined to form A zigzag continuous composite pulse. The operation of non-volatile memory components as described in claim 1 The method, wherein the first set pulse is after the first write pulse and the first verify pulse; and the second set pulse is after the second write pulse and the second verify pulse. The method of operating a non-volatile memory element according to claim 1, wherein the first set pulse is applied after the second write pulse. The method for operating a non-volatile memory device according to claim 8 , further comprising: after the first set pulse, performing a second write operation, the second write operation comprising: The variable resistance memory cell applies a third write pulse having the first electrical property; and a third verify pulse having the verification voltage (V _ver ) is applied to the variable resistive memory cell. The method of operating a non-volatile memory element according to claim 1, wherein the first set pulse has a pulse width greater than a pulse width of the first verify pulse. Non-volatile memory components as described in claim 10 The operating method, wherein the pulse width of the first set pulse is 1 microsecond (μs); the first verify pulse has a pulse between 50 nanoseconds (ns) and 100 nanoseconds width. A non-volatile memory component comprising: at least one variable resistance memory cell; and a controller electrically coupled to the variable resistance memory for performing a first a write operation, the first write operation includes: applying a first write pulse having a first electrical property to the variable resistive memory cell; applying a verify voltage to the variable resistive memory cell (V) _Ver) a first verify pulse; the first verify pulse before or after a first application of a set pulse to the variable resistance memory cell, the first set pulse comprises a set voltage (V _set), and having a second electrical property of the first electrical opposite and substantially less than an absolute value of the verifying voltage (| _Vset | |V _ver |); applying a second write pulse having the first electrical property to the variable resistive memory cell; and applying a second verify pulse to the variable resistive memory cell. The non-volatile memory component of claim 12, wherein the verification voltage has the first electrical property or the second electrical property. The non-volatile memory component of claim 12, wherein the first set pulse has a real value greater than a pulse width of the first verify pulse. A method of fabricating a non-volatile memory device, comprising: forming at least one variable resistance memory cell; and forming a controller electrically coupled to the variable resistance memory for use in the variable resistance memory Performing a first write operation, the first write operation includes: applying a first write pulse having a first electrical property to the variable resistive memory cell; and applying the variable resistive memory cell to a first verification pulse of the verification voltage (V _ver ); applying a first set pulse to the variable resistance memory cell before or after the first verification pulse, the first set pulse comprising a set voltage (V _Set ), having a second electrical property opposite to the first electrical property and substantially less than an absolute value of the verification voltage (|V _set | |V _ver |); applying a second write pulse having the first electrical property to the variable resistive memory cell; and applying a second verify pulse to the variable resistive memory cell. The method of fabricating the non-volatile memory device of claim 15, wherein the verification voltage has the first electrical property or the second electrical property. The method of fabricating the non-volatile memory device of claim 15, wherein the first set pulse has a real value greater than a pulse width of the first verify pulse.