TWI641227B - Duty cycle adjustment device - Google Patents

Duty cycle adjustment device Download PDF

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TWI641227B
TWI641227B TW106106760A TW106106760A TWI641227B TW I641227 B TWI641227 B TW I641227B TW 106106760 A TW106106760 A TW 106106760A TW 106106760 A TW106106760 A TW 106106760A TW I641227 B TWI641227 B TW I641227B
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current
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input signal
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TW201834396A (en
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郭建良
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北京集創北方科技股份有限公司
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Abstract

一種占空比調整裝置包含一比較器及一反相器。該比較器包括一產生一輸入電流的電流源;一占空比調整電路,根據該輸入電流及一正相輸入信號與一反相輸入信號,產生一第一電流及一第二電流;及一電流鏡,具有一接收該第一電流的輸入端、及一電連接該占空比調整電路之一第二輸出端的輸出端,該電流鏡產生一對應該第一電流且流入其本身之該輸出端的一映射電流,該比較器在該輸出端與該第二輸出端間的一共同接點輸出一比較信號。該反相器具有一接收該比較信號的輸入端、及一輸出端,該反相器根據該比較信號,在其輸出端,輸出一輸出信號。 A duty ratio adjusting device includes a comparator and an inverter. The comparator includes a current source for generating an input current; a duty ratio adjusting circuit generates a first current and a second current according to the input current and a positive phase input signal and an inverted input signal; a current mirror having an input receiving the first current and an output electrically connected to a second output of the duty adjustment circuit, the current mirror generating a pair of outputs that should be first current and flow into itself A mapping current of the terminal, the comparator outputs a comparison signal at a common contact between the output terminal and the second output terminal. The inverter has an input terminal for receiving the comparison signal and an output terminal, and the inverter outputs an output signal at an output thereof according to the comparison signal.

Description

占空比調整裝置 Duty cycle adjustment device

本發明是有關於一種調整裝置,特別是指一種用來調整輸出信號之占空比的占空比調整裝置。 The invention relates to an adjusting device, in particular to a duty adjusting device for adjusting the duty ratio of an output signal.

參閱圖1,習知占空比調整裝置1包含一第一調整模組11及一第二調整模組12。該等第一及第二調整模組11、12中的每一者接收一正相輸入信號及一反相輸入信號,並根據該等正相及反相輸入信號來分別產生一第一輸出信號及一第二輸出信號。由於該第一調整模組11本身無法調整其所輸出的該第一輸出信號的占空比(duty cycle),因此習知占空比調整裝置1藉由增加該第二調整模組12來與該第一調整模組11相配合,以調整該等第一及第二調整模組11、12各自所輸出的該等第一及第二輸出信號的占空比。 Referring to FIG. 1 , the conventional duty adjustment device 1 includes a first adjustment module 11 and a second adjustment module 12 . Each of the first and second adjustment modules 11 and 12 receives a positive phase input signal and an inverted input signal, and respectively generates a first output signal according to the positive phase and the inverted input signals. And a second output signal. Since the first adjustment module 11 itself cannot adjust the duty cycle of the first output signal that is output by the first adjustment module 11 , the conventional duty adjustment device 1 is added by adding the second adjustment module 12 . The first adjustment module 11 cooperates to adjust the duty ratios of the first and second output signals respectively output by the first and second adjustment modules 11 and 12.

然而,在上述結構中,由於習知占空比調整裝置1需要該第二調整模組12才可操作來調整其所輸出之該等第一及第二輸出信號的占空比,因此,對於習知占空比調整裝置1而言,該第二 調整模組12是必要構件,其導致習知占空比調整裝置1的結構較為複雜,並具有電路面積較大、電能消耗較多及製造成本較高等缺點。 However, in the above configuration, since the conventional duty adjustment device 1 requires the second adjustment module 12 to be operable to adjust the duty ratios of the first and second output signals that are outputted therefrom, The conventional duty ratio adjusting device 1 is the second The adjustment module 12 is an essential component, which results in a complicated structure of the conventional duty ratio adjusting device 1 and has the disadvantages of large circuit area, high power consumption, and high manufacturing cost.

因此,本發明之目的,即在提供一種能夠克服先前技術缺點的占空比調整裝置。 Accordingly, it is an object of the present invention to provide a duty cycle adjustment apparatus that overcomes the disadvantages of the prior art.

於是,本發明占空比調整裝置,包含一調整模組。 Therefore, the duty ratio adjusting device of the present invention includes an adjustment module.

該調整模組包括一比較器及一反相器。 The adjustment module includes a comparator and an inverter.

該比較器用來接收一正相輸入信號及一反相輸入信號,並根據該等正相及反相輸入信號,產生並輸出一比較信號,且包括一電流源、一占空比調整電路及一電流鏡。 The comparator is configured to receive a positive phase input signal and an inverting input signal, and generate and output a comparison signal according to the positive phase and the inverted input signal, and includes a current source, a duty cycle adjustment circuit, and a Current mirror.

該電流源產生一輸入電流。 The current source produces an input current.

該占空比調整電路,具有一電連接該電流源以接收該輸入電流的第一輸入端、一接收該反相輸入信號的第二輸入端、一接收該正相輸入信號的第三輸入端、一第一輸出端及一第二輸出端,該占空比調整電路根據該輸入電流及該等正相及反相輸入信號,產生一第一電流及一第二電流,並在其該等第一及第二輸出端分別輸出該等第一與第二電流。 The duty ratio adjusting circuit has a first input end electrically connected to the current source to receive the input current, a second input end receiving the inverted input signal, and a third input end receiving the positive phase input signal a first output end and a second output end, the duty ratio adjusting circuit generates a first current and a second current according to the input current and the positive and negative input signals, and The first and second outputs respectively output the first and second currents.

該電流鏡具有一電連接該占空比調整電路之該第一輸出端以接收該第一電流的輸入端、及一電連接該占空比調整電路之 該第二輸出端的輸出端,該電流鏡產生一對應該第一電流且流入其本身之該輸出端的一映射電流,該電流鏡之該輸出端與該占空比調整電路之該第二輸出端間的一共同接點輸出該比較信號。 The current mirror has an input terminal electrically connected to the first output end of the duty ratio adjusting circuit to receive the first current, and an electrical connection to the duty ratio adjusting circuit An output end of the second output end, the current mirror generates a pair of mapping currents that should be the first current and flow into the output end of the current, the output end of the current mirror and the second output end of the duty cycle adjusting circuit A common contact between the outputs outputs the comparison signal.

該反相器具有一電連接該比較器之該共同接點以接收該比較信號的輸入端、及一輸出端,該反相器根據該比較信號,在其輸出端,輸出一輸出信號。 The inverter has an input terminal electrically connected to the common contact of the comparator to receive the comparison signal, and an output terminal, and the inverter outputs an output signal at an output thereof according to the comparison signal.

本發明之功效在於:該占空比調整裝置藉由該占空比調整電路來調整該輸出信號的占空比,可使該占空比調整裝置具有較簡單的電路結構,且可減少電路面積、降低電能消耗並且同時降低製造成本。 The effect of the invention is that the duty ratio adjusting device adjusts the duty ratio of the output signal by the duty ratio adjusting circuit, so that the duty adjusting device has a simpler circuit structure and can reduce the circuit area. Reduce power consumption while reducing manufacturing costs.

2‧‧‧調整模組 2‧‧‧Adjustment module

3‧‧‧比較器 3‧‧‧ comparator

31‧‧‧電流源 31‧‧‧current source

32‧‧‧占空比調整電路 32‧‧‧Duty cycle adjustment circuit

33‧‧‧電流鏡 33‧‧‧current mirror

331‧‧‧電晶體 331‧‧‧Optoelectronics

34、35‧‧‧第一調整單元 34, 35‧‧‧ first adjustment unit

341‧‧‧第一開關 341‧‧‧First switch

342‧‧‧第一電晶體 342‧‧‧First transistor

36、37‧‧‧第二調整單元 36, 37‧‧‧ second adjustment unit

361‧‧‧第二開關 361‧‧‧second switch

362‧‧‧第二電晶體 362‧‧‧Second transistor

38‧‧‧第三電晶體 38‧‧‧ Third transistor

39‧‧‧第四電晶體 39‧‧‧ Fourth transistor

4‧‧‧反相器 4‧‧‧Inverter

5‧‧‧控制電路 5‧‧‧Control circuit

C1‧‧‧比較信號 C1‧‧‧ comparison signal

C1’‧‧‧比較信號 C1’‧‧‧ comparison signal

C1”‧‧‧比較信號 C1”‧‧‧ comparison signal

CKP‧‧‧正相輸入信號 CK P ‧‧‧phase input signal

CKN‧‧‧反相輸入信號 CK N ‧‧‧Inverting input signal

Ts‧‧‧切換週期的長度 Length of Ts‧‧‧ switching cycle

t‧‧‧時間 t‧‧‧Time

t1‧‧‧時間點 T1‧‧‧ time

t2‧‧‧時間點 T2‧‧‧ time

t11‧‧‧時間點 T11‧‧‧ time point

t12‧‧‧時間點 T12‧‧‧ time point

t13‧‧‧時間點 T13‧‧‧ time point

t14‧‧‧時間點 T14‧‧‧ time point

Vo‧‧‧輸出信號 Vo‧‧‧ output signal

Vo,‧‧‧輸出信號 Vo, ‧‧‧ output signal

Vo”‧‧‧輸出信號 Vo"‧‧‧ output signal

V1‧‧‧轉態電壓 V1‧‧‧Transition voltage

Iin‧‧‧輸入電流 Iin‧‧‧ input current

Iin1‧‧‧第一分流 Iin1‧‧‧ first diversion

Iin2‧‧‧第二分流 Iin2‧‧‧Secondary

I1‧‧‧第一電流 I1‧‧‧First current

I2‧‧‧第二電流 I2‧‧‧second current

I1’‧‧‧映射電流 I1’‧‧‧ mapping current

P1‧‧‧第一輸入端 P1‧‧‧ first input

P2‧‧‧第二輸入端 P2‧‧‧ second input

P3‧‧‧第三輸入端 P3‧‧‧ third input

P4‧‧‧第一輸出端 P4‧‧‧ first output

P5‧‧‧第二輸出端 P5‧‧‧second output

Q1‧‧‧共同接點 Q1‧‧‧Common joint

S1‧‧‧第一控制信號 S1‧‧‧ first control signal

S2‧‧‧第一控制信號 S2‧‧‧ first control signal

S3‧‧‧第二控制信號 S3‧‧‧second control signal

S4‧‧‧第二控制信號 S4‧‧‧second control signal

本發明之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中:圖1是一電路圖,說明習知一占空比調整裝置;圖2是一電路圖,說明本發明占空比調整裝置之第一實施例;圖3是一時序圖,說明該第一實施例之一輸出信號的占空比;圖4至圖6是電路圖,各自說明該第一實施例之二個第一開關及二個第二開關的切換情況;及圖7是一電路圖,說明本發明占空比調整裝置之第二實施例。 Other features and effects of the present invention will be apparent from the embodiments of the present invention, wherein: FIG. 1 is a circuit diagram illustrating a conventional duty cycle adjustment apparatus; FIG. 2 is a circuit diagram illustrating the present invention. The first embodiment of the air ratio adjusting device; FIG. 3 is a timing chart illustrating the duty ratio of the output signal of one of the first embodiments; FIG. 4 to FIG. 6 are circuit diagrams, each of which illustrates the two of the first embodiment. The switching of the first switch and the two second switches; and FIG. 7 is a circuit diagram illustrating the second embodiment of the duty ratio adjusting device of the present invention.

在本發明被詳細描述之前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。 Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

<第一實施例> <First Embodiment>

參閱圖2,本發明占空比調整裝置之第一實施例包含一調整模組2。該調整模組2包括一比較器3及一反相器4。 Referring to FIG. 2, a first embodiment of the duty cycle adjusting device of the present invention includes an adjustment module 2. The adjustment module 2 includes a comparator 3 and an inverter 4.

該比較器3用來接收一正相輸入信號及一反相輸入信號,並根據該等正相及反相輸入信號,產生並輸出一比較信號。該比較器3包括一電流源31、一占空比調整電路32及一電流鏡33。 The comparator 3 is configured to receive a positive phase input signal and an inverting input signal, and generate and output a comparison signal according to the positive phase and the inverted input signal. The comparator 3 includes a current source 31, a duty ratio adjustment circuit 32, and a current mirror 33.

該電流源31產生一輸入電流Iin。 The current source 31 produces an input current Iin.

該占空比調整電路32具有一電連接該電流源31以接收該輸入電流Iin的第一輸入端P1、一接收該反相輸入信號的第二輸入端P2、一接收該正相輸入信號的第三輸入端P3、一第一輸出端P4及一第二輸出端P5。該占空比調整電路32根據該輸入電流Iin及該等正相及反相輸入信號,產生一第一電流I1及一第二電流I2,並在其該等第一及第二輸出端P4、P5分別輸出該等第一與第二電流I1、I2。在本實施例中,該占空比調整電路32包括二個第一調整單元34、35、二個第二調整單元36、37、一第三電晶體38、一第四電晶體39,但不限於此。在其他實施例中,第一調整單元的數量可 為一或大於二,第二調整單元的數量可為一或大於二,且第一調整單元的數量等於第二調整單元的數量。 The duty ratio adjusting circuit 32 has a first input terminal P1 electrically connected to the current source 31 for receiving the input current Iin, a second input terminal P2 receiving the inverted input signal, and a receiving the positive phase input signal. The third input terminal P3, a first output terminal P4 and a second output terminal P5. The duty ratio adjusting circuit 32 generates a first current I1 and a second current I2 according to the input current Iin and the positive and negative input signals, and at the first and second output terminals P4 thereof, P5 outputs the first and second currents I1, I2, respectively. In this embodiment, the duty ratio adjusting circuit 32 includes two first adjusting units 34, 35, two second adjusting units 36, 37, a third transistor 38, and a fourth transistor 39, but Limited to this. In other embodiments, the number of first adjustment units is For one or more than two, the number of the second adjustment units may be one or more than two, and the number of the first adjustment units is equal to the number of the second adjustment units.

每一第一調整單元34、35包括一第一開關341及一第一電晶體342。該第一開關341及該第一電晶體342串聯連接在該第一輸入端P1及該第一輸出端P4之間。該第一開關341接收一第一控制信號S1(S2),且根據該第一控制信號S1(S2)而於導通與不導通之間切換。該第一電晶體342具有一用以接收該反相輸入信號的控制端,以致該第一電晶體342根據該反相輸入信號導通或不導通。 Each of the first adjusting units 34 and 35 includes a first switch 341 and a first transistor 342. The first switch 341 and the first transistor 342 are connected in series between the first input terminal P1 and the first output terminal P4. The first switch 341 receives a first control signal S1 (S2) and switches between conduction and non-conduction according to the first control signal S1 (S2). The first transistor 342 has a control terminal for receiving the inverted input signal, such that the first transistor 342 is turned on or off according to the inverted input signal.

每一第二調整單元36、37包括一第二開關361及一第二電晶體362。該第二開關361及該第二電晶體362串聯連接在該第一輸入端P1及該第二輸出端P5之間。該第二開關361接收一第二控制信號S3(S4),且根據該第二控制信號S3(S4)而於導通與不導通之間切換。該第二電晶體362具有一用以接收該正相輸入信號的控制端,以致該第二電晶體362根據該正相輸入信號導通或不導通。 Each of the second adjusting units 36 and 37 includes a second switch 361 and a second transistor 362. The second switch 361 and the second transistor 362 are connected in series between the first input terminal P1 and the second output terminal P5. The second switch 361 receives a second control signal S3 (S4) and switches between conduction and non-conduction according to the second control signal S3 (S4). The second transistor 362 has a control terminal for receiving the positive phase input signal, such that the second transistor 362 is turned on or off according to the positive phase input signal.

該第三電晶體38具有一電連接該第一輸入端P1的第一端、一電連接該第一輸出端P4的第二端、及一用以接收該反相輸入信號的控制端,以致該第三電晶體38根據該反相輸入信號導通或不導通。 The third transistor 38 has a first end electrically connected to the first input end P1, a second end electrically connected to the first output end P4, and a control end for receiving the inverted input signal, such that The third transistor 38 is turned on or off according to the inverting input signal.

該第四電晶體39具有一電連接該第一輸入端P1的第一端、一電連接該第二輸出端P5的第二端、及一用以接收該正相輸入 信號的控制端,以致該第四電晶體39根據該正相輸入信號導通或不導通。 The fourth transistor 39 has a first end electrically connected to the first input end P1, a second end electrically connected to the second output end P5, and a receiving end of the positive phase input The control terminal of the signal is such that the fourth transistor 39 is turned on or off according to the positive phase input signal.

需說明的是,在本實施例中,該等第一至第四電晶體342、362、38、39各自為一P型金氧半場效電晶體。該等第一及第二開關341、361各自也可由一P型金氧半場效電晶體來實現。該等第一及第二控制信號S1、S2、S3、S4之每一者具有一高邏輯準位及一低邏輯準位。該等第一及第二控制信號S1、S2、S3、S4是由使用者根據其所欲調整的每一開關341、361的切換情況,而手動操控相關電路來提供。 It should be noted that, in this embodiment, the first to fourth transistors 342, 362, 38, and 39 are each a P-type MOS field effect transistor. Each of the first and second switches 341, 361 can also be implemented by a P-type MOS field effect transistor. Each of the first and second control signals S1, S2, S3, S4 has a high logic level and a low logic level. The first and second control signals S1, S2, S3, and S4 are provided by the user manually controlling the relevant circuit according to the switching condition of each switch 341, 361 that the user desires to adjust.

該電流鏡33具有一電連接該占空比調整電路32之該第一輸出端P4以接收該第一電流I1的輸入端、及一電連接該占空比調整電路32之該第二輸出端P5的輸出端。該電流鏡33產生一對應該第一電流I1且流入其本身之該輸出端的一映射電流I1’。該電流鏡33之該輸出端與該占空比調整電路32之該第二輸出端P5間的一共同接點Q1輸出該比較信號。該電流鏡33包括二個電晶體331,其各自具有一第一端、一接地的第二端、及一控制端,該等電晶體331的該等第一端分別作為該電流鏡33之該輸入端與該輸出端,該等電晶體331的該等控制端電連接至該電流鏡33之該輸入端。在本實施例中,該等電晶體331各自為一N型金氧半場效電晶體,其中該N 型金氧半場效電晶體的汲極、源極及閘極分別為該等電晶體331中的每一者的該第一端、該第二端及該控制端。 The current mirror 33 has an input terminal electrically connected to the first output terminal P4 of the duty ratio adjusting circuit 32 to receive the first current I1, and an electrical output connected to the second output end of the duty ratio adjusting circuit 32. The output of P5. The current mirror 33 produces a pair of mapping currents I1' which should be at the first current I1 and flow into the output of itself. The comparison signal is outputted from a common contact Q1 between the output terminal of the current mirror 33 and the second output terminal P5 of the duty ratio adjustment circuit 32. The current mirror 33 includes two transistors 331 each having a first end, a grounded second end, and a control end. The first ends of the transistors 331 are respectively used as the current mirror 33. The input terminal and the output terminal, the control terminals of the transistors 331 are electrically connected to the input end of the current mirror 33. In this embodiment, the transistors 331 are each an N-type gold oxide half field effect transistor, wherein the N The drain, source and gate of the MOS field-effect transistor are respectively the first end, the second end and the control terminal of each of the transistors 331.

該反相器4具有一電連接該比較器3之該共同接點Q1以接收該比較信號的輸入端、及一輸出端。該反相器4根據該比較信號,在其輸出端,輸出一輸出信號。 The inverter 4 has an input terminal electrically connected to the common contact Q1 of the comparator 3 to receive the comparison signal, and an output terminal. The inverter 4 outputs an output signal at its output based on the comparison signal.

在操作時,本發明占空比調整裝置調整該輸出信號之占空比(duty cycle)的實現方式為:若該輸出信號的占空比偏小(如,小於0.3),可藉由減少該等第二電晶體362與該第四電晶體39並聯的數量,也就是說,將該等第二開關361中的至少一者切換為不導通,來使該輸出信號的占空比提高。同理,若該輸出信號的占空比偏大(如,大於0.7),可藉由減少該等第一電晶體342與該第三電晶體38並聯的數量,即將該等第一開關341中的至少一者切換為不導通,來使該輸出信號的占空比下降。 In operation, the duty cycle adjusting device of the present invention adjusts the duty cycle of the output signal by: if the duty ratio of the output signal is small (eg, less than 0.3), by reducing the The second transistor 362 is connected in parallel with the fourth transistor 39, that is, at least one of the second switches 361 is switched to be non-conductive to increase the duty ratio of the output signal. Similarly, if the duty ratio of the output signal is too large (eg, greater than 0.7), the number of the first transistor 342 and the third transistor 38 can be reduced in parallel, that is, in the first switch 341. At least one of the switches switches to non-conduction to reduce the duty cycle of the output signal.

參閱圖3,為本實施例的操作時序圖,參數CKP、CKN分別為該等正相及反相輸入信號,參數Ts為該等正相及反相輸入信號CKP、CKN的一切換週期的長度,參數t為時間,參數C1、Vo分別為該等第一及第二開關341、361皆導通(參閱圖4)時的該比較信號及該輸出信號,參數C1’、Vo’分別為該第二開關361不導通(參閱圖5)時的該比較信號及該輸出信號,參數C1”、Vo”分別為該第一開關341不導通(參閱圖6)時的該比較信號及該輸出信號。圖4至 圖6的電路圖與圖2相似,主要差異在於圖4至圖6中,導通的元件以實線畫出,而不導通的元件以虛線畫出。 Referring to FIG. 3, which is an operation timing diagram of the embodiment, parameters CK P and CK N are respectively the positive and negative input signals, and the parameter Ts is one of the positive and negative input signals CK P and CK N . The length of the switching period, the parameter t is time, and the parameters C1 and Vo are respectively the comparison signal and the output signal when the first and second switches 341 and 361 are both turned on (refer to FIG. 4), and the parameters C1' and Vo' The comparison signal and the output signal when the second switch 361 is not turned on (see FIG. 5), respectively, the parameters C1", Vo" are the comparison signals when the first switch 341 is not conductive (refer to FIG. 6) and The output signal. The circuit diagrams of Figures 4 through 6 are similar to those of Figure 2, with the main difference being that in Figures 4 through 6, the conductive elements are drawn in solid lines and the non-conducting elements are drawn in dashed lines.

參閱圖3、圖4,正常操作下,由於該等第一及第二開關341、361皆導通,因此當該正相輸入信號CKP等於該反相輸入信號CKN時,一第一分流Iin1等於一第二分流Iin2(該等第一及第二分流Iin1、Iin2之和等於該輸入電流Iin,Iin1=Iin2=0.5×Iin)。此時,該比較信號C1的電壓大小等於該反向器4的一轉態電壓V1,因此該輸出信號Vo的電壓準位會從高(低)邏輯準位切換成低(高)邏輯準位。該輸出信號Vo的占空比如圖3所示。 Referring to FIG. 3 and FIG. 4, in normal operation, since the first and second switches 341 and 361 are both turned on, when the positive phase input signal CK P is equal to the inverted input signal CK N , a first shunt Iin1 It is equal to a second shunt Iin2 (the sum of the first and second shunts Iin1, Iin2 is equal to the input current Iin, Iin1=Iin2=0.5×Iin). At this time, the voltage of the comparison signal C1 is equal to a transition voltage V1 of the inverter 4, so the voltage level of the output signal Vo is switched from a high (low) logic level to a low (high) logic level. . The duty ratio of the output signal Vo is as shown in FIG.

參閱圖3、圖5,若該輸出信號的占空比偏小,將該等第二開關361中的至少一者切換為不導通,可使該輸出信號的占空比提高。在本實施例中,是舉將遠離該電流源31的該第二開關361切換為不導通為例,但不限於此。由於減少該等第二電晶體362的並聯數量意味著該占空比調整電路32中右邊電路的電阻會上升,因此,舉例來說,當該正相輸入信號CKP等於該反相輸入信號CKN時,流入右邊電路的總電流(即該第二分流Iin2)就會減少,使得該第一分流Iin1大於該第二分流Iin2,且該映射電流I1’等於該第一電流I1,該第一電流I1等於該第一分流Iin1,該第二電流I2等於該第二分流Iin2,該比較信號C1’的電壓大小相關於該第二分流Iin2及該映射電流I1’間的差值。如此,在充電階段時,該比較信號C1’ 上升的速度會變慢,該比較信號C1’的電壓會在時間點t11才上升到該轉態電壓V1,導致該輸出信號Vo’延遲轉態(即,晚於時間點t1,才從高邏輯準位切換成低邏輯準位);而在放電階段時,該比較信號C1’下降的速度會變快,該比較信號C1’的電壓會在時間點t12就下降到該轉態電壓V1,導致該輸出信號Vo’提早轉態(即,早於時間點t2,就從低邏輯準位切換成高邏輯準位)。如此一來,使得該輸出信號Vo’的占空比提高。 Referring to FIGS. 3 and 5, if the duty ratio of the output signal is too small, at least one of the second switches 361 is switched to be non-conductive, and the duty ratio of the output signal can be increased. In the present embodiment, the second switch 361 remote from the current source 31 is switched to be non-conductive, but is not limited thereto. Since reducing the parallel number of the second transistors 362 means that the resistance of the right circuit in the duty ratio adjusting circuit 32 rises, for example, when the positive phase input signal CK P is equal to the inverted input signal CK N , the total current flowing into the right circuit (ie, the second shunt Iin2) is reduced, such that the first shunt Iin1 is greater than the second shunt Iin2, and the mapping current I1' is equal to the first current I1, the first The current I1 is equal to the first shunt Iin1, the second current I2 is equal to the second shunt Iin2, and the voltage of the comparison signal C1' is related to the difference between the second shunt Iin2 and the mapping current I1'. Thus, during the charging phase, the rising speed of the comparison signal C1' will be slower, and the voltage of the comparison signal C1' will rise to the transition voltage V1 at the time point t11, causing the output signal Vo' to delay the transition state ( That is, after the time point t1, the high logic level is switched to the low logic level); while in the discharge phase, the speed of the comparison signal C1' decreases, and the voltage of the comparison signal C1' will be in time. The point t12 falls to the transition voltage V1, causing the output signal Vo' to transition early (i.e., switching from a low logic level to a high logic level earlier than the time point t2). In this way, the duty ratio of the output signal Vo' is increased.

參閱圖3、圖6,若該輸出信號的占空比偏大,將該等第一開關341中的至少一者切換為不導通,可使該輸出信號的占空比下降。在本實施例中,是舉將遠離該電流源31的該第一開關341切換為不導通為例,但不限於此。同理,減少該等第一電晶體342的並聯數量會使該占空比調整電路32中左邊電路的電阻上升,因此,舉例來說,當該正相輸入信號CKP等於該反相輸入信號CKN時,流入左邊電路的總電流(即該第一分流Iin1)就會減少,使得該第一分流Iin1小於該第二分流Iin2,且該映射電流I1’等於該第一電流I1,該第一電流I1等於該第一分流Iin1,該第二電流I2等於該第二分流Iin2,該比較信號C1”的電壓大小相關於該第二分流Iin2及該映射電流I1’間的差值。如此,在充電階段時,該比較信號C1”上升的速度會變快,該比較信號C1”的電壓會在時間點t13就上升到該轉態電壓V1,導致該輸出信號Vo”提早轉態(即,早於時間點 t1,就從高邏輯準位切換成低邏輯準位);而在放電階段時,該比較信號C1”下降的速度會變慢,該比較信號C1”的電壓會在時間點t14才下降到該轉態電壓V1,導致該輸出信號Vo”延遲轉態(即,晚於時間點t2,才從低邏輯準位切換成高邏輯準位)。如此一來,使得該輸出信號Vo”的占空比下降。 Referring to FIGS. 3 and 6, if the duty ratio of the output signal is too large, at least one of the first switches 341 is switched to be non-conductive, and the duty ratio of the output signal can be lowered. In the present embodiment, the first switch 341 remote from the current source 31 is switched to be non-conductive, but is not limited thereto. Similarly, reducing the number of parallel connections of the first transistors 342 causes the resistance of the left circuit in the duty cycle adjusting circuit 32 to rise, so that, for example, when the positive phase input signal CK P is equal to the inverted input signal When CK N , the total current flowing into the left circuit (ie, the first shunt Iin1) is reduced, so that the first shunt Iin1 is smaller than the second shunt Iin2, and the mapping current I1' is equal to the first current I1. A current I1 is equal to the first shunt Iin1, the second current I2 is equal to the second shunt Iin2, and the voltage magnitude of the comparison signal C1" is related to the difference between the second shunt Iin2 and the mapping current I1'. During the charging phase, the rising speed of the comparison signal C1" will become faster, and the voltage of the comparison signal C1" will rise to the transition voltage V1 at the time point t13, causing the output signal Vo" to transition early (ie, Before the time point t1, the high logic level is switched to the low logic level); in the discharging phase, the speed of the comparison signal C1" is slowed down, and the voltage of the comparison signal C1" will be at the time point t14. Only fall to the transition voltage V1, causing the loss Signal Vo "transient delay (i.e., later than the time point T2, it is switched from the low logic level to a high logic level). In this way, so that the output signal Vo" decrease duty cycle.

<第二實施例> <Second embodiment>

圖7繪示本發明占空比調整裝置之第二實施例,其與第一實施例相似,二者不同之處在於:此實施例還包括一控制電路5。該控制電路5電連接該二個第一開關341及該二個第二開關361,且電連接該反相器4之該輸出端以接收該輸出信號,並根據該輸出信號產生該等第一及第二控制信號S1、S2、S3、S4,而且將該等第一及第二控制信號S1、S2、S3、S4分別輸出至該二個第一開關341及該二個第二開關361。藉由該控制電路5自動調整該等第一及第二開關341、361的導通情況也可達到調整該輸出信號之占空比的功效。 FIG. 7 illustrates a second embodiment of the duty cycle adjusting device of the present invention, which is similar to the first embodiment, except that the embodiment further includes a control circuit 5. The control circuit 5 is electrically connected to the two first switches 341 and the two second switches 361, and is electrically connected to the output end of the inverter 4 to receive the output signal, and generates the first according to the output signal. And the second control signals S1, S2, S3, and S4, and the first and second control signals S1, S2, S3, and S4 are output to the two first switches 341 and the two second switches 361, respectively. The effect of adjusting the duty ratio of the output signal can also be achieved by the control circuit 5 automatically adjusting the conduction of the first and second switches 341, 361.

綜上所述,由於本發明占空比調整裝置僅需一個調整模組2,並藉由切換該等第一及第二開關341、361即可調整該輸出信號之占空比,所以本發明占空比調整裝置不需如習知占空比調整裝置1(見圖1)需額外增加第二調整模組12。因此,本發明占空比調 整裝置相較於習知占空比調整裝置1具有較簡單的電路結構,且可減少電路面積、降低電能消耗並且同時降低製造成本。 In summary, since the duty ratio adjusting device of the present invention requires only one adjustment module 2, and the duty ratio of the output signal can be adjusted by switching the first and second switches 341, 361, the present invention The duty ratio adjusting device does not need to additionally add the second adjusting module 12 as in the conventional duty ratio adjusting device 1 (see FIG. 1). Therefore, the duty cycle of the present invention The whole device has a simpler circuit structure than the conventional duty ratio adjusting device 1, and can reduce the circuit area, reduce power consumption, and at the same time reduce manufacturing costs.

惟以上所述者,僅為本發明之實施例而已,當不能以此限定本發明實施之範圍,凡是依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。 However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.

Claims (5)

一種占空比調整裝置,包含:一調整模組,包括一比較器,用來接收一正相輸入信號及一反相輸入信號,並根據該等正相及反相輸入信號,產生並輸出一比較信號,且包括一電流源,產生一輸入電流,一占空比調整電路,具有一電連接該電流源以接收該輸入電流的第一輸入端、一接收該反相輸入信號的第二輸入端、一接收該正相輸入信號的第三輸入端、一第一輸出端及一第二輸出端,該占空比調整電路根據該輸入電流及該等正相及反相輸入信號,產生一第一電流及一第二電流,並在其該等第一及第二輸出端分別輸出該等第一與第二電流,及一電流鏡,具有一電連接該占空比調整電路之該第一輸出端以接收該第一電流的輸入端、及一電連接該占空比調整電路之該第二輸出端的輸出端,該電流鏡產生一對應該第一電流且流入其本身之該輸出端的一映射電流,該電流鏡之該輸出端與該占空比調整電路之該第二輸出端間的一共同接點輸出該比較信號,及一反相器,具有一電連接該比較器之該共同接點以接收該比較信號的輸入端、及一輸出端,該反相器根據該比較信號,在其輸出端,輸出一輸出信號;該占空比調整電路包括:一第一調整單元,包括一第一開關及一第一電晶體,串聯連接在該第一輸入端及該第一輸出端之間,該第一開關接收一第一控制信號,且根據該第一控制信號而於導通與不導通之間切換,該第一電晶體具有一用以接收該反相輸入信號的控制端,以致該第一電晶體根據該反相輸入信號導通或不導通;一第二調整單元,包括一第二開關及一第二電晶體,串聯連接在該第一輸入端及該第二輸出端之間,該第二開關接收一第二控制信號,且根據該第二控制信號而於導通與不導通之間切換,該第二電晶體具有一用以接收該正相輸入信號的控制端,以致該第二電晶體根據該正相輸入信號導通或不導通;一第三電晶體,具有一電連接該第一輸入端的第一端、一電連接該第一輸出端的第二端、及一用以接收該反相輸入信號的控制端,以致該第三電晶體根據該反相輸入信號導通或不導通;及一第四電晶體,具有一電連接該第一輸入端的第一端、一電連接該第二輸出端的第二端、及一用以接收該正相輸入信號的控制端,以致該第四電晶體根據該正相輸入信號導通或不導通。A duty adjustment device includes: an adjustment module, comprising a comparator for receiving a positive phase input signal and an inverting input signal, and generating and outputting a positive phase and an inverted input signal according to the positive phase and the inverted input signal Comparing the signal, and including a current source, generating an input current, a duty cycle adjusting circuit having a first input electrically connected to the current source to receive the input current, and a second input receiving the inverted input signal a third input end, a first output end and a second output end receiving the positive phase input signal, the duty ratio adjusting circuit generates a signal according to the input current and the positive phase and the inverted input signal a first current and a second current, respectively outputting the first and second currents at the first and second output ends, and a current mirror having an electrical connection to the duty adjustment circuit An output terminal for receiving the first current, and an output terminal electrically connected to the second output terminal of the duty ratio adjusting circuit, the current mirror generating a pair of currents corresponding to the first current and flowing into the output terminal of the current One map a common contact between the output end of the current mirror and the second output end of the duty ratio adjusting circuit, and an inverter having an electrical connection to the common connection of the comparator Pointing to receive the input end of the comparison signal, and an output end, the inverter outputs an output signal at an output end thereof according to the comparison signal; the duty ratio adjustment circuit includes: a first adjustment unit, including a The first switch and a first transistor are connected in series between the first input end and the first output end, the first switch receives a first control signal, and is turned on and off according to the first control signal Switching between conduction, the first transistor has a control terminal for receiving the inverted input signal, such that the first transistor is turned on or off according to the inverted input signal; and a second adjustment unit includes a first a second switch and a second transistor connected in series between the first input end and the second output end, the second switch receiving a second control signal, and being turned on and off according to the second control signal Switch between The second transistor has a control terminal for receiving the positive phase input signal, such that the second transistor is turned on or off according to the positive phase input signal; and a third transistor having an electrical connection to the first input a first end of the terminal, a second end electrically connected to the first output end, and a control end for receiving the inverted input signal, such that the third transistor is turned on or off according to the inverted input signal; a fourth transistor having a first end electrically connected to the first input end, a second end electrically connected to the second output end, and a control end for receiving the positive phase input signal, so that the fourth transistor The positive phase input signal is turned on or off according to the positive phase input signal. 如請求項1所述的占空比調整裝置,還包含:一控制電路,電連接該等第一及第二開關,且電連接該反相器之該輸出端以接收該輸出信號,並根據該輸出信號產生該等第一及第二控制信號,而且將該等第一及第二控制信號分別輸出至該等第一及第二開關,該等第一及第二控制信號之每一者具有一高邏輯準位及一低邏輯準位。The duty ratio adjusting device of claim 1, further comprising: a control circuit electrically connecting the first and second switches, and electrically connecting the output end of the inverter to receive the output signal, and according to The output signals generate the first and second control signals, and the first and second control signals are respectively output to the first and second switches, each of the first and second control signals Has a high logic level and a low logic level. 如請求項1所述的占空比調整裝置,其中,該等第一至第四電晶體各自為一P型金氧半場效電晶體。The duty ratio adjusting device of claim 1, wherein the first to fourth transistors are each a P-type MOSFET. 如請求項1所述的占空比調整裝置,其中,於該電流鏡中,該電流鏡包括:二個電晶體,其各自具有一第一端、一接地的第二端、及一控制端,該等電晶體的該等第一端分別作為該輸入端與該輸出端,該等電晶體的該等控制端電連接至該輸入端。The duty ratio adjusting device of claim 1, wherein in the current mirror, the current mirror comprises: two transistors each having a first end, a grounded second end, and a control end The first ends of the transistors serve as the input terminal and the output terminal, respectively, and the control terminals of the transistors are electrically connected to the input terminal. 如請求項4所述的占空比調整裝置,其中,該等電晶體各自為一N型金氧半場效電晶體,且該N型金氧半場效電晶體的汲極、源極及閘極分別為該等電晶體中的每一者的該第一端、該第二端及該控制端。The duty ratio adjusting device according to claim 4, wherein each of the transistors is an N-type MOS field effect transistor, and the drain, the source and the gate of the N-type MOS field-effect transistor The first end, the second end, and the control end of each of the transistors are respectively.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6643790B1 (en) * 2000-03-06 2003-11-04 Rambus Inc. Duty cycle correction circuit with frequency-dependent bias generator
US20050134249A1 (en) * 2003-12-19 2005-06-23 Infineon Technologies Ag Circuit arrangement for regulating the duty cycle of electrical signal
US20080197903A1 (en) * 2005-01-14 2008-08-21 Mayo Foundation For Medical Education And Research Clock Pulse Duty Cycle Control Circuit for a Clock Fanout Chip
TWI505645B (en) * 2012-01-03 2015-10-21 Nanya Technology Corp Duty cycle controlling circuit, duty cycle adjusting cell, and duty cycle detecting circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6643790B1 (en) * 2000-03-06 2003-11-04 Rambus Inc. Duty cycle correction circuit with frequency-dependent bias generator
US20050134249A1 (en) * 2003-12-19 2005-06-23 Infineon Technologies Ag Circuit arrangement for regulating the duty cycle of electrical signal
US20080197903A1 (en) * 2005-01-14 2008-08-21 Mayo Foundation For Medical Education And Research Clock Pulse Duty Cycle Control Circuit for a Clock Fanout Chip
TWI505645B (en) * 2012-01-03 2015-10-21 Nanya Technology Corp Duty cycle controlling circuit, duty cycle adjusting cell, and duty cycle detecting circuit

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