TWI640182B - Receiving device and log-likelihood generating method - Google Patents

Receiving device and log-likelihood generating method Download PDF

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TWI640182B
TWI640182B TW106143096A TW106143096A TWI640182B TW I640182 B TWI640182 B TW I640182B TW 106143096 A TW106143096 A TW 106143096A TW 106143096 A TW106143096 A TW 106143096A TW I640182 B TWI640182 B TW I640182B
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ratio
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TW201926963A (en
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賴科印
廖懿穎
童泰來
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晨星半導體股份有限公司
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Abstract

一種接收裝置,包括一等化器,用來產生一等化信號以及一第一信號,該等化信號位於一決策區域;一序列估測器,用來根據該第一信號,產生一估測信號;一解碼器;以及一對數概度比計算器,用來根據該等化信號以及該估測信號,產生複數個對數概度比,其中當該估測信號不位於該決策區域時,至少一對數概度比為0。A receiving device includes an equalizer for generating an equalized signal and a first signal, the equalized signal being located in a decision area, and a sequence estimator for generating an estimate based on the first signal a signal; a decoder; and a pair-to-number ratio ratio calculator for generating a plurality of logarithmic probability ratios based on the equalized signal and the estimated signal, wherein when the estimated signal is not located in the decision region, at least The one-to-one ratio is 0.

Description

接收裝置及對數概度比產生方法Receiving device and logarithmic probability ratio generating method

本發明係指一種接收裝置及對數概度比產生方法,尤指一種避免錯誤遞延的接收裝置及對數概度比產生方法。The present invention relates to a receiving apparatus and a logarithmic probability ratio generating method, and more particularly to a receiving apparatus and a logarithmic probability ratio generating method for avoiding erroneous deferral.

決策反饋等化器(DFE)已廣泛應用於接收端中,然而,決策反饋等化器具有錯誤遞延(Error Propagation)的缺點。也就是說,當決策錯誤時,決策反饋等化器會根據錯誤的決策對接收信號進行等化,進而降低等化器的效能,並產生更多的錯誤決策。Decision feedback equalizer (DFE) has been widely used in the receiving end. However, the decision feedback equalizer has the disadvantage of Error Propagation. That is to say, when the decision is wrong, the decision feedback equalizer will equalize the received signal according to the wrong decision, thereby reducing the performance of the equalizer and generating more wrong decisions.

另一方面,現行通訊系統的接收端可利用低密度同位檢查碼(LDPC)解碼器對信號進行解碼,LDPC解碼器需要正確的對數概度比才能正確的進行解碼,而決策反饋等化器的錯誤遞延會將更多錯誤的對數概度比輸出至LDPC解碼器,導致LDPC解碼器的錯誤率上升。On the other hand, the receiving end of the current communication system can decode the signal by using a low density parity check code (LDPC) decoder, and the LDPC decoder needs the correct logarithmic probability ratio to correctly decode, and the decision feedback equalizer False deferral will output more erroneous logarithmic odds ratios to the LDPC decoder, resulting in an increase in the error rate of the LDPC decoder.

因此,如何產生避免錯誤遞延的對數概度比,也就成為業界所努力的目標之一。Therefore, how to generate a logarithmic ratio that avoids erroneous deferral has become one of the goals of the industry.

因此,本發明之主要目的即在於提供一種避免錯誤遞延的接收裝置及對數概度比產生方法,以改善習知技術的缺點。Accordingly, it is a primary object of the present invention to provide a receiving apparatus and a logarithmic ratio ratio generating method that avoid erroneous deferral to improve the disadvantages of the prior art.

本發明實施例揭露一種接收裝置,包括一等化器,用來接收一接收信號,並產生一等化信號以及一第一信號,其中該等化信號對應複數個位元,該等化信號位於複數個決策區域中一決策區域,該複數個決策區域的每一決策區域對應該複數個位元的一組位元值;一序列估測器,耦接於該等化器,用來根據該第一信號,產生一估測信號;一對數概度比計算器,耦接於該等化器以及該序列估測器,用來根據該等化信號以及該估測信號,產生對應於該複數個位元的複數個對數概度比,其中當該估測信號不位於該決策區域時,該複數個對數概度比中至少一對數概度比為0;以及一解碼器,耦接於該對數概度比計算器,用來根據該複數個對數概度比進行解碼。The embodiment of the invention discloses a receiving device, comprising an equalizer for receiving a received signal and generating an equalized signal and a first signal, wherein the equalized signal corresponds to a plurality of bits, and the equalized signal is located a decision area in a plurality of decision areas, each decision area of the plurality of decision areas corresponding to a set of bit values of a plurality of bits; a sequence estimator coupled to the equalizer for a first signal, generating an estimated signal; a pair of odds ratio calculator coupled to the equalizer and the sequence estimator for generating a corresponding number based on the equalized signal and the estimated signal a plurality of logarithmic probability ratios of the plurality of bits, wherein when the estimated signal is not located in the decision region, the ratio of the at least one pair of the logarithmic odds ratio is 0; and a decoder coupled to the A log-probability ratio calculator for decoding based on the complex log-probability ratio.

本發明實施例另揭露一種對數概度比產生方法,應用於一接收裝置的一對數概度比計算器,其中該對數概度比計算器耦接於該接收裝置的一等化器以及一序列估測器,該對數概度比產生方法包括自該等化器及該序列估測器接收一等化信號以及一估測信號,其中該等化器根據一接收信號產生該等化信號,該等化信號對應複數個位元,該等化信號位於複數個決策區域中一決策區域,該複數個決策區域的每一決策區域對應該複數個位元的一組位元值;以及根據該等化信號以及該估測信號,產生對應於該複數個位元的複數個對數概度比,其中當該估測信號不位於該決策區域時,該複數個對數概度比中至少一對數概度比為0;其中,該接收裝置的一解碼器根據該複數個對數概度比號進行解碼。The embodiment of the present invention further discloses a log-probability ratio generating method, which is applied to a pair-amount ratio ratio calculator of a receiving device, wherein the log-probability ratio calculator is coupled to the equalizer and a sequence of the receiving device. The estimator, the log-probability ratio generating method includes receiving an equalization signal and an estimation signal from the equalizer and the sequence estimator, wherein the equalizer generates the equalization signal according to a received signal, The equalization signal corresponds to a plurality of bits, and the equalization signal is located in a decision region of the plurality of decision regions, each decision region of the plurality of decision regions corresponding to a set of bit values of the plurality of bits; and according to the plurality of bits And the estimated signal, generating a plurality of log-probability ratios corresponding to the plurality of bits, wherein at least one pair of values in the plurality of log-probability ratios when the estimated signal is not located in the decision region The ratio is 0; wherein a decoder of the receiving device decodes according to the plurality of log-probability ratio numbers.

請參考第1圖,第1圖為本發明實施例一接收裝置10之方塊圖。接收裝置10用於一通訊系統,其包括一等化器12、一序列估測器14、一對數概度比計算器16以及一解碼器18。等化器12可為一決策反饋等化器(Decision Feedback Equalizer,DFE),用來接收一接收信號y n+ Δ,並根據接收信號y n+ Δ產生一等化信號z n以及一信號r n。序列估測器14耦接於等化器12,用來根據信號r n產生一估測信號x t,n,序列估測器14可為一最大似然序列估測器(Maximum Likelihood Sequence Estimator,MLSE)。其中,等化信號z n以及接收信號y n+Δ分別代表於時間n所接收到的等化信號以及時間(n+Δ)所接收到的接收信號,等化信號z n可被解調(Demodulated)成複數個位元b 0~b L-1,即等化信號z n可對應於複數個位元b 0~b L-1。對數概度比計算器16耦接於等化器12及序列估測器14,用來比對等化信號z n以及估測信號x t,n,並根據比對結果產生對應於複數個位元b 0~b L-1的複數個對數概度比LLR 0~LLR L-1。在後續說明書中,將等化信號z n與估測信號x t,n進行比對係指比對等化信號z n與估測信號x t,n於一星座平面的分佈,將詳述於後。解碼器18可為一低密度同位檢查碼(Low Density Parity Check,LDPC)解碼器,其耦接於對數概度比計算器16,用來根據對數概度比LLR 0~LLR L-1進行解碼。 Please refer to FIG. 1. FIG. 1 is a block diagram of a receiving apparatus 10 according to an embodiment of the present invention. The receiving device 10 is used in a communication system comprising an equalizer 12, a sequence estimator 14, a pairwise probability ratio calculator 16, and a decoder 18. The equalizer 12 can be a decision feedback equalizer (DFE) for receiving a received signal y n+ Δ and generating an equalized signal z n and a signal r n according to the received signal y n+ Δ . The sequence estimator 14 is coupled to the equalizer 12 for generating an estimated signal x t,n according to the signal r n , and the sequence estimator 14 can be a Maximum Likeli sequence estimator (Maximum Likelihood Sequence Estimator, MLSE). Wherein, the equalization signal z n and the received signal y n+Δ respectively represent the equalized signal received at time n and the received signal received at time (n+Δ), and the equalized signal z n can be demodulated ( Demodulated) into a plurality of bits b 0 ~ b L-1, i.e. equalized signal z n may correspond to a plurality of bits b 0 ~ b L-1. The log-probability ratio calculator 16 is coupled to the equalizer 12 and the sequence estimator 14 for comparing the equalized signal z n and the estimated signal x t,n and corresponding to the plurality of bits according to the comparison result. The complex logarithm of the elements b 0 to b L-1 is greater than LLR 0 to LLR L-1 . In the subsequent description, the equalization signal z n is compared with the estimated signal x t,n to compare the distribution of the equalization signal z n and the estimated signal x t,n to a constellation plane, which will be described in detail in Rear. The decoder 18 can be a Low Density Parity Check (LDPC) decoder coupled to the Logarithmic Probability Ratio Calculator 16 for decoding according to the logarithmic probability ratio LLR 0 to LLR L-1 . .

一般來說,若等化信號z n為以M階相位偏移調變(M-PSK (Phase Shift Keying))、M階脈波振幅調變(M-PAM (Pulse Amplitude Modulation))或M階正交振幅調變(M-QAM (Quadrature Amplitude Modulation))來進行調變的信號,等化信號z n可被解調成L個位元b 0~b L-1,其中M=2 L。另外,為了進行解調,一星座平面(或一複數平面)可被分割成複數個決策區域(Decision Region)R (0)~R (M-1),決策區域R (0)~R (M-1)中每一決策區域對應位元b 0~b L-1的一組位元值。舉例來說,請一併參考第3圖,第3圖為本發明實施例QPSK的4個星座點於星座平面分佈的示意圖,星座平面上任一個點s可解調出一組位元值b 1b 0,其中4個QPSK星座點可經過格雷編碼(Gray Coded),即相鄰的QPSK星座點的位元值組僅單一位元相異,4個QPSK以及其所代表的位元值組繪示於第3圖的左上圖。為了解調出位元值組b 1b 0,星座平面可被分割為決策區域R (0)~R (3)(繪示於第3圖的右下圖),位於決策區域R (0)、R (1)、R (2)、R (3)的星座點可分別代表(被解調為)b 1b 0=00、b 1b 0=01、b 1b 0=10或b 1b 0=11。 In general, if the equalization signal z n is M-PSK (Phase Shift Keying), M-PAM (Pulse Amplitude Modulation) or M-order The modulated signal is modulated by quadrature amplitude modulation (M-QAM), and the equalized signal z n can be demodulated into L bits b 0 to b L-1 , where M=2 L . In addition, for demodulation, a constellation plane (or a complex plane) can be divided into a plurality of decision regions (Decision Region) R (0) to R (M-1) , and decision regions R (0) to R (M) Each of the decision regions in -1) corresponds to a set of bit values of the bits b 0 to b L-1 . For example, please refer to FIG. 3 together. FIG. 3 is a schematic diagram of distribution of four constellation points of QPSK in a constellation plane according to an embodiment of the present invention. Any point s on the constellation plane can demodulate a set of bit values b 1 . b 0 , wherein 4 QPSK constellation points can be Gray Coded, that is, the bit value groups of adjacent QPSK constellation points are different only in a single bit, 4 QPSKs and the bit value groups they represent are drawn. Shown in the upper left of Figure 3. In order to demodulate the bit value group b 1 b 0 , the constellation plane can be divided into decision regions R (0) to R (3) (shown in the lower right diagram of FIG. 3), located in the decision region R (0) The constellation points of R (1) , R (2) , and R (3) may respectively represent (demodulated to) b 1 b 0 =00, b 1 b 0 =01, b 1 b 0 =10 or b 1 b 0 =11.

另外,為了避免等化器12(其可為DFE)可能產生的錯誤遞延(Error Propagation),接收裝置10利用序列估測器14來進行序列估測,以產生估測信號x t,n,而對數概度比計算器16可根據等化信號z n與估測信號x t,n的比對結果,產生對數概度比LLR 0~LLR L-1。具體來說,當等化信號z n與估測信號x t,n分別位於決策區域R (0)~R (M-1)中的不同決策區域時,對數概度比LLR 0~LLR L-1中至少一對數概度比LLR k為0,以避免錯誤的對數概度比被傳遞至解碼器18。也就是說,在等化信號z n位於決策區域R (0)~R (M-1)中一決策區域R (m1)且估測信號x t,n位於決策區域R (0)~R (M-1)中一決策區域R (m2)(R (m2)≠R (m1))的情況下,對數概度比LLR 0~LLR L-1中至少一對數概度比LLR k為0。 In order to avoid equalizer 12 (which may be a DFE) Deferred error (Error Propagation) may be generated, the receiving apparatus 10 using a sequence estimator 14 to estimate sequence to produce estimated signal x t, n, The log-probability ratio calculator 16 can generate a log-probability ratio LLR 0 -LLR L-1 based on the comparison of the equalization signal z n with the estimated signal x t,n . Specifically, when the equalization signal z n and the estimated signal x t,n are respectively located in different decision regions in the decision regions R (0) to R (M-1) , the logarithmic probability ratio LLR 0 to LLR L- At least one pair of odds ratios in 1 is 0 in LLR k to avoid an erroneous logarithmic probability ratio being passed to decoder 18. That is, the equalization signal z n is located in a decision region R (m1) in the decision regions R (0) - R (M-1 ) and the estimated signal x t,n is located in the decision region R (0) - R ( M-1) In the case of the first decision region R (m2) (R (m2) ≠ R (m1) ), the logarithmic generality ratio LLR 0 to LLR L-1 is at least one pair of the odds ratio LLR k is zero.

詳細來說,對任何數位調變而言,當欲解調出信號s所代表的位元b k時,整個星座平面可被分割為一二元區域R k,0以及一二元區域R k,1,且二元區域R k,0及二元區域R k,1分割整個星座平面(代表二元區域R k,0與二元區域R k,1互斥且二元區域R k,0與二元區域R k,1的聯集為整個星座平面)。二元區域R k,0代表解調出b k=0的區域,而二元區域R k,1代表解調出b k=1的區域,換句話說,若信號s位於二元區域R k,0中,則解調出信號s的位元b k為0;若信號s位於二元區域R k,1中,則解調出信號s的位元b k為1(其中二元區域R k,0以及二元區域R k,1可被視為對應於位元b k)。當等化信號z n位於二元區域R k,1且估測信號x t,n位於二元區域R k,0(或等化信號z n位於二元區域R k,0且估測信號x t,n位於二元區域R k,1)時,對數概度比計算器16輸出對數概度比LLR k為0。 In detail, for any digital modulation, when the bit b k represented by the signal s is to be demodulated, the entire constellation plane can be divided into a binary region R k,0 and a binary region R k , 1 , and the binary region R k,0 and the binary region R k,1 divide the entire constellation plane (representing the binary region R k,0 and the binary region R k,1 are mutually exclusive and the binary region R k,0 The union with the binary region R k,1 is the entire constellation plane). The binary region R k,0 represents the region where b k =0 is demodulated, and the binary region R k,1 represents the region where b k =1 is demodulated, in other words, if the signal s is located in the binary region R k , 0 , the bit b k of the demodulated signal s is 0; if the signal s is located in the binary region R k,1 , the bit b k of the demodulated signal s is 1 (where the binary region R k, 0 and the binary region R k,1 can be considered to correspond to the bit b k ). When the equalization signal z n is located in the binary region R k,1 and the estimated signal x t,n is located in the binary region R k,0 (or the equalization signal z n is located in the binary region R k,0 and the estimated signal x When t, n is located in the binary region R k,1 ), the log-probability ratio calculator 16 outputs a log-probability ratio LLR k of zero.

於一實施例中,對數概度比計算器16可根據等化信號z n與估測信號x t,n的比對結果(即判斷等化信號z n與估測信號x t,n是否位於相同的決策區域),產生一個複數信號(抹除信號),再根據抹除信號產生對數概度比。請參考第2圖,第2圖為本發明實施例一對數概度比計算器26之方塊圖。對數概度比計算器26可用來實現對數概度比計算器16,其可用於以QPSK調變的等化信號z n(代表等化信號z n可被解調成可被解調成位元b 0、b 1)。對數概度比計算器26包括一抹除單元260以及一對數概度比計算單元262;抹除單元260用來根據等化信號z n以及估測信號x t,n,產生一抹除信號q n,其中抹除信號q n可表示為q n=q n,I+j q n,Q,q n,I代表抹除信號q n的實部(以下簡稱抹除實部),q n,Q代表抹除信號q n的虛部(以下簡稱抹除虛部);對數概度比計算單元262用來根據抹除信號q n產生對數概度比LLR 0、LLR 1。於一實施例中,對數概度比計算單元262可根據QPSK於星座平面的特性,計算出對數概度比LLR 0、LLR 1分別為LLR 0=c×q n,I(公式1.1)以及LLR 1=c×q n,Q(公式1.2),其中c為一常數,常數c可正比於一信雜比(Signal-to-Noise Ratio,SNR)。 In one embodiment, the log likelihood of the equalized signal according to the estimated signal z n x t, n, than the result (i.e., judgment signal z n and the estimated signal x t, n ratio calculator 16 is located The same decision area) produces a complex signal (erase signal) and a logarithmic probability ratio based on the erase signal. Please refer to FIG. 2, which is a block diagram of a pair-to-digits ratio calculator 26 according to an embodiment of the present invention. Log likelihood ratio calculator 26 may be used to achieve the log likelihood ratio calculator 16, which may be used to signal to other z n (on behalf of the QPSK modulation signal z n, etc. can be demodulated is demodulated into bits to be b 0 , b 1 ). The log-probability ratio calculator 26 includes an erasing unit 260 and a pair-to-number ratio ratio calculating unit 262. The erasing unit 260 is configured to generate an erasing signal q n according to the equalized signal z n and the estimated signal x t, n . The erase signal q n can be expressed as q n =q n, I +jq n,Q ,q n,I represents the real part of the erase signal q n (hereinafter referred to as the erased real part), q n, Q represents the wipe In addition to the imaginary part of the signal q n (hereinafter referred to as the erased imaginary part); the log-probability ratio calculation unit 262 is used to generate a log-probability ratio LLR 0 , LLR 1 from the erase signal q n . In an embodiment, the log-probability ratio calculation unit 262 can calculate the log-probability ratios LLR 0 and LLR 1 according to the characteristics of the QPSK in the constellation plane, respectively, LLR 0 = c × q n, I (formula 1.1) and LLR. 1 = c × q n, Q (Equation 1.2), where c is a constant, and the constant c can be proportional to a Signal-to-Noise Ratio (SNR).

以QPSK信號為例,如第3圖的右上圖所示,二元區域R 0,1、R 0,0為星座平面的右、左半平面(即R 0,1可表示為R 0,1={s | Re( s) ≥0},R 0,0可表示為R 0,0={s | Re(s)<0}),如第3圖的左下圖所示,二元區域R 1,1、R 1,0為星座平面的上、下半平面(即R 1,1可表示為R 1,1={s | Im( s) ≥0},R 1,0可表示為R 1,0={s | Im (s)<0}),其中Re(·)及Im(·)分別代表取實部運算以及取虛部運算。換句話說,對QPSK信號而言,只要判斷等化信號z n及估測信號x t,n的實部大小或虛部大小,即可判斷等化信號z n及估測信號x t,n位於所在的區域。在此情形下,當等化信號z n的等化實部Re(z n)與估測信號x t,n的估測實部Re(x t,n)互為異號時(即sign(Re(z n))不等於sign(Re(x t,n)),其中sign(·)為取正負號運算,sign(·)可表示為公式2),對數概度比計算器26輸出對數概度比LLR 0為0;當等化信號z n的等化虛部Im(z n)與估測信號x t,n的估測虛部Im(x t,n)互為異號時(即sign(Im(z n))不等於sign(Im (x t,n))),對數概度比計算器26輸出對數概度比LLR 1為0。從另一個角度來說,當等化實部Re(z n)與估測實部Re(x t,n)互為異號時,抹除單元260可產生抹除實部q n,I為0,對數概度比計算單元262依據公式1.1可產生對數概度比LLR 0為0。而當等化虛部Im(z n)與估測虛部Im(x t,n)互為異號時,抹除單元260可產生抹除虛部q n,Q為0,對數概度比計算單元262依據公式1.2可產生對數概度比LLR 1為0。另一方面,當等化實部Re(z n)與估測實部Re(x t,n)互為同號時,抹除單元260可產生抹除實部q n,I為等化實部Re(z n);當等化虛部Im(z n)與估測虛部Im(x t,n)互為同號時,抹除單元260可產生抹除虛部q n,Q為等化虛部Im(z n)。 (公式2) Taking the QPSK signal as an example, as shown in the upper right diagram of FIG. 3, the binary regions R 0,1 , R 0,0 are the right and left half planes of the constellation plane (ie, R 0,1 can be expressed as R 0,1 ={s | Re( s) ≥0}, R 0,0 can be expressed as R 0,0 ={s | Re(s)<0}), as shown in the lower left diagram of Figure 3, the binary region R 1,1 , R 1,0 are the upper and lower half planes of the constellation plane (ie, R 1,1 can be expressed as R 1,1 ={s | Im( s) ≥0}, R 1,0 can be expressed as R 1,0 ={s | Im (s)<0}), where Re(·) and Im(·) represent the real part operation and the imaginary part operation, respectively. In other words, for the QPSK signal, the equalization signal z n and the estimated signal x t,n can be determined by judging the real part size or the imaginary part size of the equalization signal z n and the estimated signal x t,n . Located in the area where you are located. In this case, when the equal real part Re(z n ) of the equalization signal z n and the estimated real part Re(x t,n ) of the estimated signal x t,n are mutually different (ie, sign( Re (z n)) not equal sign (Re (x t, n )), where sign (·) for the collection of sign operation, sign (·) can be represented as formula 2), of log likelihood output calculator 26 ratio for The probability ratio LLR 0 is 0; when the equalized imaginary part Im(z n ) of the equalization signal z n and the estimated imaginary part Im(x t,n ) of the estimated signal x t,n are mutually different ( That is, sign(Im(z n )) is not equal to sign(Im (x t,n ))), and the logarithmic probability ratio calculator 26 outputs a logarithmic probability ratio LLR 1 of 0. From another point of view, when the equalized real part Re(z n ) and the estimated real part Re(x t,n ) are mutually different, the erasing unit 260 can generate the erased real part q n, I is 0, the log-probability ratio calculation unit 262 can generate a log-probability ratio LLR 0 of 0 according to the formula 1.1. When the equalized imaginary part Im(z n ) and the estimated imaginary part Im(x t,n ) are mutually different, the erasing unit 260 can generate the erased imaginary part q n , Q is 0, and the logarithmic probability ratio The calculation unit 262 can generate a log-probability ratio LLR 1 of 0 according to Equation 1.2. On the other hand, when the equal real part Re(z n ) and the estimated real part Re(x t,n ) are identical to each other, the erasing unit 260 can generate the erased real part q n, and the I is equalized. Part Re(z n ); when the equalized imaginary part Im(z n ) and the estimated imaginary part Im(x t,n ) are identical to each other, the erasing unit 260 may generate the erasing imaginary part q n, Q is Equalize the imaginary part Im(z n ). (Formula 2)

抹除單元260不限於利用特定電路結構來實現。舉例來說,請參考第4圖,第4圖為本發明實施例一抹除單元460之方塊圖,抹除單元460可用來實現抹除單元260。抹除單元460包括實部單元R1、R2、虛部單元I1、I2、正負號單元S1~S4、判斷單元D1、D2、多工器M1、M2以及結合單元CB,實部單元R1、R2分別產生等化實部Re(z n)、估測實部Re(x t,n) ,虛部單元I1、I2分別產生等化虛部Im(z n)、估測虛部Im(x t,n),正負號單元S1、S2、S3、S4分別將等化實部Re(z n)、估測實部Re(x t,n)、等化虛部Im(z n)、估測虛部Im(x t,­ n)代入公式2,以取得正負值s1、s2、s3、s4。判斷單元D1用來判斷正負值s1與正負值s2是否相等,若是,判斷單元D1控制多工器M1以輸出抹除實部q n­,I為等化實部Re(z n);若否,判斷單元D1控制多工器M1以輸出抹除實部q n­,I為0。同樣地,判斷單元D2用來判斷正負值s3與正負值s4是否相等,若是,判斷單元D2控制多工器M2以輸出抹除虛部q n,Q為等化虛部Im(z n);若否,判斷單元D2控制多工器M2以輸出抹除虛部q n,Q為0。結合單元CB輸出抹除信號q n為q n=q n,I+j q n,QThe erase unit 260 is not limited to being implemented with a specific circuit structure. For example, please refer to FIG. 4 , which is a block diagram of an erasing unit 460 according to an embodiment of the present invention. The erasing unit 460 can be used to implement the erasing unit 260 . The erasing unit 460 includes a real unit R1, R2, an imaginary unit I1, I2, a sign unit S1 to S4, a judging unit D1, D2, a multiplexer M1, M2, and a combining unit CB, and the real unit R1, R2 respectively The equalized real part Re(z n ) is generated, and the real part Re(x t,n ) is estimated, and the imaginary part units I1 and I2 respectively generate the equalized imaginary part Im(z n ) and the estimated imaginary part Im(x t, n ), the sign units S1, S2, S3, S4 will equalize the real part Re(z n ), estimate the real part Re(x t,n ), equalize the imaginary part Im(z n ), estimate the virtual The part Im(x t, n ) is substituted into the formula 2 to obtain positive and negative values s1, s2, s3, and s4. The determining unit D1 is configured to determine whether the positive/negative value s1 is equal to the positive or negative value s2. If yes, the determining unit D1 controls the multiplexer M1 to output the erased real part q n, where I is equalized real part Re(z n ); if not, The judging unit D1 controls the multiplexer M1 to output the erased real part q n, and I is 0. Similarly, the determining unit D2 is used to determine whether the positive/negative value s3 is equal to the positive or negative value s4, and if so, the determining unit D2 controls the multiplexer M2 to output the erased imaginary part q n , Q is the equalized imaginary part Im(z n ); If not, the judging unit D2 controls the multiplexer M2 to output the erasing imaginary part q n , which is 0. The combining unit CB outputs the erase signal q n as q n =q n,I +jq n,Q .

由上述可知,當等化實部Re(z n)與估測實部Re(x t,n)互為異號時,代表用來解調位元b 0的等化實部Re(z n)可能是錯誤的,因此抹除單元260/460將等化實部Re(z n)抹除,取而代之的,抹除單元260/460輸出抹除實部q n,I為0並依據公式1.1可產生對數概度比LLR 0為0。同理,當等化虛部Im(z n)與估測虛部Im(x t,n)互為異號時,代表用來解調位元b 1的等化虛部Im(z n)可能是錯誤的,因此抹除單元260/460將等化虛部Im(z n)抹除,取而代之的,抹除單元260/460輸出抹除虛部q n,Q為0並依據公式1.2可產生對數概度比LLR 1為0。簡言之,抹除單元260/460是先產生抹除信號q n再根據抹除信號q n產生對數概度比LLR 0、LLR 1From the above, when the other portions of the real Re (z n) with the estimated real part Re (x t, n) mutually different numbers, and other representatives of b bits for demodulating the real part Re 0 to (z n It may be wrong, so the erase unit 260/460 erases the equalized real part Re(z n ), and instead, the erase unit 260/460 outputs the erased real part q n , I is 0 and according to the formula 1.1 A logarithmic probability ratio LLR 0 can be generated to be 0. Similarly, when the equalized imaginary part Im(z n ) and the estimated imaginary part Im(x t,n ) are mutually different, the equalized imaginary part Im(z n ) for demodulating the bit b 1 is represented. It may be wrong, so the erasing unit 260/460 erases the equalized imaginary part Im(z n ), and the erase unit 260/460 outputs the erased imaginary part q n , Q is 0 and can be according to the formula 1.2 Generate a logarithmic probability ratio LLR 1 to zero. In short, the erasing unit 260/460 first generates the erase signal q n and then generates a logarithmic probability ratio LLR 0 , LLR 1 according to the erase signal q n .

於另一實施例中,對數概度比計算器16可根據等化信號z n先計算預先對數概度比LLR 0’~LLR L-1’,再比對等化信號z n與估測信號x t,n於星座平面上的位置,並據以決定是否要將預先對數概度比LLR 0’~LLR L-1’進行抹除,其中對預先對數概度比LLR 0’~LLR L-1’中一預先對數概度比LLR k’進行抹除代表輸出對數概度比LLR k為0(k=0,…,L-1)。請參考第5圖,第5圖為本發明實施例一對數概度比計算器56之方塊圖,對數概度比計算器56包括一對數概度比計算單元562以及一抹除單元560。對數概度比計算單元562可根據等化信號z n先計算對應於等化信號z n所代表位元b 0~b L-1的預先對數概度比LLR 0’~LLR L-1’,詳細來說,對數概度比計算單元562可套用習知計算對數概度比的公式,根據等化信號z n計算對預先數似然率LLR 0’~LLR L-1’。一般來說,預先數似然率LLR k’可表示為公式3,而針對不同的調變方式,對數概度比計算單元562可套用公式(該公式相關於照位元值組及其對應星座點於星座平面排列方式),計算預先數似然率LLR 0’~LLR L-1’。舉例來說,對M-PSK而言,預先數似然率LLR k’可表示為公式4,而對16-QAM而言,於一實施例中,預先數似然率LLR 0’可表示為公式5,其中, αβ為傳送信號, α Iβ Iα Qβ Q)為傳送信號 αβ的實部(虛部),S k (0)/ S k (1)對應b k=0/1的星座點集合,SNR為信雜比。 In another embodiment, a log likelihood ratio calculator 16 can calculate the first equalized signal z n in accordance with a pre-estimate of the degree of re-alignment of the equalized signal estimate signal z n ratio LLR 0 '~ LLR L-1 ', embodiment x t,n is the position on the constellation plane, and it is decided whether to erase the pre-logarithm probability ratio LLR 0 '~LLR L-1 ', where the pre-logarithm probability ratio LLR 0 '~LLR L- 1 'Second-first logarithmic probability is erased than LLR k ' to represent the output log-probability ratio LLR k is 0 (k=0,...,L-1). Please refer to FIG. 5. FIG. 5 is a block diagram of a one-to-seven-degree ratio calculator 56 according to an embodiment of the present invention. The log-probability ratio calculator 56 includes a pair-to-number ratio ratio calculating unit 562 and an erasing unit 560. Of log likelihood ratio calculation unit 562 may first calculate corresponds to the equalized signal z n equalized signal z n represents bit b 0 ~ b advance log likelihood ratio LLR 0 '~ LLR L-1 ' of the L-1, In detail, the log-probability ratio calculation unit 562 can apply the conventional formula for calculating the log-probability ratio, and calculate the pre-number likelihood ratios LLR 0 ' to LLR L-1 ' based on the equalization signal z n . In general, the pre-number likelihood LLR k ' can be expressed as Equation 3, and for different modulation methods, the log-probability ratio calculation unit 562 can apply a formula (this formula is related to the illuminant value group and its corresponding constellation) Calculate the pre-number likelihood LLR 0 '~LLR L-1 ' by focusing on the constellation plane arrangement). For example, for M-PSK, the pre-number likelihood LLR k ' can be expressed as Equation 4, and for 16-QAM, in an embodiment, the pre-number likelihood LLR 0 ' can be expressed as formula 5, wherein, α, β of the transmission signal, α I, β I (α Q, β Q) to transmit a signal [alpha], the real part beta] (the imaginary part), S k (0) / S k (1) corresponding to The set of constellation points with b k =0/1, SNR is the signal to noise ratio.

(公式3) (Formula 3)

(公式4) (Formula 4)

(公式5) (Equation 5)

另外,抹除單元560耦接於等化器12以及序列估測器14,用來比對等化信號z n與估測信號x t,n(比對等化信號z n與估測信號x t,n是否位於相同的決策區域),並根據等化信號z n與估測信號x t,n的比對結果,輸出對數概度比LLR k為預先對數概度比LLR k’或是0。精確來說,當抹除單元560判斷等化信號z n及估測信號x t,n其中之一信號位於對應於位元b k的二元區域R k,0而其中另一信號位於對應於位元b k的二元區域R k,1時,抹除單元560輸出對數概度比LLR k為0;而當抹除單元560判斷等化信號z n及估測信號x t,n同時位於相同的二元區域(R k,0或是R k,1)時,抹除單元560輸出對數概度比LLR k為預先對數概度比LLR k’。 In addition, the erasing unit 560 is coupled to the equalizer 12 and the sequence estimator 14 for comparing the equalized signal z n with the estimated signal x t,n (the equalizing signal z n and the estimated signal x Whether t,n is located in the same decision area), and based on the comparison result of the equalization signal z n and the estimated signal x t,n , the output logarithmic probability ratio LLR k is a pre-logarithm probability ratio LLR k 'or 0 . Specifically, when the erasing unit 560 determines that the equalization signal z n and the estimated signal x t,n one of the signals is located in the binary region R k,0 corresponding to the bit b k and the other signal is located corresponding to When the binary region R k,1 of the bit b k , the erasing unit 560 outputs a logarithmic probability ratio LLR k is 0; and when the erasing unit 560 determines that the equalized signal z n and the estimated signal x t,n are simultaneously located When the same binary region (R k, 0 or R k, 1 ) is used, the erasing unit 560 outputs a log-probability ratio LLR k which is a pre-logarithm probability ratio LLR k '.

舉例來說,請再參考第3圖(以QPSK為例),假設等化信號z n位於決策區域R (3),若估測信號x t,n位於決策區域R (1),抹除單元560輸出對數概度比LLR 0為預先對數概度比LLR 0’(LLR 0=LLR 0’)並輸出對數概度比LLR 1為0(LLR 1=0);若估測信號x t,n位於決策區域R (2),抹除單元560輸出對數概度比LLR 0為0(LLR 0=0)並輸出對數概度比LLR 1為預先對數概度比LLR 1’(LLR 1=LLR 1’);若估測信號x t,n位於決策區域R (0),抹除單元560輸出對數概度比LLR 0為0(LLR 0=0)並輸出對數概度比LLR 1為0(LLR 1=0)。 For example, please refer to Figure 3 (taking QPSK as an example), assuming that the equalization signal z n is located in the decision region R (3) , if the estimated signal x t,n is located in the decision region R (1) , the erase unit 560 output logarithmic probability ratio LLR 0 is the pre-logarithm probabilistic ratio LLR 0 '(LLR 0 = LLR 0 ') and the output log-probability ratio LLR 1 is 0 (LLR 1 =0); if the estimated signal x t,n Located in the decision area R (2) , the erasing unit 560 outputs a logarithmic probability ratio LLR 0 of 0 (LLR 0 =0) and outputs a logarithmic probability ratio LLR 1 to a pre-logarithm probability ratio LLR 1 '(LLR 1 =LLR 1 '); if the estimated signal x t,n is located in the decision region R (0) , the erasing unit 560 outputs a log-probability ratio LLR 0 of 0 (LLR 0 =0) and outputs a log-probability ratio LLR 1 of 0 (LLR) 1 =0).

請參考第6圖,第6圖為本發明實施例4-PAM的4個星座點於星座平面分佈的示意圖,4個4-PAM以及其所代表的位元值組繪示於第6圖的左上圖,其每一組位元值所對應的決策區域R (0)~R (3)繪示於於第6圖的右下圖。同樣地,位元b 0所對應的二元區域R 0,0以及二元區域R 0,1繪示於第6圖的右上圖,位元b 1所對應的二元區域R 1,0以及二元區域R 1,1繪示於第6圖的左下圖。假設等化信號z n位於決策區域R (3),若估測信號x t,n位於決策區域R (1),抹除單元560輸出對數概度比LLR 0為LLR 0’並輸出對數概度比LLR 1為0;若估測信號x t,n位於決策區域R (2),抹除單元560輸出對數概度比LLR 0為0並輸出對數概度比LLR 1為LLR 1’;若估測信號x t,n位於決策區域R (0),抹除單元560輸出對數概度比LLR 00並輸出對數概度比LLR 1為0。 Please refer to FIG. 6. FIG. 6 is a schematic diagram showing the distribution of four constellation points of the 4-PAM in the constellation plane according to the embodiment of the present invention. The four 4-PAMs and the bit value groups they represent are shown in FIG. In the upper left figure, the decision areas R (0) to R (3) corresponding to each set of bit values are shown in the lower right diagram of FIG. Similarly, the binary region R 0,0 corresponding to the bit b 0 and the binary region R 0,1 are shown in the upper right diagram of FIG. 6 , and the binary region R 1,0 corresponding to the bit b 1 and The binary region R 1,1 is shown in the lower left diagram of Fig. 6. Assuming that the equalization signal z n is located in the decision region R (3) , if the estimated signal x t,n is located in the decision region R (1) , the erasing unit 560 outputs a logarithmic probability ratio LLR 0 to LLR 0 'and outputs a logarithmic probability ratio LLR 1 is 0; if the estimated signal x t, n positioned decision region R (2), erasing unit 560 outputs a log likelihood ratio of the LLR 0 is 0 and outputs a log likelihood ratio LLR 1 as LLR 1 '; if the estimate The measurement signal x t,n is located in the decision region R (0) , and the erasing unit 560 outputs a log-probability ratio LLR 0 0 and outputs a log-probability ratio LLR 1 of zero.

請參考第7圖,第7圖為本發明實施例8-PSK的8個星座點於星座平面分佈的示意圖,8-PSK的8個星座點與其所代表的位元值組及決策區域R (0)~R (7)繪示於第7圖的左上圖,位元b 0所對應的二元區域R 0,0以及二元區域R 0,1繪示於第7圖的右上圖,位元b 1所對應的二元區域R 1,0以及二元區域R 1,1繪示於第7圖的左下圖,位元b 2所對應的二元區域R 2,0以及二元區域R 2,1繪示於第7圖的右下圖。假設等化信號z n位於決策區域R (7),而依照前述原則,估測信號x t,n位於決策區域R (0)~R (7)時,抹除單元560輸出對數概度比LLR 0~LLR 2如表I。 表I <TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> </td><td> R<sub>(0)</sub></td><td> R<sub>(1)</sub></td><td> R<sub>(2)</sub></td><td> R<sub>(3)</sub></td><td> R<sub>(4)</sub></td><td> R<sub>(5)</sub></td><td> R<sub>(6)</sub></td><td> R<sub>(7)</sub></td></tr><tr><td> LLR<sub>0</sub></td><td> 0 </td><td> LLR<sub>0</sub>’ </td><td> 0 </td><td> LLR<sub>0</sub>’ </td><td> 0 </td><td> LLR<sub>0</sub>’ </td><td> 0 </td><td> LLR<sub>0</sub>’ </td></tr><tr><td> LLR<sub>1</sub></td><td> 0 </td><td> 0 </td><td> LLR<sub>1</sub>’ </td><td> LLR<sub>1</sub>’ </td><td> 0 </td><td> 0 </td><td> LLR<sub>1</sub>’ </td><td> LLR<sub>1</sub>’ </td></tr><tr><td> LLR<sub>2</sub></td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td> LLR<sub>2</sub>’ </td><td> LLR<sub>2</sub>’ </td><td> LLR<sub>2</sub>’ </td><td> LLR<sub>2</sub>’ </td></tr></TBODY></TABLE>Please refer to FIG. 7. FIG. 7 is a schematic diagram showing the distribution of eight constellation points of the 8-PSK in the constellation plane according to the embodiment of the present invention. The eight constellation points of the 8-PSK and the bit value group and the decision region R (represented) 0) ~R (7) is shown in the upper left diagram of FIG. 7, and the binary region R 0,0 corresponding to the bit b 0 and the binary region R 0,1 are shown in the upper right diagram of FIG. 7 . The binary region R 1,0 and the binary region R 1,1 corresponding to the element b 1 are shown in the lower left diagram of FIG. 7 , and the binary region R 2,0 corresponding to the bit b 2 and the binary region R 2, 1 is shown in the lower right diagram of Figure 7. Assuming that the equalization signal z n is located in the decision region R (7) , and according to the foregoing principle, the estimation signal x t,n is located in the decision regions R (0) to R (7) , the erasing unit 560 outputs a logarithmic probability ratio LLR 0 to LLR 2 are shown in Table 1. Table I <TABLE border="1"borderColor="#000000"width="85%"><TBODY><tr><td></td><td>R<sub>(0)</sub></td><td>R<sub>(1)</sub></td><td>R<sub>(2)</sub></td><td>R<sub>(3)</sub></td><td>R<sub>(4)</sub></td><td>R<sub>(5)</sub></td><td>R<sub>(6)</sub></td><td>R<sub>(7)</sub></td></tr><tr><td>LLR<sub>0</sub></Td><td> 0 </td><td>LLR<sub>0</sub>'</td><td> 0 </td><td>LLR<sub>0</sub>'</Td><td> 0 </td><td>LLR<sub>0</sub>'</td><td> 0 </td><td>LLR<sub>0</sub>'</Td></tr><tr><td>LLR<sub>1</sub></td><td> 0 </td><td> 0 </td><td>LLR<sub>1</sub>'</td><td>LLR<sub>1</sub>'</td><td> 0 </td><td> 0 </td><td>LLR<sub>1</sub>'</td><td>LLR<sub>1</sub>'</td></tr><tr><td>LLR<sub>2</sub></td><td> 0 </td><td> 0 </td><td> 0 </td><td> 0 </td><td>LLR<sub>2</sub>'</td><td>LLR<sub>2</sub>'</td><td>LLR<sub>2</sub>'</td><td>LLR<sub>2</sub>'</td></Tr></TBODY></TABLE>

另外,對數概度比計算器16的運作可歸納成為一對數概度比產生方法80,請參考第8圖。對數概度比產生方法80可由對數概度比計算器16來執行。關於對數概度比產生方法80的細節,請參考前述相關段落,於此不再贅述。In addition, the operation of the logarithmic probability ratio calculator 16 can be summarized as a one-to-severity ratio generation method 80, please refer to FIG. The log-probability ratio generation method 80 can be performed by the log-probability ratio calculator 16. For details of the logarithmic probability ratio generation method 80, please refer to the aforementioned related paragraphs, and details are not described herein again.

另外,關於等化器12的結構,請參考第9圖,第9圖繪示本發明實施例等化器12之方塊圖。等化器12為決策反饋等化器,等化器12包括一前饋等化器(Feed Forward Equalizer,FFE)120、一決策單元122、一反饋等化器(Feedback Equalizer,FBE)124、加法器126、128以及減法器129。前饋等化器120用來根據接收信號y n+ Δ,產生一前饋輸出信號a n,前饋輸出信號a n可表示為a nf iy n+ Δ - i,其中f i代表前饋等化器120的第i個濾波器係數,Nf代表前饋等化器120的濾波器長度。決策單元122用來根據等化信號z n,產生一決策信號x h,n。反饋等化器124用來根據決策信號x h,n,產生一反饋輸出信號u n以及一部分和(Partial Sum)信號v n,反饋輸出信號u n可表示為u nb ix h,n-i,其中b i代表反饋等化器124的第i個濾波器係數,Nb代表反饋等化器124的濾波器長度。另外,部分和信號v n為反饋輸出信號u n減去第m個濾波器係數與決策信號x h,n-m的相乘結果,即v nb ix h,n-i- b mx h,n-m。加法器126用來將前饋輸出信號a n與反饋輸出信號u n相加,以產生等化信號z n為前饋輸出信號a n與反饋輸出信號u n的相加結果。加法器128用來將前饋輸出信號a n與部分和信號v n相加,以產生信號r n為前饋輸出信號a n與部分和信號v n的相加結果。等化器12將信號r n輸出至序列估測器14,序列估測器14即可根據信號r n產生估測信號x t,n。另外,減法器129計算等化信號z n與決策信號x h,n的相減結果,以產生一誤差信號e,前饋等化器120的濾波器係數f i以及反饋等化器124的濾波器係數b i皆可根據誤差信號e而調整。其餘關於等化器12及序列估測器14的運作,請參考申請人於中華民國專利申請號104128970以及中華民國專利申請號105102644所揭露的內容,於此不再贅述。 In addition, regarding the structure of the equalizer 12, please refer to FIG. 9, which shows a block diagram of the equalizer 12 of the embodiment of the present invention. The equalizer 12 is a decision feedback equalizer, and the equalizer 12 includes a feed forward equalizer (FFE) 120, a decision unit 122, a feedback equalizer (FBE) 124, and an addition. The 126, 128 and the subtractor 129. The feedforward equalizer 120 is configured to generate a feedforward output signal a n according to the received signal y n+ Δ , and the feedforward output signal a n can be expressed as a n = f i y n+ Δ - i , where f i represents the ith filter coefficient of the feedforward equalizer 120 and Nf represents the filter length of the feedforward equalizer 120. The decision unit 122 for equalized signal z n, generates a decision signal x h, n. The feedback equalizer 124 is configured to generate a feedback output signal u n and a partial (Sial) signal v n according to the decision signal x h,n , and the feedback output signal u n can be expressed as u n = b i x h,ni , where b i represents the ith filter coefficient of the feedback equalizer 124 and Nb represents the filter length of the feedback equalizer 124. In addition, the partial sum signal v n is the feedback output signal u n minus the multiplication result of the mth filter coefficient and the decision signal x h, nm , ie v n = b i x h,ni - b m x h,nm . The adder 126 to the output signal of the feedforward output and the feedback signal a n u n summed to produce an equalized signal z n is the addition result a n feedforward output signal and the feedback of the output signal u n. The adder 128 to the feedforward output signal a n v n partial signals and summed to produce the addition result signal r n is a n feedforward output signal and the portion of the signal v n. The equalizer 12 outputs a signal r n to the sequence estimator 14, sequence estimator 14 can generate estimated signal according to the signal x t r n, n. In addition, the subtracter 129 calculates the subtraction result of the equalization signal z n and the decision signal x h,n to generate an error signal e, the filter coefficient f i of the feedforward equalizer 120, and the filtering of the feedback equalizer 124. The coefficient b i can be adjusted according to the error signal e. For the operation of the equalizer 12 and the sequence estimator 14, please refer to the contents disclosed by the applicant in the Republic of China Patent Application No. 104128970 and the Republic of China Patent Application No. 105102644, and details are not described herein.

綜上所述,為了避免決策反饋等化器所造成產生錯誤遞延,本發明利用對數概度比計算器判斷等化信號以及估測信號是否位於相同的決策區域,而據以產生對數概度比,當等化信號以及估測信號位於不同決策區域時,至少一對數概度比為0。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。In summary, in order to avoid the error deferral caused by the decision feedback equalizer, the present invention uses the log-probability ratio calculator to determine whether the equalization signal and the estimated signal are located in the same decision area, thereby generating a logarithmic probability. For example, when the equalization signal and the estimated signal are located in different decision regions, at least one pair of odds ratios is zero. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧接收裝置10‧‧‧ Receiving device

12‧‧‧等化器 12‧‧‧ Equalizer

14‧‧‧序列估測器 14‧‧‧Sequence estimator

16、26、56‧‧‧對數概度比計算器 16, 26, 56‧‧‧ logarithmic ratio ratio calculator

18‧‧‧解碼器 18‧‧‧Decoder

120‧‧‧前饋等化器 120‧‧‧Feed-feed equalizer

122‧‧‧決策單元 122‧‧‧Decision unit

124‧‧‧反饋等化器 124‧‧‧Feedback equalizer

126、128‧‧‧加法器 126, 128‧‧ ‧ adder

129‧‧‧減法器 129‧‧‧Subtractor

260、460、560‧‧‧抹除單元 260, 460, 560‧‧‧ erasing unit

262、562‧‧‧對數概度比計算單元 262, 562‧‧‧ logarithmic odds ratio calculation unit

b0~b2‧‧‧位元b 0 ~b 2 ‧‧‧ bits

CB‧‧‧結合單元 CB‧‧‧ combination unit

D1、D2‧‧‧判斷單元 D1, D2‧‧‧ judgment unit

I1、I2‧‧‧虛部單元 I1, I2‧‧‧ imaginary unit

LLR0~LLRL-1‧‧‧對數概度比LLR 0 ~ LLR L-1 ‧‧‧ logarithmic odds ratio

LLR0’~LLRL-1’‧‧‧預先對數概度比LLR 0 '~LLR L-1 '‧‧‧pre-logarithm ratio

M1、M2‧‧‧多工器 M1, M2‧‧‧ multiplexer

qn,I‧‧‧抹除實部q n,I ‧‧‧Erasing the real part

qn,Q‧‧‧抹除虛部q n,Q ‧‧‧Erase the imaginary part

R1、R2‧‧‧實部單元 R1, R2‧‧‧ real unit

R(0)~R(7)‧‧‧決策區域R (0) ~ R (7) ‧ ‧ decision area

R0,0~R2,0、R0,1~R2,1‧‧‧二元區域R 0,0 to R 2,0 , R 0,1 to R 2,1 ‧‧‧ binary region

an、e、qn、rn、un、vn、xh,n、xt,n、yn+Δ、zn‧‧‧信號a n , e , q n , r n , u n , v n , x h,n , x t,n , y n+Δ , z n ‧‧‧ signals

S1~S4‧‧‧正負號單元 S1~S4‧‧‧positive unit

第1圖為本發明實施例一接收裝置之方塊圖。 第2圖為本發明實施例一對數概度比計算器之方塊圖。 第3圖繪示本發明實施例複數個星座點之示意圖。 第4圖為本發明實施例一抹除單元之方塊圖。 第5圖為本發明實施例一對數概度比計算器之方塊圖。 第6圖繪示本發明實施例複數個星座點之示意圖。 第7圖繪示本發明實施例複數個星座點之示意圖。 第8圖為本發明實施例一對數概度比產生方法之流程圖。 第9圖繪示本發明實施例一等化器之方塊圖。FIG. 1 is a block diagram of a receiving apparatus according to an embodiment of the present invention. 2 is a block diagram of a pair-to-digit ratio ratio calculator according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing a plurality of constellation points according to an embodiment of the present invention. FIG. 4 is a block diagram of an erasing unit according to an embodiment of the present invention. Figure 5 is a block diagram of a pairwise probability ratio calculator in accordance with an embodiment of the present invention. FIG. 6 is a schematic diagram showing a plurality of constellation points according to an embodiment of the present invention. FIG. 7 is a schematic diagram showing a plurality of constellation points according to an embodiment of the present invention. FIG. 8 is a flow chart of a method for generating a one-to-one ratio ratio according to an embodiment of the present invention. FIG. 9 is a block diagram of an equalizer according to an embodiment of the present invention.

Claims (17)

一種接收裝置,包括: 一等化器,用來接收一接收信號,並產生一等化信號以及一第一信號,其中該等化信號對應複數個位元,該等化信號位於複數個決策區域中一決策區域,該複數個決策區域的每一決策區域對應該複數個位元的一組位元值; 一序列估測器,耦接於該等化器,用來根據該第一信號,產生一估測信號;以及 一對數概度比計算器,耦接於該等化器以及該序列估測器,用來根據該等化信號以及該估測信號,產生對應於該複數個位元的複數個對數概度比,其中當該估測信號不位於該決策區域時,該複數個對數概度比中至少一對數概度比為0; 其中,該對數概度比計算器耦接於一解碼器,該解碼器用來根據該複數個對數概度比進行解碼。A receiving device, comprising: an equalizer for receiving a received signal, and generating an equalized signal and a first signal, wherein the equalized signal corresponds to a plurality of bits, and the equalized signal is located in a plurality of decision regions a first decision area, each decision area of the plurality of decision areas corresponds to a set of bit values of a plurality of bits; a sequence estimator coupled to the equalizer for using the first signal, Generating an estimated signal; and a pair of odds ratio calculator coupled to the equalizer and the sequence estimator for generating a plurality of bits corresponding to the equalized signal and the estimated signal a plurality of logarithmic probabilities ratio, wherein when the estimated signal is not located in the decision region, the at least one pair of odds ratios of the plurality of logarithmic probabilities are 0; wherein the logarithmic probability ratio is coupled to the calculator A decoder for decoding based on the plurality of logarithmic odds ratios. 如請求項1所述的接收裝置,其中該對數概度比計算器包括: 一抹除單元,耦接於該等化器以及該序列估測器;以及 一對數概度比計算單元,耦接於該抹除單元。The receiving device of claim 1, wherein the logarithm ratio ratio calculator comprises: an erasing unit coupled to the equalizer and the sequence estimator; and a pair-to-number ratio ratio calculating unit coupled to The erase unit. 如請求項2所述的接收裝置,其中該抹除單元根據該等化信號以及該估測信號,產生一抹除信號,該對數概度比計算單元根據該抹除信號產生該複數個對數概度比,當該估測信號不位於該決策區域時,該抹除信號的一抹除虛部或一抹除實部為0。The receiving device of claim 2, wherein the erasing unit generates an erasing signal according to the equalized signal and the estimated signal, and the logarithmic probability ratio calculating unit generates the plurality of logarithmic probabilities according to the erasing signal For example, when the estimated signal is not located in the decision area, an erased imaginary part of the erase signal or a erased real part is zero. 如請求項3所述的接收裝置,其中當該等化信號的一等化實部與該估測信號的一估測實部互為異號時,該抹除單元產生該抹除信號的該抹除實部為0;當等化信號的一等化虛部與該估測信號的一估測虛部互為異號時,該抹除單元產生該抹除信號的該抹除虛部為0。The receiving device of claim 3, wherein when the realized real part of the equalized signal and the estimated real part of the estimated signal are mutually different, the erasing unit generates the erased signal Erasing the real part to 0; when the first-order imaginary part of the equalization signal and the estimated imaginary part of the estimated signal are mutually different, the erasing unit generates the erasing imaginary part of the erasing signal as 0. 如請求項4所述的接收裝置,其中當該等化實部與該估測實部互為同號時,該抹除單元產生該抹除實部為該等化實部;當該等化虛部與該估測虛部互為同號時,該抹除單元產生該抹除虛部為該等化虛部。The receiving device of claim 4, wherein when the real part and the estimated real part are identical to each other, the erasing unit generates the erasing real part as the real part; when the equalizing When the imaginary part and the estimated imaginary part are identical to each other, the erasing unit generates the imaginary part as the imaginary part. 如請求項5所述的接收裝置,其中該抹除單元包括: 一第一實部單元,用來產生該等化實部; 一第二實部單元,用來產生該估測實部; 一第一虛部單元,用來產生該等化虛部; 一第二虛部單元,用來產生該估測虛部; 一第一正負號單元,用來產生對應於該等化實部一第一正負值; 一第二正負號單元,用來產生對應於該估測實部一第二正負值; 一第三正負號單元,用來產生對應於該等化虛部一第三正負值; 一第四正負號單元,用來產生對應於該估測虛部一第四正負值; 一第一多工器,當該第一正負值與該第二正負值不相等時,該第一多工器輸出該抹除實部為0,而當該第一正負值等於該第二正負值時,該第一多工器輸出該抹除實部為該等化實部;以及 一第二多工器,當該第三正負值與該第四正負值不相等時,該第二多工器輸出該抹除虛部為0,而當該第一正負值等於該第二正負值時,該第二多工器輸出該抹除虛部為該等化虛部。The receiving device of claim 5, wherein the erasing unit comprises: a first real unit for generating the real part; and a second real unit for generating the estimated real part; a first imaginary unit for generating the imaginary part; a second imaginary unit for generating the estimated imaginary part; a first sign unit for generating a corresponding one of the real part a positive and negative value; a second sign unit for generating a second positive and negative value corresponding to the estimated real part; a third sign unit for generating a third positive and negative value corresponding to the imaginary part; a fourth sign unit for generating a fourth positive and negative value corresponding to the estimated imaginary part; a first multiplexer, when the first positive and negative value is not equal to the second positive and negative value, the first plurality The workpiece outputs the erased real part to 0, and when the first positive and negative value is equal to the second positive and negative value, the first multiplexer outputs the erased real part as the real part; and a second When the third positive and negative value is not equal to the fourth positive and negative value, the second multiplexer outputs the erased imaginary part to 0, and When the first positive and negative value is equal to the second positive and negative value, the second multiplexer outputs the erased imaginary part as the imaginary part. 如請求項2所述的接收裝置,其中該對數概度比計算單元根據該等化信號產生對應於該複數個位元的複數個預先對數概度比,該抹除單元根據該複數個預先對數概度比輸出該複數個對數概度比,該複數個位元中一位元對應一第一二元區域以及一第二二元區域,該第一二元區域以及該第二二元區域分割一星座平面,當該等化信號區域位於該第一二元區域且該估測信號位於該第二區域時,該抹除單元輸出該複數個對數概度比中對應於該位元的一對數概度比為0。The receiving apparatus according to claim 2, wherein the logarithmic probability ratio calculating unit generates a plurality of pre-logarithm ratio ratios corresponding to the plurality of bits according to the equalization signal, the erasing unit according to the plurality of pre-logarithms The ratio is greater than the ratio of the logarithm of the plurality of bits, wherein the one bit of the plurality of bits corresponds to a first binary region and a second binary region, and the first binary region and the second binary region are divided. a constellation plane, when the equalized signal region is located in the first binary region and the estimated signal is located in the second region, the erasing unit outputs a pair of numbers corresponding to the bit in the plurality of logarithmic probabilities The probability ratio is 0. 如請求項7所述的接收裝置,其中當該估測信號位於該第一區域時,該抹除單元輸出對應於該位元的該對數概度比為該複數個預先對數概度比中對應於該位元的一預先對數概度比。The receiving device according to claim 7, wherein when the estimated signal is located in the first region, the erasing unit outputs the log-probability ratio corresponding to the bit to correspond to the plurality of pre-logarithm probabilities A pre-logarithm probabilistic ratio of the bit. 如請求項1所述的接收裝置,其中該等化器為一決策反饋等化器,其包括: 一前饋等化器,用來根據該接收信號,產生一前饋輸出信號; 一決策單元,用來根據該等化信號,產生一決策信號; 一反饋等化器,用來根據該決策信號,產生一反饋輸出信號以及一部分和信號;以及 一加法器,用來將該前饋輸出信號與該部分和信號相加,以產生該第一信號為該前饋輸出信號與該部分和信號的相加結果。The receiving device of claim 1, wherein the equalizer is a decision feedback equalizer, comprising: a feedforward equalizer for generating a feedforward output signal according to the received signal; And generating a decision signal according to the equalized signal; a feedback equalizer for generating a feedback output signal and a portion of the sum signal according to the decision signal; and an adder for outputting the feedforward signal And adding the partial sum signal to generate the first signal as an addition result of the feedforward output signal and the partial sum signal. 如請求項1所述的接收裝置,其中該序列估測器為一最大似然序列估測器。The receiving device of claim 1, wherein the sequence estimator is a maximum likelihood sequence estimator. 一種對數概度比產生方法,應用於一接收裝置的一對數概度比計算器,其中該對數概度比計算器耦接於該接收裝置的一等化器以及一序列估測器,該對數概度比產生方法包括: 自該等化器及該序列估測器接收一等化信號以及一估測信號,其中該等化器根據一接收信號產生該等化信號,該等化信號對應複數個位元,該等化信號位於複數個決策區域中一決策區域,該複數個決策區域的每一決策區域對應該複數個位元的一組位元值;以及 根據該等化信號以及該估測信號,產生對應於該複數個位元的複數個對數概度比,其中當該估測信號不位於該決策區域時,該複數個對數概度比中至少一對數概度比為0; 其中,該接收裝置的一解碼器根據該複數個對數概度比號進行解碼。A logarithmic ratio ratio generating method is applied to a pairwise ratio ratio calculator of a receiving device, wherein the logarithmic probability ratio calculator is coupled to an equalizer of the receiving device and a sequence estimator, the logarithm The method for generating an overview ratio includes: receiving an equalization signal and an estimation signal from the equalizer and the sequence estimator, wherein the equalizer generates the equalization signal according to a received signal, the equalization signal corresponding to the plurality a bit, the equalization signal is located in a decision region of the plurality of decision regions, each decision region of the plurality of decision regions corresponds to a set of bit values of the plurality of bits; and the estimated signal and the estimate Measuring a signal, generating a plurality of logarithmic probabilities ratio corresponding to the plurality of bits, wherein when the estimated signal is not located in the decision region, the at least one pair of odds ratios of the plurality of logarithmic odds ratios is 0; And a decoder of the receiving device decodes according to the plurality of log-probability ratio numbers. 如請求項11所述的對數概度比產生方法,其中根據該等化信號以及該估測信號,產生對應於該複數個位元的複數個對數概度比的步驟包括: 根據該等化信號以及該估測信號,產生一抹除信號,其中當該估測信號不位於該決策區域時,該抹除信號的一抹除虛部或一抹除實部為0;以及 根據該抹除信號產生該複數個對數概度比。The method for generating a logarithmic probability ratio according to claim 11, wherein the step of generating a plurality of logarithmic probability ratios corresponding to the plurality of bits according to the equalized signal and the estimated signal comprises: according to the equalized signal And the estimator signal, wherein an erase signal is generated, wherein when the estimated signal is not located in the decision area, an erase imaginary part or a erased real part of the erase signal is 0; and the complex number is generated according to the erase signal Logarithmic probabilities. 如請求項12所述的對數概度比產生方法,其中根據該等化信號以及該估測信號,產生該抹除信號的步驟包括: 當該等化信號的一等化實部與該估測信號的一估測實部互為異號時,產生該抹除信號的該抹除實部為0;以及 當等化信號的一等化虛部與該估測信號的一估測虛部互為異號時,產生該抹除信號的該抹除虛部為0。The method for generating a logarithmic probability ratio according to claim 12, wherein the step of generating the erase signal according to the equalization signal and the estimated signal comprises: when the equalization real part of the equalization signal and the estimation When the estimated real part of the signal is different from each other, the erased real part of the erased signal is 0; and when the equalized imaginary part of the equalized signal and an estimated imaginary part of the estimated signal are mutually When it is an alien sign, the erased imaginary part of the erase signal is 0. 如請求項13所述的對數概度比產生方法,其中根據該等化信號以及該估測信號,產生該抹除信號的步驟包括: 當該等化實部與該估測實部互為同號時,產生該抹除實部為該等化實部;以及 當該等化虛部與該估測虛部互為同號時,產生該抹除虛部為該等化虛部。The method according to claim 13, wherein the step of generating the erase signal according to the equalization signal and the estimated signal comprises: when the real part is identical to the estimated real part When the number is generated, the erased real part is the real part; and when the imaginary part is identical to the estimated imaginary part, the erased imaginary part is generated as the imaginary part. 如請求項11所述的對數概度比產生方法,其中根據該等化信號以及該估測信號,產生對應於該複數個位元的複數個對數概度比的步驟包括: 根據該等化信號,產生對應於該複數個位元的複數個預先對數概度比; 根據該複數個預先對數概度比,輸出該複數個對數概度比。The method for generating a logarithmic probability ratio according to claim 11, wherein the step of generating a plurality of logarithmic probability ratios corresponding to the plurality of bits according to the equalized signal and the estimated signal comprises: according to the equalized signal Generating a plurality of pre-logarithm probabilities ratio corresponding to the plurality of bits; and outputting the plurality of logarithmic probabilities ratio according to the plurality of pre-logarithm probabilities. 如請求項15所述的對數概度比產生方法,其中該複數個位元中一位元對應一第一二元區域以及一第二二元區域,該第一二元區域以及該第二二元區域分割一星座平面,而根據該複數個預先對數概度比,輸出該複數個對數概度比的步驟包括: 當該等化信號區域位於該第一二元區域且該估測信號位於該第二二元區域時,該複數個對數概度比中對應於該位元的一對數概度比為0。The method for generating a logarithmic probability ratio according to claim 15, wherein one bit of the plurality of bits corresponds to a first binary region and a second binary region, the first binary region and the second second The meta-region is divided into a constellation plane, and according to the plurality of pre-logarithm probabilities, the step of outputting the plurality of log-probability ratios includes: when the equalized signal region is located in the first binary region and the estimated signal is located in the In the second binary region, the ratio of the pair of numbers corresponding to the bit in the complex logarithmic probability ratio is zero. 如請求項15所述的對數概度比產生方法,其中根據該複數個預先對數概度比,輸出該複數個對數概度比的步驟包括: 當該估測信號位於該第一區域時,對應於該位元的該對數概度比為該複數個預先對數概度比中對應於該位元的一預先對數概度比。The method for generating a logarithmic probability ratio according to claim 15, wherein the step of outputting the plurality of logarithmic probability ratios according to the plurality of pre-logarithm probabilities ratio comprises: when the estimated signal is located in the first region, corresponding to The log-probability ratio for the bit is a pre-logarithm probabilities ratio corresponding to the bit in the plurality of pre-logarithm probabilities.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100266065A1 (en) * 2007-12-20 2010-10-21 Kazunari Yokomakura Radio communication system, reception device, and reception method
EP2306458A2 (en) * 2009-09-30 2011-04-06 LSI Corporation Automatic filter-reset mechanism
US20120170684A1 (en) * 2010-12-30 2012-07-05 Raymond Yim Method and System for Decoding OFDM Signals Subject to Narrowband Interference
US20130114765A1 (en) * 2011-11-08 2013-05-09 Ramesh Annavajjala Method for Reducing Interference in OFDM Wireless Networks
US8489973B1 (en) * 2010-08-02 2013-07-16 Sk Hynix Memory Solutions Inc. Numerical solution on LLR exchange in turbo equalization
US8644370B2 (en) * 2012-01-25 2014-02-04 Silicon Laboratories Providing slope values for a demapper
US20140140384A1 (en) * 2010-05-03 2014-05-22 Sk Hynix Memory Solutions Inc. Matching signal dynamic range for turbo equalization system
EP3182662A1 (en) * 2015-12-15 2017-06-21 Intel IP Corporation Soft llr/bit combining for comp or soft handover receiver

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100266065A1 (en) * 2007-12-20 2010-10-21 Kazunari Yokomakura Radio communication system, reception device, and reception method
EP2306458A2 (en) * 2009-09-30 2011-04-06 LSI Corporation Automatic filter-reset mechanism
US20140140384A1 (en) * 2010-05-03 2014-05-22 Sk Hynix Memory Solutions Inc. Matching signal dynamic range for turbo equalization system
US8489973B1 (en) * 2010-08-02 2013-07-16 Sk Hynix Memory Solutions Inc. Numerical solution on LLR exchange in turbo equalization
US20120170684A1 (en) * 2010-12-30 2012-07-05 Raymond Yim Method and System for Decoding OFDM Signals Subject to Narrowband Interference
US20130114765A1 (en) * 2011-11-08 2013-05-09 Ramesh Annavajjala Method for Reducing Interference in OFDM Wireless Networks
US8644370B2 (en) * 2012-01-25 2014-02-04 Silicon Laboratories Providing slope values for a demapper
EP3182662A1 (en) * 2015-12-15 2017-06-21 Intel IP Corporation Soft llr/bit combining for comp or soft handover receiver

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