TWI637903B - 生物感測系統 - Google Patents

生物感測系統 Download PDF

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TWI637903B
TWI637903B TW106135999A TW106135999A TWI637903B TW I637903 B TWI637903 B TW I637903B TW 106135999 A TW106135999 A TW 106135999A TW 106135999 A TW106135999 A TW 106135999A TW I637903 B TWI637903 B TW I637903B
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nanowire
gate
sensing
electrode
sensing electrode
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許鉦宗
陳志偉
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神鉦生技股份有限公司
國立交通大學
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Abstract

本發明提供一種生物感測系統，其包含一無接面奈米線場效電晶體，具有源極端、汲極端及閘極端，閘極端電性環繞一無接面矽奈米線或閘極端電性連接一無接面矽奈米帶，無接面矽奈米線的直徑小於20nm，並且無接面矽奈米帶的通道厚度小於15nm；以及一感測晶片，具有延伸閘極，延伸閘極是一電容式感測電極，並且感測晶片之感測電極連接至無接面奈米線場效電晶體之閘極端，藉由等效電路分析；對感測電極的電極面積與總感測晶片面積之面積比、氧化層厚度與感測電極之塊氧化介電膜厚度之厚度比以及無接面矽奈米線的閘極電容或無接面矽奈米帶的閘極電容與感測電極的電極電容之電容比、以及待測溶液的離子濃度進行最佳化，以獲得在感測電極及閘極端之間的最佳化電位耦合效率。

Description

生物感測系統
[相關申請案交互參照]
本發明專利申請案主張向美國智慧財產局於2016年10月19日提出申請之第62/409,931號之美國臨時申請案(Provisional Application)的優先權，其中，所揭露之內容併入本說明書作為參考。
本發明係有關一種使用延伸閘極(extended gate)及環繞式閘極矽奈米線元件(gate-all-around silicon nanowire device)的生物感測系統。
場效電晶體(Field effect transistor,FET)是藉由通過電場效應來控制電流大小的半導體元件。由於FET具有體積小、重量輕、省電特性、使用壽命長、閘極輸入阻抗高、低雜訊、熱穩定性好以及製程成熟等優點。FET的適用範圍非常廣泛，特別是在大型積體電路(large scale integrated circuit,LSI)和超大型積體電路(very large scale integrated circuit,VLSI)領域。由於奈米尺寸的場效電晶體具有非常高的電位靈敏度，所以可作為生物感測器的基本結構，並應用於生物感測領域。然而，由碳奈米管(carbon nanotube)製成的FET通道難以將碳奈米管置於適當的位置，亦難以分離具有金屬及半導體特性的碳奈米管，也不易修飾碳奈米管的表面，同時也不易製造大面積的FET通道。另一方面，採用自上而下的製程技術的矽奈米線場效電晶體會產生昂貴的製造成本，使得在生物感測應用 中所進行的每次檢測的成本太高。但是，如果採用自下而上的製程技術，則存在不易將矽奈米線置於適當位置的問題，也難以控制矽奈米線的均勻半徑，並且不易維持較佳的大面積製程的良率。此外，對於奈米線元件(奈米線FET或奈米線二極體等)的表面上之特異性方面，不易控制其表面的均勻性，使得利用奈米線FET來進行生物感測無法實現。
另外，如圖1(a)所示，在許多研究中雖然已經實現了使用感測晶片10以及金屬氧化物半導體場效電晶體12(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)來進行傳統的生物感測，但是，由於感測晶片與MOSFET之間的電耦合沒有進行最佳化處理，所以造成靈敏度太低，進而無法與ELISA或其他現有感測技術(如SPR及QCM)競爭。圖1(b)顯示傳統MOSFET的剖面圖。
有鑑於現有技術的上述缺點，如何有效地設計並最佳化延伸閘極與環繞式閘極矽奈米線元件的感測元件已成為重要課題之一。
本發明之實施例揭露一種生物感測系統，包括：一無接面奈米線場效電晶體(junctionless nanowire field-effect transistor)，包括一源極端、一汲極端及一閘極端，其中，該閘極端電性環繞一無接面閘極矽奈米線(junctionless silicon nanowire)或該閘極端電性連接一無接面矽奈米帶(gate-all-around silicon nanobelt)，該無接面矽奈米線的直徑小於20nm，並且該無接面矽奈米帶的通道厚度小於15nm；以及一感測晶片(sensing chip)，包括至少一延伸閘極(extended gate)，其中，該至少一延伸閘極是一感測電極，並且該感測晶片之該感測電極耦合至該無接面奈米線場效電晶體之該閘極端；其中，藉由一等效電路，對該感測電極的電極 面積與總感測晶片面積之面積比、一氧化層厚度與該感測電極之塊氧化介電膜厚度之厚度比以及該無接面閘極矽奈米線的閘極電容或該無接面矽奈米帶的閘極電容與該感測電極的電極電容之電容比進行最佳化，以獲得在該感測電極及該閘極端之間的最佳化電位耦合效率(optimized potential coupling efficiency)。
較佳地，該無接面奈米線場效電晶體復包含：一基板；一絕緣層，設置該基板上；以及一奈米線，設置於該絕緣層上，其中，該奈米線之一部分的材質為單晶矽、多晶矽或非晶矽，該奈米線之另一部分的材質為金屬矽化物，並且該源極端及該汲極端位於該奈米線之兩端。
較佳地，該無接面奈米線場效電晶體之該奈米線係藉由側壁間隔物製程來形成。
較佳地，該感測晶片復包括一流體井(fluid well)以及一印刷電路板(PCB)，其中，該流體井設置於該感測電極上，並且該感測電極電性連接至該印刷電路板。
較佳地，該等效電路包括該感測電極之一第一雙電層電容(electric double layer capacitor)及一雙電層電阻(electric double layer resistor)；磷酸鹽緩衝生理鹽水(Phosphate-buffered saline,PBS)之溶液電阻(solution resistor)；該感測電極之該電極電容；該無接面矽奈米線或該環繞式矽奈米帶的該閘極電容；在該感測電極外部的區域上的一第二雙電層電容；以及在該感測晶片之該感測電極與該無接面奈米線場效電晶體之該閘極端之間的寄生電容(parasitic capacitor)。
較佳地，值得注意的是，該感測晶片為拋棄式。
10‧‧‧感測晶片
12‧‧‧金屬氧化物半導體場效電晶體
20‧‧‧感測晶片
201‧‧‧流體井
202‧‧‧印刷電路板
203‧‧‧感測電極
204‧‧‧銲線
圖1(a)為使用傳統金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)之延伸閘極(extended gate)感測結構的示意圖；圖1(b)為傳統金屬氧化物半導體場效電晶體結構的剖面圖；圖2顯示微流體通道(microfluidic channel)之延伸閘極環繞式閘極矽奈米線元件(gate-all-around silicon nanowire device)的示意圖；圖3顯示本發明之無接面奈米線場效電晶體(junctionless nanowire field-effect transistor,JL nanowire FET)的剖面圖；圖4依據本發明之實施例，顯示本發明之無接面矽奈米線結構的穿透式電子顯微鏡(Transmission electron microscope,TEM)影像之剖面圖；圖5依據本發明之實施例，顯示本發明之一種包含感測電極、流體井(fluid well)及印刷電路板(PCB)之生物感測系統的剖面示意圖；圖6依據本發明之實施例，顯示本發明之感測電極及奈米線元件的等效電路示意圖；圖7(a)依據本發明之實施例，當x=1以及測試感測電極上的電荷密度(charge density,Q)時，顯示電位耦合效率(η)相對於Aratio及Cratio變化的示意圖；圖7(b)依據本發明之實施例，當x=1000以及測試感測電極上的電荷密度時，顯示電位耦合效率(η)相對於Aratio及Cratio變化的示意圖；圖7(c)依據本發明之實施例，當Cratio=1以及測試感測電極上的電荷密度時，顯示電位耦合效率(η)相對於Aratio及x變化的示意圖；圖7(d)依據本發明之實施例，當Cratio=0.01以及測試感測電極上的電荷密度時，顯示電位耦合效率(η)相對於Aratio及x變化的示意圖； 圖8(a)依據本發明之實施例，當Cratio=0.01以及測試感測電極的外部區域上的電荷密度時，顯示電位耦合效率(η)相對於Aratio及x變化的示意圖；圖8(b)依據本發明之實施例，當Cratio=1以及測試感測電極的外部區域上的電荷密度時，顯示電位耦合效率(η)相對於Aratio及x變化的示意圖；圖9(a)依據本發明之實施例，當Aratio=0.5,Cratio=0.01 and x=200並且測試感測電極上的電荷密度時，顯示閘極電位(VT)相對於磷酸鹽緩衝生理鹽水(Phosphate-buffered saline,PBS)及電荷密度(charge density,Q)變化的示意圖，以及圖9(b)依據本發明之實施例，當Aratio=0.5,Cratio=0.01 and x=200並且測試感測電極的外部區域上的電荷密度時，顯示閘極電位(VT)相對於磷酸鹽緩衝生理鹽水(Phosphate-buffered saline,PBS)及電荷密度(charge density,Q)變化的示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技術之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。本發明亦可藉由其他不同的具體實例加以施行或應用，本發明說明書中的各項細節亦可基於不同觀點與應用在不悖離本發明之精神下進行各種修飾與變更。
其中，本說明書所附圖式繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技術之人士瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應落在本發明所揭示之技術內容得能涵蓋之範圍內。
圖2顯示一延伸閘極(extended gate)環繞式閘極矽奈米線元件(gate-all-around silicon nanowire device)之示意圖，其中，包括微流體通 道(microfluidic channel)的生物感測平台(biosensing platform)。如圖2所示，右下方顯示閘極介質圍繞奈米線元件的通道之掃描電子顯微鏡(Scanning Electron Microscope,SEM)圖像，其中，延伸閘極是可拋棄式的，而昂貴的環繞式閘極矽奈米線元件(非拋棄式)則設置於一感測系統內。
以下依據本發明之較佳實施例，描述一種生物感測系統，該生物感測系統包括一無接面奈米線場效電晶體(junctionless nanowire field-effect transistor)以及一感測晶片(sensing chip)，此系統能有效地實現在無接面奈米線場效電晶體與感測晶片之間的電位耦合進行最佳化，進而能有效地提高靈敏度。
如圖3所示，無接面奈米線場效電晶體包括一源極(Source)端、一汲極(Drain)端及一閘極(Gate)端，其中，閘極端電性環繞一無接面矽奈米線(junctionless silicon nanowire)或閘極端電性連接一無接面矽奈米帶(junctionless silicon nanobelt)，值得注意的是，無接面矽奈米線的直徑小於20nm，或者無接面矽奈米帶的通道厚度小於15nm。圖4依據本發明之實施例，顯示本發明之無接面矽奈米線結構的穿透式電子顯微鏡(Transmission electron microscope,TEM)影像之剖面圖，其中，無接面矽奈米帶的通道厚度為10nm，但不限於此。
其中，無接面奈米線場效電晶體之電流與電位的關係式如下所示：
其中，△φ為由於特異性引起的閘極電位變化，Vg為閘極偏壓，k為波茲曼常數(Boltzmman constant)，T為溫度(temperature)。
再者，感測晶片可包括至少一延伸閘極(extended gate)，其中，至少一延伸閘極是一感測電極，並且感測晶片之感測電極耦合至無接面奈米線場效電晶體之閘極端。
依據本發明之較佳實施例，如圖5所示，本發明之感測晶片20復可包括一流體井201(fluid well)以及一印刷電路板202(PCB)，其中，流體井201係設置於感測電極203上，並且感測電極203可藉由銲線204(bondwire)電性連接至印刷電路板202。
圖6顯示本發明之感測電極及奈米線元件的等效電路示意圖。藉由本發明所提供的等效電路，可針對感測電極的電極面積(Apro)與總感測晶片面積(Aall)之面積比(Aratio=Apro/Aall)、一氧化層厚度(D)與感測電極之塊氧化介電膜厚度(d)之厚度比(x=D/d)以及無接面矽奈米線的閘極電容(CT)或無接面矽奈米帶的閘極電容(CT)與感測電極的電極電容(CDry(max))之電容比(Cratio=CT/CDry(max))進行最佳化，進而有效地獲得在感測電極及閘極端之間的最佳化電位耦合效率(η)(optimized potential coupling efficiency)。
依據本發明之較佳實施例，本發明之無接面奈米線場效電晶體亦可包含一基板、一絕緣層以及一奈米線，其中，絕緣層設置基板上，奈米線設置於絕緣層上，值得一提的是，奈米線之一部分的材質可為單晶矽、多晶矽或非晶矽，奈米線之另一部分的材質可為金屬矽化物，並且源極端及汲極端位於奈米線之兩端。
值得一提的是，本發明之無接面奈米線場效電晶體之奈米線可藉由側壁間隔物(sidewall spacer)製程來形成。
值得說明的是，依據本發明之較佳實施例，本發明所提出之等效電路包括感測電極之一第一雙電層電容(electric double layer capacitor)(R)及一雙電層電阻(electric double layer resistor)(C)、磷酸鹽緩 衝生理鹽水(Phosphate-buffered saline,PBS)之溶液電阻(solution resistor)(Rsolution)、感測電極之電極電容(CO)、環繞式閘極矽奈米線或環繞式矽奈米帶的閘極電容(CT)、在感測電極外部的區域上的一第二雙電層電容(Cext)、以及在感測晶片之感測電極與無接面奈米線場效電晶體之閘極端之間的寄生電容(parasitic capacitor)(CP)。
其中，在進行測試時，以四種不同型式進行測試，分別為測試感測電極上的電荷密度(charge density,Q)[type A]、測試感測電極的外部區域上的電荷密度[type B]、測試感測電極上的電荷密度並使基板接地[type C]、測試感測電極的外部區域上的電荷密度並使基板接地[type D]。
基於上述的說明，閘極電位(VT)[type A]可表示如下：
其中，
依據本發明之較佳實施例，表一顯示本發明之等效電路的相關參數及其符號。
圖7(a)依據本發明之實施例，當x=1以及測試感測電極上的電荷密度(charge density,Q)時，顯示電位耦合效率(η)相對於Aratio及Cratio變化的示意圖；圖7(b)依據本發明之實施例，當x=1000以及測試感測電極上的電荷密度時，顯示電位耦合效率(η)相對於Aratio及Cratio變化的示意圖；圖7(c)依據本發明之實施例，當Cratio=1以及測試感測電極上的電荷密度時，顯示電位耦合效率(η)相對於Aratio及x變化的示意圖；以及7(d)依據本發明之實施例，當Cratio=0.01以及測試感測電極上的電荷密度時，顯示電位耦合效率(η)相對於Aratio及x變化的示意圖。
圖8(a)依據本發明之實施例，當Cratio=0.01以及測試感測電極的外部區域上的電荷密度時，顯示電位耦合效率(η)相對於Aratio及x變化的示意圖；以及圖8(b)依據本發明之實施例，當Cratio=1以及測試感測電極的外部區域上的電荷密度時，顯示電位耦合效率(η)相對於Aratio及x變化的示意圖。
圖9(a)依據本發明之實施例，當Aratio=0.5,Cratio=0.01 and x=200並且測試感測電極上的電荷密度時，顯示閘極電位(VT)相對於磷酸鹽緩衝生理鹽水(Phosphate-buffered saline,PBS)及電荷密度(charge density,Q)變化的示意圖；以及圖9(b)依據本發明之實施例，當Aratio=0.5,Cratio=0.01 and x=200並且測試感測電極的外部區域上的電荷密度時，顯示閘極電位(VT)相對於磷酸鹽 緩衝生理鹽水(Phosphate-buffered saline,PBS)及電荷密度(charge density,Q)變化的示意圖。
綜而言之，由於感測晶片為拋棄式而環繞式閘極(無接面)矽奈米線元件(為非拋棄式)設置於生物感測系統內，所以本發明之生物感測系統可有效地降低檢測成本，同時又能有效地提升電位耦合效率。
儘管已參考本申請的許多說明性實施例描述了實施方式，但應瞭解的是，本領域技術人員能夠想到多種其他改變及實施例，這些改變及實施例將落入本公開原理的精神與範圍內。尤其是，在本公開、圖式以及所附申請專利的範圍之內，對主題結合設置的組成部分及/或設置可作出各種變化與修飾。除對組成部分及/或設置做出的變化與修飾之外，可替代的用途對本領域技術人員而言將是顯而易見的。

Claims (6)

  1. 一種生物感測系統，包括：一無接面奈米線場效電晶體(junctionless nanowire field-effect transistor)，包括一源極端、一汲極端及一閘極端，其中，該閘極端電性環繞一無接面矽奈米線(junctionless silicon nanowire)或該閘極端電性連接一無接面矽奈米帶(junctionless silicon nanobelt)，該無接面矽奈米線的直徑小於20nm，並且該無接面矽奈米帶的通道厚度小於15nm；以及一感測晶片(sensing chip)，包括至少一延伸閘極(extended gate)，其中，該至少一延伸閘極是一感測電極，並且該感測晶片之該感測電極耦合至該無接面奈米線場效電晶體之該閘極端；其中，藉由一等效電路，對該感測電極的電極面積與總感測晶片面積之面積比、一氧化層厚度與該感測電極之塊氧化介電膜厚度之厚度比以及該無接面矽奈米線的閘極電容或該無接面矽奈米帶的閘極電容與該感測電極的電極電容之電容比進行最佳化，以獲得在該感測電極及該閘極端之間的最佳化電位耦合效率(optimized potential coupling efficiency)。
  2. 如申請專利範圍第1項所述之生物感測系統，其中，該無接面奈米線場效電晶體復包含：一基板；一絕緣層，設置該基板上；一奈米線，設置於該絕緣層上，其中，該奈米線之一部分的材質為單晶矽、多晶矽或非晶矽，該奈米線之另一部分的材質為金屬矽化物，並且該源極端及該汲極端位於該奈米線之兩端。
  3. 如申請專利範圍第1項所述之生物感測系統，其中，該無接面奈米線場效電晶體之該奈米線係藉由側壁間隔物製程來形成。
  4. 如申請專利範圍第1項所述之生物感測系統，其中，該感測晶片復包括一流體井(fluid well)以及一印刷電路板(PCB)，其中，該流體井設置於該感測電極上，並且該感測電極電性連接至該印刷電路板。
  5. 如申請專利範圍第1項所述之生物感測系統，其中，該等效電路包括該感測電極之一第一雙電層電容(electric double layer capacitor)及一雙電層電阻(electric double layer resistor)；磷酸鹽緩衝生理鹽水(Phosphate-buffered saline,PBS)之溶液電阻(solution resistor)；該感測電極之該電極電容；該無接面奈米線或該環繞式矽奈米帶的該閘極電容；在該感測電極外部的區域上的一第二雙電層電容；以及在該感測晶片之該感測電極與該無接面奈米線場效電晶體之該閘極端之間的寄生電容(parasitic capacitor)。
  6. 如申請專利範圍第1項所述之生物感測系統，其中，該感測晶片為拋棄式。
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