TWI637635B - Power management control circuit and lnb circuit therefor - Google Patents

Abstract

A power management control circuit and a high frequency head circuit applying the power management control circuit, wherein the power management control circuit comprises a first segment LDO voltage regulator circuit, a DC/DC converter and a third segment LDO stable a voltage circuit, the input end of the first LDO voltage stabilizing circuit is a power input end, and the output end of the third LDO voltage stabilizing circuit is a power supply output end, the DC/DC converter includes a switching device electrically connected, A non-overlapping clock generator and a reference clock generator circuit; thereby, the LNB power supply efficiency is improved, the power consumption of the power source itself is reduced, the heat generation of the LNB is reduced, and low ripple, spurious, and stable are provided. The power supply voltage is used by the high frequency processing circuit.

Description

Power management control circuit and high frequency head circuit of application power management control circuit

The invention relates to the technical field of power supply, in particular to a power management control circuit and a high frequency head circuit for applying a power management control circuit.

Satellite communication systems, such as satellite television receiver systems, typically consist of an outdoor parabolic antenna receiving unit and an indoor receiver. The outdoor receiving unit is commonly called the high frequency processing circuit, also known as the LNB. Its function is to receive and amplify the high frequency signal emitted by the satellite, and downconvert the high frequency signal to the intermediate frequency signal. Since the outdoor unit and the indoor receiver are connected by a coaxial cable, the intermediate frequency signal is transmitted from the high frequency processing circuit to the indoor receiver through the coaxial cable, and the indoor receiver also controls the polarization control voltage and the current through the coaxial cable. The vibration frequency control audio signal is transmitted to the high frequency processing circuit, and the polarization control voltage also functions as a power supply. For example, in the popular UTELSAT system in Europe, the polarization control voltage is 13V and 18V, respectively, for receiving vertical polarization signals and level polarization signals; and whether the 13V or 18V polarization control voltage is modulated with 22KHz. The audio signal controls the frequency of the local oscillator in the high-frequency processing circuit. When the 22KHz signal is not modulated, the low-frequency signal is received using the low local oscillator frequency, and the high-frequency signal is received using the high local oscillator frequency when the 22KHz signal is modulated. It should be noted that the 13V or 18V polarization control voltage (including the 22KHz modulation signal) also acts as a power supply for the low noise amplifier and downconverter circuits in the high frequency processing circuit.

The first figure shows a schematic diagram of the channel and power supply structure of a conventional tuner circuit. The polarization control voltage is input to the inside of the LNB through the coaxial cable connection terminal 10, and is respectively printed on the input terminal of the three-terminal regulator 90 and the polarization/local oscillation control input terminal of the high-frequency processing circuit 70. 13V or 18V polarization control The voltage is stepped down and regulated by a three-terminal regulator 90 to form a stable ripple-free voltage supply to the high frequency processing circuit 70 including the low noise amplifier and downconverter for use as a supply voltage. The high-frequency processing circuit operates under this power supply condition, and the 22KHz control signal according to the polarization voltage value and the local oscillation frequency receives the corresponding polarization and band signals, is amplified and down-converted, and is output from the intermediate frequency output terminal, and passes through the DC blocking capacitor. Connect to the coaxial cable connection end 10. Therefore, the intermediate frequency signal is transmitted to the indoor receiver through the coaxial cable connection end 10, and the receiver demodulates the corresponding communication signal for the user to use.

In recent years, with the improvement of high-frequency device manufacturing technology, devices have become more refined, and the power supply voltage tends to be lower in voltage during use. In this way, the difference between the input voltage and the output voltage of the three-terminal regulator in the conventional LNB increases, resulting in an increase in power consumption on the three-terminal regulator and an increase in the amount of heat generated. Therefore, the ambient temperature during the operation of the LNB increases, causing an increase in the noise coefficient of the high-frequency processing circuit, which directly affects the sensitivity of the reception. That is to say, in the conventional LNB, since the power supply voltage of the power supply is high and the high-frequency processing circuit requires a low power supply voltage, most of the power is unnecessarily consumed on the three-terminal regulator, and the power supply efficiency is low. Causes LNB heating, affecting the receiving sensitivity.

If the three-terminal regulator in the conventional LNB is changed to a DC/DC converter, since the power supply efficiency of the DC/DC converter is high, power consumption can be effectively saved, heat generation can be reduced, and the environment during LNB operation can be reduced. temperature. However, due to the low ripple removal capability of the DC/DC converter, a portion of the 22KHz audio signal in the LNB supply circuit will be printed by the DC/DC converter to the power supply terminal of the high frequency processing circuit, affecting the high frequency processing circuit spurs. Performance reduces the receiver's signal reception quality, and the use of DC/DC variators can affect the phase noise performance of high-frequency processing circuits.

Therefore, in the patent application of the present invention, the applicant has carefully studied a power management control circuit and a high frequency head circuit using the power management control circuit to solve the above problems.

The present invention is directed to the above prior art deficiencies, and the main object thereof is to provide a power management control circuit and a high frequency head circuit for applying the power management control circuit to improve the power supply of the LNB. Efficiency, reducing the power consumption of the power supply itself, reducing the heat output of the LNB, while providing low ripple, spurious-free, stable power supply voltage for high-frequency processing circuits in the high-frequency head.

In order to achieve the above object, the present invention adopts the following technology: a power management control circuit, comprising a first segment LDO voltage regulator circuit, a DC/DC converter and a third segment LDO voltage regulator circuit, which are sequentially connected, the first The input end of the segment LDO voltage stabilizing circuit is a power input end, and the output end of the third LDO voltage stabilizing circuit is a power supply output end, the DC/DC converter includes a switching device electrically connected, and a non-overlapping clock generator And a reference clock generator circuit, wherein the switching device comprises a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first switch (S1), and a second a switch tube (S2), a third switch tube (S3), a fourth switch tube (S4), a fifth switch tube (S5), a sixth switch tube (S6), and a seventh switch tube (S7) And an eighth switch tube (S8); the power input end is connected to one end of the first switch tube (S1) and the fifth switch tube (S5), and the other end of the first switch tube (S1) is connected to the first One end of the second switch tube (S2) and one end of the first capacitor (C1), and the other end of the second switch tube (S2) is connected to the sixth switch tube (S6) and the first One end of the seven switch tube (S7) and one end of the second capacitor (C2), the other end of the sixth switch tube (S6) is connected to the other end of the fifth switch tube (S5), the third switch tube (S3) One end of the third switch (C3) and the other end of the third switch (C3) are connected to one end of the third capacitor (C3) and one end of the eighth switch (S8), The other end of the eighth switch tube (S8) is grounded, and the other end of the third switch tube (S3) is connected to one end of the fourth switch tube (S4) and connected to the other end of the first capacitor (C1). The other end of the fourth switch tube (S4) is grounded, and the other end of the second capacitor (C2) is grounded; the first switch tube (S1), the second switch tube (S2), and the third switch tube (S3) The control ends of the fourth switch tube (S4), the fifth switch tube (S5), the sixth switch tube (S6), the seventh switch tube (S7), and the eighth switch tube (S8) are respectively connected. To the switch control output of the non-overlapping clock generator, the first stage LDO regulator circuit has a polarization voltage detector, and the non-overlapping clock generator selects and controls the corresponding switch according to the output state of the polarization voltage detector State.

Further, the first switch tube (S1), the second switch tube (S2), the third switch tube (S3), the fourth switch tube (S4), the fifth switch tube (S5), and the sixth The switch tube (S6), the seventh switch tube (S7), and the eighth switch tube (S8) are field effect transistors or metal oxide semiconductor field effect transistors.

A power management control circuit includes a first stage LDO voltage regulator circuit, a DC/DC converter and a third stage LDO voltage regulator circuit, wherein the input end of the first stage LDO voltage regulator circuit is a power input terminal The output end of the third-stage LDO regulator circuit is a power supply output terminal, and the DC/DC converter includes a switching device electrically connected, a non-overlapping clock generator, a reference clock generator circuit, and a high frequency processing The synchronous reference clock output used by the circuit, wherein the switching device comprises a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first switch (S1), and a second a switch tube (S2), a third switch tube (S3), a fourth switch tube (S4), a fifth switch tube (S5), a sixth switch tube (S6), and a seventh switch tube (S7) And an eighth switch tube (S8); the power input end is connected to one end of the first switch tube (S1) and the fifth switch tube (S5), and the other end of the first switch tube (S1) is connected to the second switch One end of the tube (S2) and one end of the first capacitor (C1), and the other end of the second switch tube (S2) is connected to the sixth switch tube (S6) and the seventh open One end of the switch (S7) and one end of the second capacitor (C2), the other end of the sixth switch (S6) is connected to the other end of the fifth switch (S5), the third switch (S3) One end and one end of the third capacitor (C3), the other end of the seventh switch tube (S7) is connected to the other end of the third capacitor (C3) and one end of the eighth switch tube (S8), the first The other end of the eighth switch tube (S8) is grounded, and the other end of the third switch tube (S3) is connected to one end of the fourth switch tube (S4) and connected to the other end of the first capacitor (C1). The other end of the fourth switch tube (S4) is grounded, and the other end of the second capacitor (C2) is grounded; the first switch tube (S1), the second switch tube (S2), the third switch tube (S3), The control ends of the fourth switch tube (S4), the fifth switch tube (S5), the sixth switch tube (S6), the seventh switch tube (S7), and the eighth switch tube (S8) are respectively connected to a switch control output of the non-overlapping clock generator, the first stage LDO regulator circuit has a polarization voltage detector, and the non-overlapping clock generator selects and controls a corresponding switch operation according to an output state of the polarization voltage detector .

Further, the first switch tube (S1), the second switch tube (S2), the third switch tube (S3), the fourth switch tube (S4), the fifth switch tube (S5), and the sixth The switch tube (S6), the seventh switch tube (S7), and the eighth switch tube (S8) are field effect transistors or metal oxide semiconductor field effect transistors.

Further, comprising at least two of the foregoing first stage LDO voltage stabilizing circuits, one of the foregoing DC/DC converters, and one of the foregoing third stage LDO voltage stabilizing circuits, wherein the output ends of all the first stage LDO voltage stabilizing circuits are respectively connected through respective connecting elements At a common end, the common terminal is coupled to the input of the DC/DC converter.

Further, the connecting element is a diode (D1) or a switching tube (S0).

A high frequency head circuit applying the foregoing power management control circuit further comprises a coaxial cable connection end, an intermediate frequency signal output transmission line, a DC blocking capacitor, a polarization and local oscillator control signal transmission line, and a power management control circuit power supply input a power supply output line, a high frequency processing circuit and a clock signal transmission line; the coaxial cable connection end is connected to a DC/DC converter of the power management control circuit via the power supply control input line of the power management control circuit The coaxial cable connection end is connected to the high frequency processing circuit via the polarization and local oscillator control signal transmission line, and the high frequency processing circuit is connected to the coaxial cable connection end via the intermediate frequency signal output transmission line, and the DC blocking capacitor is connected to the coaxial cable connection end. The power supply output end of the power management control circuit is connected to the high frequency processing circuit via the power management output circuit power supply output line, and the clock control circuit of the power management control circuit is connected to the high frequency processing circuit via the clock signal transmission line.

Further, comprising at least two of the foregoing coaxial cable connection ends, a power management control circuit, and a high frequency processing circuit, each of the coaxial cable connection ends outputting a transmission line, the DC blocking capacitor, and the polarization through respective intermediate frequency signals. The local oscillator control signal transmission line is connected to the high frequency processing circuit, and each coaxial cable connection end is connected to the DC/DC converter of the power management control circuit through a power supply input line of the respective power management control circuit.

According to the above technical features, the following effects can be achieved: Through reasonable design of the power management control circuit structure, the power supply efficiency of the LNB can be greatly improved, the power consumption of the power supply itself can be reduced, the heat generation of the LNB can be further reduced, and the ambient temperature during operation can be reduced, so that the noise coefficient of the receiving channel is reduced and improved. Receive sensitivity, while providing low ripple, no stray, stable supply voltage for high frequency processing circuits.

(10)‧‧‧Coaxial cable connection

(101)‧‧‧First coaxial cable connection

(102)‧‧‧Second coaxial cable connection

(20)‧‧‧Intermediate frequency signal output transmission line

(201)‧‧‧First IF signal output transmission line

(202)‧‧‧Second IF signal output transmission line

(30) ‧‧ ‧Polarization and local oscillator control signal transmission line

(301)‧‧‧First polarization and local oscillator control signal transmission line

(302)‧‧‧Second polarization and local oscillator control signal transmission line

(40)‧‧‧Power management control circuit power supply input line

(401)‧‧‧First power management control circuit power supply input line

(402)‧‧‧Second power management control circuit power supply input line

(50)‧‧‧Power management control circuit power supply output line

(60)‧‧‧Power Management Control Circuit

(600)‧‧‧The first stage LDO regulator circuit

(601)‧‧‧Polarization voltage detector

(610)‧‧‧DC/DC converter

(6100)‧‧‧Switching device

(6120)‧‧‧ Non-overlapping clock generators

(6130)‧‧‧Reference clock generator

(620)‧‧‧The third stage LDO regulator circuit

(70)‧‧‧High frequency processing circuit

(80)‧‧‧clock signal transmission line

(90)‧‧‧Three-terminal regulator

(90)‧‧‧Three-terminal regulator

(S1)‧‧‧First switch tube

(S2)‧‧‧Second switch

(S3)‧‧‧ Third switch tube

(S4)‧‧‧fourth switch

(S5) ‧‧‧ fifth switch tube

(S6) ‧‧‧ sixth switch tube

(S7)‧‧‧ seventh switch tube

(S8) ‧‧‧ eighth switch tube

(C1)‧‧‧First Capacitor

(C2)‧‧‧second capacitor

(C3)‧‧‧ Third Capacitor

(D1) ‧ ‧ diode

(S0)‧‧‧Switch tube

[The first picture] is a schematic diagram of the channel and power supply structure of the conventional high frequency head circuit.

[Second Picture] is a schematic diagram of a channel and a power supply structure of a high frequency head circuit to which a single channel power supply management control circuit is applied in the first embodiment of the present invention.

[Third Diagram] is a schematic structural diagram of a single-channel power management control circuit in the second figure.

[Fourth Diagram] is a schematic diagram of a channel and a power supply structure of a tuner circuit to which another single-channel power supply management control circuit is applied in the first embodiment of the present invention.

[Fifth] is a schematic structural diagram of a single-channel power management control circuit in the fourth figure.

[Sixth Diagram] is a schematic structural view of an embodiment of a switching device in the fourth figure.

[Seventh figure] is another schematic structural diagram of the single-channel power management control circuit in the fourth figure.

[Eighth Diagram] is a schematic structural view of another embodiment of the switching device in the fourth figure.

[9th] is a second embodiment of the present invention, which is a schematic structural view of an embodiment in which a power management control circuit uses a multi-channel input.

[Tenth Graph] is a second embodiment of the present invention, which is a schematic structural diagram of another embodiment in which a power management control circuit uses multi-channel input.

[11th] is a schematic diagram of the channel and power supply structure of the LNB of the multi-channel power management control circuit in the second embodiment of the present invention.

In summary of the above technical features, the main functions of the power management control circuit of the present invention and the high frequency head circuit of the application power management control circuit will be clearly shown in the following embodiments.

The invention is further described below in conjunction with the drawings and specific embodiments.

In the following description, the same elements in different embodiments and different structures are denoted by the same reference numerals to make the description easier to understand. Referring to the second to eleventh drawings, one of the present inventions is shown. A plurality of specific configurations of an embodiment, and various specific structures of a second embodiment.

Referring to the second figure, in the first embodiment, a schematic diagram of a channel and a power supply structure of a high-frequency head circuit using a single-channel power management control circuit (60) includes a coaxial cable connection end (10) and an intermediate frequency signal. Output transmission line (20), a DC blocking capacitor, a polarization and local oscillator control signal transmission line (30), a power management control circuit power supply input line (40), a power management control circuit power supply output line (50), a high The frequency processing circuit (70) and a power management control circuit (60) are shown in the fourth figure. In the first embodiment, the channel of the tuner circuit of another single-channel power management control circuit (60) is applied. A schematic diagram of the power supply structure, which is substantially the same as the second figure, except that it further includes a clock signal transmission line (80).

Referring to the second and fourth figures, the coaxial cable connection end (10) is connected to a DC/DC converter of the power management control circuit (60) via the power management control circuit power supply input line (40). The coaxial cable connection end (10) is connected to the high frequency processing circuit (70) via the polarization and local oscillation control signal transmission line (30), and the high frequency processing circuit (70) outputs the transmission line (20) via the intermediate frequency signal, The DC blocking capacitor is connected to the coaxial cable connection end (10), and the power supply output end of the power management control circuit (60) is connected to the high frequency processing circuit (70) via the power management control circuit power supply output line (50); In the fourth figure, the clock control circuit of the power management control circuit (60) is connected to the high frequency processing circuit (70) via the clock signal transmission line (80).

Referring to the second and third figures, the third figure is a schematic structural diagram of the single-channel power management control circuit (60) in the first embodiment. In the high frequency head circuit of the foregoing single channel power management control circuit (60), the power management control circuit (60) includes a first stage LDO voltage regulator circuit (600) and a DC/DC converter ( 610) and a third-stage LDO regulator circuit (620), the input end of the first-stage LDO regulator circuit (600) is a power input end, and the output end of the third-stage LDO regulator circuit (620) is powered An output terminal; the DC/DC converter (610) includes a switching device (6100) electrically connected, a non-overlapping clock generator (6120), and a reference clock generator (6130) circuit, the switching device (6100) The operational state is controlled by the output signal of the non-overlapping clock generator (6120), and the input signal of the non-overlapping clock signal generator (6120) is generated and provided by the reference clock generator (6130).

The voltage from the power management input line (40) of the power management control circuit is set by the indoor receiver to modulate the polarized wave and frequency band modulated according to the signal received. For example, in the European UTELSAT system, the voltage of the vertically polarized wave is 13V, and the voltage of the horizontally polarized wave is 18V. When the low frequency band local oscillator is required, the 22KHz audio signal is not modulated in the polarization voltage, and the high frequency local oscillator is required. In the polarization voltage, a 22KHz audio pulse signal with an amplitude of 0.8Vpp is modulated.

The power management control circuit (60) must first suppress the audio modulation signal in order to output a stable DC voltage for use by the high frequency processing circuit (70), and the output voltage must be maintained regardless of whether the input voltage value is 13V or 18V. constant. The first stage LDO regulator circuit (600) of the power management control circuit (60) is configured to operate in the form of a linear regulator to remove such a 22KHz audio signal, and the output is relatively stable. DC voltage of about 10V.

In order to reduce the power consumption of the power supply, the voltage outputted by the first stage LDO regulator circuit (600) is applied to the input terminal of the DC/DC converter (610), and the DC voltage is passed through the DC/DC converter (610). Reduce and improve the power supply efficiency of the power supply. The principle that the DC/DC converter (610) improves the power supply efficiency of the power supply is well known in the art, and a detailed description is omitted here. The DC/DC converter (610) may be of a configuration using an inductor or a configuration of a switched capacitor without using an inductor. No matter which structure is used Because the DC/DC converter (610) must switch on a large current and generate a large ripple signal at the output, so set a bypass capacitor after the DC/DC converter (610). While not shown in the middle, the third-stage LDO regulator circuit (620) suppresses the ripple caused by the switching current, and simultaneously performs the 22KHz audio signal that cannot be completely suppressed by the first-stage LDO regulator circuit (600). Again, the ripple of the voltage output from the third stage LDO regulator circuit (620), the switching noise generated by the DC/DC converter (610), and the spur of the 22 KHz audio signal can be sufficiently low. The level allows the high frequency processing circuit (70) to operate normally.

It must be emphasized that the DC/DC converter (610) is realized by switching a large current, except that a ripple signal of a large clock signal appears at its output end, so the third stage is passed. The LDO regulator circuit (620) stabilizes the output voltage of the DC/DC converter (610) again, thereby greatly improving the power supply efficiency of the power supply, reducing power consumption, reducing the ambient temperature during the operation of the device, and reducing the noise coefficient. When the receiving sensitivity is improved, the spur caused by the audio signal of the local oscillator frequency can be effectively eliminated, and the high frequency processing circuit (70) can be effectively prevented from being affected by the use of the DC/DC converter (610). Phase noise performance.

Referring to the fourth and fifth figures, the fifth figure is a schematic structural diagram of the other single-channel power management control circuit (60) in the first embodiment. In the high frequency head circuit of the other single channel power management control circuit (60), the power management control circuit (60) includes a first segment LDO circuit (600) and a DC/DC converter ( 610) and a third-stage LDO regulator circuit (620), the input end of the first-stage LDO circuit (600) is a power input end, and the output end of the third-stage LDO voltage stabilization circuit (620) is a power supply output end The DC/DC converter (610) includes a switching device (6100) electrically connected, a non-overlapping clock generator (6120), a reference clock generator (6130) circuit, and the high frequency processing circuit ( 70) Using the synchronous reference clock output, the operating state of the switching device (6100) is controlled by the output signal of the non-overlapping clock generator (6120), and the input signal of the non-overlapping clock signal generator (6120) is used by the reference clock generator (6130) generated and provided, at the same time, the reference clock is sent The generator (6130) also outputs a synchronous clock signal to the high frequency processing circuit (70) via the synchronous clock signal transmission line (80) for use as a reference clock of the frequency trace for use in the DC/DC converter (610) The first clock signal is synchronized with the second clock signal used by the high frequency processing circuit (70).

Referring to the second to fifth figures, the fourth figure differs from the second figure in whether or not the synchronous clock output is output for use by the high frequency processing circuit (70), and the same principle of operation is here. Do not repeat the description. It must be emphasized that the DC/DC converter (610) is realized by switching a large current, and the switching signal is high except for the problem that a large clock signal ripple signal appears at its output end. The subharmonics also radiate into the air, affecting the performance of the high frequency processing circuit (70) through air coupling. Particularly when the clock frequency is unstable or the first clock signal is not synchronized with the second clock signal in the high frequency processing circuit (70), the first clock signal output by the DC/DC converter (610) The ripple signal and the higher harmonic signal will be diverged in the high frequency processing circuit (70), and the phase noise of the phase locked loop and the high frequency voltage controlled oscillator in the high frequency processing circuit (70) Has a serious impact. Therefore, the first clock signal used in the DC/DC converter (610) is synchronized with the second clock signal used by the tuner (70) so that the switching signal does not diverge in the receiving channel to form phase noise. Moreover, the output voltage of the DC/DC converter (610) is again regulated by the third-stage LDO regulator circuit (620), thereby greatly improving the power supply efficiency of the power supply, reducing power consumption, and reducing device operation. The ambient temperature reduces the noise coefficient and improves the receiving sensitivity. At the same time, it can effectively eliminate the spur caused by the audio signal of the local oscillator frequency, and effectively prevent the influence of the DC/DC converter (610). Phase noise performance of the high frequency processing circuit (70).

Referring to the fifth and sixth figures, in the first embodiment, the switching device (6100) includes a first capacitor (C1), a second capacitor (C2), a first switching transistor (S1), A second switch tube (S2), a third switch tube (S3) and a fourth switch tube (S4) are used to implement step-down and improve power supply efficiency. The structure of the circuit is: the power input end is connected to one end of the first switch tube (S1), and the other end of the first switch tube (S1) is connected to one end of the second switch tube (S2) and the first capacitor ( One end of C1), the second switch The other end of the third switch tube (S3) is connected to one end of the third switch tube (S3) and one end of the second capacitor (C2), and the other end of the third switch tube (S3) is connected to the fourth switch tube (S4). One end and the other end of the first capacitor (C1), the other end of the fourth switch tube (S4) is grounded; the other end of the second capacitor (C2) is grounded; the first switch tube (S1), the second switch The control terminals of the tube (S2), the third switch tube (S3), and the fourth switch tube (S4) are respectively connected to respective switch control outputs of the non-overlapping clock generator (6120). In the first embodiment, the control end of the first switch tube (S1) is in phase with the control signal of the control end of the third switch tube (S3), and the second switch tube (S2) control end and the fourth switch tube (S4) The control signal of the control terminal is in phase; the output of the DC/DC converter (610) is led out by the non-ground terminal of the second capacitor (C2).

The operation principle of the DC/DC converter (610) is as follows: The control rule of the non-overlapping clock generator (6120) is: when the first switch tube (S1) and the third switch tube (S3) are turned on, The second switch tube (S2) and the fourth switch tube (S4) are turned off; when the second switch tube (S2) and the fourth switch tube (S4) are turned on, the first switch tube (S1) and the first The three switch tubes (S3) are turned off; when the first switch tube (S1) and the third switch tube (S3) are turned on and the second switch tube (S2) and the fourth switch tube (S4) are turned off, the input is The voltage of the first capacitor (C1) and the second capacitor (C2) are serially charged through the first switch tube (S1) and the third switch tube (S3), when the first capacitor (C1) capacitance When the capacitance of the second capacitor (C2) is equal to, the voltage difference between the charged first capacitor (C1) and the second capacitor (C2) is about half of the input voltage; at the first switch When the tube (S1) and the third switch tube (S3) are turned off and the second switch tube (S2) and the fourth switch tube (S4) are turned on, the amount of electricity saved on the first capacitor (C1) passes through the second The switch tube (S2) and the second capacitor (C2) are supplied to the output side by side At this time, the first switching transistor (S1) has no current flowing. When the circuit is stably operated, the discharge amount of the first capacitor (C1) and the second capacitor (C2) is equal to the charge amount of the first capacitor (C1) and the second capacitor (C2), that is, charged The current is equal to the current discharged. Since the current discharged by the first capacitor (C1) and the second capacitor (C2) is the load current, the charging current of the first capacitor (C1) and the second capacitor (C2) is also equal to the load current. And the charge and discharge duty ratio of the first capacitor (C1) and the second capacitor (C2) Each is 50%, so the average current at the input is half the average current at the output. In other words, the power supply efficiency of the power supply has doubled.

In the circuit, the first switch tube (S1), the second switch tube (S2), the third switch tube (S3) and the fourth switch tube (S4) are field effect transistors or metal oxide semiconductor fields. The effect transistor can be appropriately set according to the characteristics of another switching transistor (not shown). The advantage of this circuit is that it can achieve buck and improve power efficiency without using any inductive components.

As shown in the seventh and eighth figures, wherein the seventh figure is another structural diagram of the other single-channel power management control circuit (60) in the first embodiment. The eighth figure is a schematic structural view of another embodiment of the switching device (6100) of the other single-channel power management control circuit (60) in the first embodiment. The switching device (6100) includes a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first switching transistor (S1), a second switching transistor (S2), a third switch tube (S3), a fourth switch tube (S4), a fifth switch tube (S5), a sixth switch tube (S6), a seventh switch tube (S7), and an eighth switch tube (S8), used to achieve step-down and improve power supply efficiency. The structure of the circuit is: the power input end is connected to one end of the first switch tube (S1) and the fifth switch tube (S5), and the other end of the first switch tube (S1) is connected to the second switch tube (S2) One end and one end of the first capacitor (C1), and the other end of the second switch tube (S2) is connected to one end of the sixth switch tube (S6) and the seventh switch tube (S7) and the second capacitor (C2) One end of the sixth switch tube (S6) is connected to the other end of the fifth switch tube (S5), one end of the third switch tube (S3), and one end of the third capacitor (C3). The other end of the seventh switch (S7) is connected to the other end of the third capacitor (C3) and one end of the eighth switch (S8), and the other end of the eighth switch (S8) is grounded, the third The other end of the switch tube (S3) is connected to one end of the fourth switch tube (S4), and is connected to the other end of the first capacitor (C1), and the other end of the fourth switch tube (S4) is grounded. The other end of the second capacitor (C2) is grounded; the first switch tube (S1), the second switch tube (S2), the third switch tube (S3), the fourth switch tube (S4), and the fifth switch tube (S5), the sixth switch tube (S6), the seventh The control terminals of the switch tube (S7) and the eighth switch tube (S8) are respectively connected to the non-overlapping clock generator (6120) Corresponding output end, the first stage LDO regulator circuit (600) has a polarization voltage detector (601), and the non-overlapping clock generator (6120) is selectively controlled according to the output state of the polarization voltage detector (601) The corresponding switch action state.

When the polarization voltage is 13V, the first switch tube (S1) to the fourth switch tube (S4) are in an off state. At this time, the fifth switch tube (S5) control end and the seventh switch tube (S7) The control signal of the control end is in phase, the control end of the sixth switch tube (S6) is in phase with the control signal of the control end of the eighth switch tube (S8); and when the polarization voltage is 18V, the fifth switch tube (S5) Is in an off state, at this time, the control terminal signals of the first switch tube (S1), the third switch tube (S3) and the seventh switch tube (S7) have the same phase, and the second switch tube (S2) The signals of the control terminals of the fourth switch tube (S4), the sixth switch tube (S6) and the eighth switch tube (S8) are all the same. The output of the DC/DC converter (610) is taken out by the non-ground terminal of the second capacitor (C2); the principle of operation here is as follows: The control rule of the non-overlapping clock generator (6120) in the circuit is: 1. When the polarization voltage detector (601) detects that the polarization voltage is a low voltage, such as 13V, when the fifth switch tube (S5) and the seventh switch tube (S7) are turned on, the sixth switch tube (S6) and the eighth switch tube (S8) are turned off; when the fifth switch tube (S5) and the seventh switch tube (S7) are turned off, the sixth switch tube (S6) and the eighth switch tube (S8) conducting; 2. when the polarization voltage detector (601) detects that the polarization voltage is a high voltage, such as 18V, the first switching transistor (S1), the third switching transistor (S3), and the first When the seven switch tube (S7) is turned on, the second switch tube (S2), the fourth switch tube (S4), the sixth switch tube (S6), and the eighth switch tube (S8) are turned off; When the switch tube (S1), the third switch tube (S3), and the seventh switch tube (S7) are turned off, the second switch tube (S2), the fourth switch tube (S4), and the sixth switch tube (S6) and the eighth switch (S8) are turned on.

When the polarization voltage detector (601) detects that the polarization voltage is a low voltage, such as 13V, the operation principle of the DC/DC converter is the same as that of the fourth figure. As a result, the power supply efficiency of the power supply is increased by one. Times. When the polarization voltage detector (601) detects that the polarization voltage is a high voltage, such as 18V, the fifth switch tube (S5) is normally turned off, at this time, in the first switch tube (S1), the Third open The closing pipe (S3), the seventh switching pipe (S7) is turned on, the second switching pipe (S2), the fourth switching pipe (S4), the sixth switching pipe (S6), and the eighth switching pipe (S8) When the voltage is off, the input voltage passes through the first switch (S1), the third switch (S3), and the seventh switch (S7) to the first capacitor (C1) and the third capacitor (C3). And charging the second capacitor (C2) in series, when the capacitances of the first capacitor (C1), the third capacitor (C3), and the second capacitor (C2) are the same, the first capacitor after charging ( C1), the voltage difference between the third capacitor (C3) and the second capacitor (C2) is about 1/3 of the input voltage; in the first switch tube (S1), the third switch tube (S3) and the seventh switch tube (S7) are turned off, and the second switch tube (S2), the fourth switch tube (S4), the sixth switch tube (S6), and the eighth switch tube (S8) are turned on. The amount of electricity saved on the first capacitor (C1) and the amount of electricity saved on the third capacitor (C3) pass through the second switch (S2) and the sixth switch (S6), respectively, and the second capacitor ( C2) Parallelly supplying power to the output terminal, that is, the first switch tube (S1) and the fifth switch tube (S5) No current is passed. When the circuit is stable, the discharge amount of the first capacitor (C1), the third capacitor (C3), and the second capacitor (C2) is equal to the first capacitor (C1), the third capacitor (C3), and the The amount of charge of the second capacitor (C2), that is, the current charged is equal to 2/3 of the current discharged. The first capacitor (C1), the third capacitor (C3), and the second capacitor The charging current of the second capacitor (C2) is also equal to 2/3 of the load current. Since the charge and discharge duty ratios of the first capacitor (C1), the third capacitor (C3), and the second capacitor (C2) are each 50%, the average current at the input terminal is 1/3 of the average current of the output terminal. . In other words, the power supply efficiency of the power supply has been increased by two times.

The power management control circuit (60) of the DC/DC converter (610) is used, since the polarization voltage detector (601) is chased in the first stage LDO regulator circuit (600), according to the polarization The voltage level selects the corresponding switching tube action state, which doubles the efficiency of the low polarization voltage and doubles the efficiency when the high polarization voltage is used, which greatly reduces the power consumption of the LNB and lowers the operating environment temperature of the LNB. Low power consumption and high receiving sensitivity.

The first switch tube (S1), the second switch tube (S2), the third switch tube (S3), the fourth switch tube (S4), and the fifth switch tube (S5) described in this circuit The sixth switch tube (S6), the seventh switch (S7) tube and the eighth switch tube (S8) are field effect transistors or metal oxide semiconductor field effect transistors, and the control voltage is high and low. It can be appropriately set according to the characteristics of another switch tube (not shown). The advantage of this circuit is that it can achieve step-down and greater power efficiency without using any inductive components.

Referring to the ninth to eleventh drawings, and referring to the fourth figure, wherein the ninth embodiment is a second embodiment of the present invention, the power management control circuit (60) uses a multi-channel input FIG. 10 is a schematic structural diagram of another embodiment of the power management control circuit (60) using multi-channel input in the second embodiment; and FIG. 11 is the second embodiment. The schematic diagram of the channel and power supply structure of the LNB of the multi-channel power management control circuit.

The power management control circuit (60) is expanded for use on a multi-channel (multi-channel) output LNB, including at least two of the aforementioned first-stage LDO regulator circuits (600), one of the aforementioned DC/DC converters (610), and a third stage LDO voltage stabilizing circuit (620), here, two first-stage LDO voltage stabilizing circuits (600) are listed, which are respectively a first segment LDO1 and a first segment LDO2; all the first segments The output terminals of the LDO regulator circuit (600) are respectively connected to a common terminal through respective connection elements, and the common terminal is connected to the input terminal of the DC/DC converter (610), and the output of the DC/DC converter (610) is output. The terminals are respectively connected to the input terminals of the third-stage LDO regulator circuit (620); it should be noted that the principle is the same as that of the single-channel (single-channel) power management control circuit (60). Since any one of the multi-output LNBs is powered, the path in the high-frequency processing circuit (70) must have a corresponding polarization and an intermediate frequency signal output corresponding to the local oscillator frequency. Such a function can be realized by the first multi-channel LDO connected by the connecting component. In this embodiment, the connecting component can be a diode (D1) or a switching transistor (S0); when the connecting component is a diode In the body (D1), as shown in the ninth figure, for the first stage LDO regulator circuit (600) However, the first stage of the LDO regulator circuit (600) of the other circuit has no power supply state, because the direction of the diode (D1) is non-conducting, the current reflow phenomenon can be avoided.

When the connecting element is a switching tube (S0), as shown in the tenth figure, the configuration of this circuit is different from the ninth figure in that: 1. The switching tube (S0) is used instead of the diode (D1). 2, the first segment of the LDO voltage regulator circuit (600) is configured with an input power supply detector (not shown), and the result of the detection is used to control the action of the switch tube (S0), that is, When the first LDO regulator circuit (600) of a certain path detects that a normal voltage is applied to the input terminal, the detector outputs a signal to turn on the switch (S0) behind it. Otherwise, no normal detection is detected. The first stage of the LDO voltage regulator circuit (600) of the input voltage, the output of the detector is such that the switch tube (S0) behind it is in the off state.

Such a configuration is advantageous in that the on-resistance of the switching transistor (S0) of the same area is smaller than the forward conduction resistance of the diode (D1), and the output of the first-stage LDO regulator circuit (600) can be lowered. The voltage drop when the voltages are connected to each other increases the efficiency of the power supply, and the operation principle of the structure is the same as that of the ninth figure.

Of course, the third stage LDO regulator circuit (620) of the multi-channel power management control circuit (60) can also be connected to multiple third-stage LDO regulators according to the needs of the multi-output high-frequency processing circuit (70). The circuit (620) is separately supplied to the multi-channel high frequency processing circuit (70). The principle and nature are the same as those in the ninth figure. This circuit configuration is characterized by simple and efficient implementation of multiple co-powered and no reflow functions.

Referring to FIG. 11 , in the second embodiment, at least two of the aforementioned coaxial cable connection ends (10), one of the foregoing power management control circuits (60), and one of the foregoing high frequency processing circuits (70) are included. The coaxial cable connection end (10) is connected to a high frequency processing circuit (70) through a respective intermediate frequency signal output transmission line (50), a DC blocking capacitor, a polarization and a local oscillation control signal transmission line (30), Each coaxial cable connection end (10) is connected to a DC/DC converter of the power management control circuit (60) through a respective power management control circuit power supply input line (40); in this embodiment, two The coaxial cable connection end (10), a power management control circuit (60), and a dual-output high-frequency processing circuit (70), wherein the two coaxial cable connection ends (10) are a first coaxial cable connection end (101) and a second coaxial cable connection end (102); the first coaxial cable connection end (101) respectively a power supply input line (401) and a first polarization and local oscillation control signal transmission line (301) are applied to the power management control circuit (60) and the high frequency processing circuit (70) through a first power management control circuit; The second coaxial cable connection end (102) is respectively printed to the power management control circuit (60) through a second power management control circuit power supply input line (402) and a second polarization and local oscillation control signal transmission line (302). The high-frequency processing circuit (70); after the operation of the power management control circuit (60), the power supply output line (50) of the power management control circuit is connected to the power supply end of the high-frequency processing circuit (70) to provide power supply. On the other hand, the first clock signal outputted by the power management control circuit (60) is applied to the high frequency processing circuit (70) through the clock signal transmission line (80) to function as a reference clock; the high frequency processing circuit ( 70) After being subjected to the post-printing action, the intermediate frequency signal is generated and respectively The first intermediate frequency signal output transmission line (201), a second intermediate frequency signal output transmission line (202) and respective DC blocking capacitors are printed and applied to the corresponding first coaxial cable connection end (101), the second coaxial cable. Connection end (102).

It should be noted that each circuit of the dual-output or multi-output high-frequency processing circuit (70) may require a power supply control circuit to provide a stable power supply voltage. In this case, the power management control circuit (60) The third stage LDO regulator circuit (620) can be set as a dual or multiple parallel output LDO circuit; the second clock signal of the multi-output high frequency processing circuit (70) is multi-way The reference clock generator circuit of the power management control circuit (60) generates and provides; the multi-way power management control circuit (60) provides multi-channel ripple-free, stray-free signal stable power supply voltage to the multi-channel high frequency processing The circuit (70) is used, that is, does not cause multi-output of the high-frequency processing circuit (70) to increase the spur or phase noise, effectively reducing the power consumption of the multi-output high-frequency processing circuit (70), thereby reducing The ambient temperature of its action improves the noise coefficient and increases the receiving sensitivity.

The main point of the design of the present invention is that it can greatly improve the power supply efficiency of the LNB, reduce the power consumption of the power supply itself, and further reduce the power supply management control circuit structure. Less LNB generates heat, lowers the ambient temperature during operation, reduces the noise coefficient of the receiving channel, improves the receiving sensitivity, and provides low ripple, spurious-free, stable power supply voltage for high-frequency processing circuits.

In view of the foregoing description of the embodiments, the operation and the use of the present invention and the effects of the present invention are fully understood, but the above described embodiments are merely preferred embodiments of the present invention, and the invention may not be limited thereto. Included within the scope of the present invention are the scope of the present invention.

Claims (8)

A power management control circuit includes a first stage LDO voltage regulator circuit, a DC/DC converter and a third stage LDO voltage regulator circuit, wherein the input end of the first stage LDO voltage regulator circuit is a power input The output end of the third-stage LDO regulator circuit is a power supply output terminal, and the DC/DC converter includes a switching device electrically connected, a non-overlapping clock generator, and a reference clock generator circuit, wherein The switching device includes a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first switch tube (S1), a second switch tube (S2), and a third switch tube. (S3), a fourth switch tube (S4), a fifth switch tube (S5), a sixth switch tube (S6), a seventh switch tube (S7), and an eighth switch tube (S8); The power input end is connected to one end of the first switch tube (S1) and the fifth switch tube (S5), and the other end of the first switch tube (S1) is connected to one end of the second switch tube (S2) and the first end One end of the capacitor (C1), the other end of the second switch tube (S2) is connected to one end of the sixth switch tube (S6) and the seventh switch tube (S7) and one of the second capacitors (C2) The other end of the sixth switch tube (S6) is connected to the other end of the fifth switch tube (S5), one end of the third switch tube (S3), and one end of the third capacitor (C3), the seventh switch The other end of the tube (S7) is connected to the other end of the third capacitor (C3) and one end of the eighth switch tube (S8), and the other end of the eighth switch tube (S8) is grounded, and the third switch tube (the third switch tube ( The other end of the S3) is connected to one end of the fourth switch tube (S4), and is connected to the other end of the first capacitor (C1), and the other end of the fourth switch tube (S4) is grounded, and the second capacitor ( C2) the other end is grounded; the first switch tube (S1), the second switch tube (S2), the third switch tube (S3), the fourth switch tube (S4), and the fifth switch tube (S5) The control ends of the sixth switch tube (S6), the seventh switch tube (S7) and the eighth switch tube (S8) are respectively connected to the switch control output end of the non-overlapping clock generator, the first segment LDO The voltage stabilizing circuit has a polarization voltage detector, and the non-overlapping clock generator selects and controls the corresponding switching action state according to the output state of the polarization voltage detector. The power management control circuit according to claim 1, wherein the first switch tube (S1), the second switch tube (S2), the third switch tube (S3), and the fourth switch tube ( S4), the fifth switch The tube (S5), the sixth switch tube (S6), the seventh switch tube (S7), and the eighth switch tube (S8) are field effect transistors or metal oxide semiconductor field effect transistors. A power management control circuit includes a first stage LDO voltage regulator circuit, a DC/DC converter and a third stage LDO voltage regulator circuit, wherein the input end of the first stage LDO voltage regulator circuit is a power input The output end of the third-stage LDO regulator circuit is a power supply output terminal, and the DC/DC converter includes a switching device electrically connected, a non-overlapping clock generator, a reference clock generator circuit, and a high frequency The synchronous reference clock output used by the processing circuit, wherein the switching device includes a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first switch (S1), and a a second switch tube (S2), a third switch tube (S3), a fourth switch tube (S4), a fifth switch tube (S5), a sixth switch tube (S6), and a seventh switch tube ( S7) and an eighth switch tube (S8); the power input end is connected to one end of the first switch tube (S1) and the fifth switch tube (S5), and the other end of the first switch tube (S1) is connected to the One end of the second switch tube (S2) and one end of the first capacitor (C1), and the other end of the second switch tube (S2) is connected to the sixth switch tube (S6) and the One end of the seventh switch tube (S7) and one end of the second capacitor (C2), and the other end of the sixth switch tube (S6) is connected to the other end of the fifth switch tube (S5), the third switch tube ( One end of S3) and one end of the third capacitor (C3), the other end of the seventh switch tube (S7) is connected to the other end of the third capacitor (C3) and one end of the eighth switch tube (S8), The other end of the eighth switch tube (S8) is grounded, and the other end of the third switch tube (S3) is connected to one end of the fourth switch tube (S4) and is connected to the other end of the first capacitor (C1). The other end of the fourth switch tube (S4) is grounded, and the other end of the second capacitor (C2) is grounded; the first switch tube (S1), the second switch tube (S2), and the third switch tube (S3) The control end of the fourth switch tube (S4), the fifth switch unit (S5), the sixth switch tube (S6), the seventh switch tube (S7), and the eighth switch tube (S8) Connected to a switch control output of a non-overlapping clock generator, the first stage LDO regulator circuit has a polarization voltage detector, and the non-overlapping clock generator selects and controls a corresponding switch according to an output state of the polarization voltage detector action State. The power management control circuit according to claim 3, wherein the first switch tube (S1), the second switch tube (S2), the third switch tube (S3), and the fourth switch tube ( S4), the fifth switch tube (S5), the sixth switch tube (S6), the seventh switch tube (S7), and the eighth switch tube (S8) are field effect transistors or metal oxide semiconductor fields. Effect transistor. The power management control circuit according to any one of the preceding claims, comprising at least two of the foregoing first stage LDO voltage stabilizing circuits, one of the foregoing DC/DC converters, and a third segment The LDO regulator circuit, the output ends of all the first LDO regulator circuits are respectively connected to a common terminal through respective connection elements, and the common terminal is connected to the input end of the DC/DC converter. The power management control circuit according to claim 5, wherein the connecting element is a diode (D1) or a switch (S0). A power management circuit for applying a power management control circuit, the power management control circuit according to any one of claims 1 to 6, further comprising a coaxial cable connection end, IF signal output transmission line, a DC blocking capacitor, a polarization and local oscillator control signal transmission line, a power management control circuit power supply input line, a power management control circuit power supply output line, a high frequency processing circuit and a clock signal transmission line; The coaxial cable connection end is connected to the DC/DC converter of the power management control circuit via the power supply input line of the power management control circuit, and the coaxial cable connection end is connected to the high frequency processing circuit via a polarization and a local oscillator control signal transmission line. The high frequency processing circuit is connected to the coaxial cable connection end via an intermediate frequency signal output transmission line and a DC blocking capacitor, and the power supply output end of the power management control circuit is connected to the high frequency processing circuit via a power supply control output circuit power supply output line, The clock control circuit of the power management control circuit is connected to the high frequency processing circuit via a clock signal transmission line. The high frequency head circuit of the application power management control circuit according to claim 7, wherein at least two coaxial cable connection ends, a power management control circuit, and a high frequency processing circuit are used, and each coaxial cable connection end passes Their respective intermediate frequency signal output transmission lines, DC blocking capacitors, polarization and local oscillator The control signal transmission line is connected to the high frequency processing circuit, and each coaxial cable connection end is connected to the DC/DC converter of the power management control circuit through a power supply input line of the respective power management control circuit.