TWI636543B - Interconnect structure and fabricating method thereof - Google Patents

Abstract

An interconnect structure includes a first dielectric layer, a first conductor layer, a second conductor layer, a cap layer, and a via. The first dielectric layer has a first trench and a second trench. The first conductor layer is located in the first trench. The second conductor layer is located in the second trench, and the top surface of the second conductor layer is lower than the top surface of the first dielectric layer. The cap layer covers the first dielectric layer, the first conductor layer, and the second conductor layer, and the cap layer has a via opening that exposes a portion of the first conductor layer. The via is located on the first conductor layer and the first dielectric layer between the first conductor layer and the second conductor layer, and the via is filled in the via opening and electrically connected to the first conductor layer.

Description

Internal connection structure and manufacturing method thereof

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to an interconnect structure and a method of fabricating the same.

As the semiconductor element is gradually reduced, the overlap window of the upper conductive element in the interconnect structure and the lower conductive element below it becomes smaller, and thus the alignment deviation is liable to occur, resulting in a decrease in the reliability of the semiconductor element. For example, the dielectric layer of the interconnect structure has a plurality of conductor layers, and the vias are located on and electrically connected to the corresponding conductor layers. When the vias are severely misaligned, they are located in addition to the phases. In addition to the corresponding conductor layer, it also extends over the dielectric layer between the adjacent two conductor layers. In this way, in the case of high operating voltage, metal ions in the via or conductor layer easily pass through the dielectric layer and migrate to adjacent conductor layers (not in direct contact with the via) to cause a short circuit. problem. Therefore, how to improve the reliability of the interconnect structure is one of the issues that R&D personnel need to solve urgently.

The present invention provides an interconnect structure having good reliability and a method of fabricating the same.

An embodiment of the present invention provides an interconnect structure including a first dielectric layer, a first conductor layer, a second conductor layer, a cap layer, and a via. The first dielectric layer has a first trench and a second trench. The first conductor layer is located in the first trench. The second conductor layer is located in the second trench, and the top surface of the second conductor layer is lower than the top surface of the first dielectric layer. The cap layer covers the first dielectric layer, the first conductor layer, and the second conductor layer, and the cap layer has a via opening that exposes a portion of the first conductor layer. The via is located on the first conductor layer and the first dielectric layer between the first conductor layer and the second conductor layer, and the via is filled in the via opening and electrically connected to the first conductor layer.

In an embodiment of the invention, the top surface of the first conductor layer is lower than the top surface of the first dielectric layer.

In an embodiment of the invention, the minimum distance between the via and the second conductor layer is greater than or equal to the offset threshold D _s and D _s = 8 nm.

In an embodiment of the invention, the cap layer covers the sidewall of the second trench and the top surface of the second conductor layer, and the via window and the second conductor layer have a first distance x in the X direction, and x>0 Nm.

In an embodiment of the invention, the cap layer fills the second trench, the via window covers the second conductor layer, and the second window has a second distance y between the via window and the second conductor layer, and y≧D _s .

In an embodiment of the invention, a second dielectric layer covering the cap layer and surrounding the via window is further included.

An embodiment of the present invention provides a method of fabricating an interconnect structure including the following steps. Forming a first trench and a second trench in the first dielectric layer. A layer of conductive material is filled in the first trench and the second trench. Removing a portion of the conductive material layer to form a first conductor layer and a second conductor layer in the first trench and the second trench, respectively, and a top surface of the first conductor layer and the second conductor layer is lower than the first dielectric layer Top surface. A cap layer is formed on the first dielectric layer, the first conductor layer, and the second conductor layer. A second dielectric layer is formed on the cap layer. Forming a via in the cap layer and the second dielectric layer, wherein the via is formed on the first conductor layer and the first dielectric layer between the first conductor layer and the second conductor layer, and is electrically connected To the first conductor layer.

In an embodiment of the invention, the minimum distance between the via and the second conductor layer is greater than or equal to the offset threshold D _s and D _s = 8 nm.

In an embodiment of the invention, the cap layer covers the sidewall of the second trench and the top surface of the second conductor layer, and the via window and the second conductor layer have a first distance x in the X direction, and x>0 Nm.

In an embodiment of the invention, the cap layer fills the second trench, the via window covers the second conductor layer, and the second window has a second distance y between the via window and the second conductor layer, and y≧D _s .

Based on the above, in the interconnect structure and the manufacturing method thereof according to the above embodiments of the present invention, since the top surface of the second conductor layer is lower than the top surface of the first dielectric layer, the second conductor layer and the second conductor layer can be enlarged. The minimum distance between the layer windows avoids the problem that the distance between the two is smaller than the offset threshold and causes a short circuit, so that the interconnect structure can still improve the via window while maintaining the miniaturization design. The margin of overlap with the first conductor layer, thereby increasing the reliability of the interconnect structure.

The above described features and advantages of the invention will be apparent from the following description.

The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not be repeated.

1A-1F are schematic cross-sectional views showing a method of fabricating an interconnect structure in accordance with an embodiment of the present invention. 2 is a cross-sectional view showing an interconnect structure in accordance with another embodiment of the present invention. 3 is a cross-sectional view showing an interconnect structure in accordance with still another embodiment of the present invention.

Referring to FIG. 1A, a substrate 100 is provided. Substrate 100 includes a semiconductor substrate. The semiconductor substrate is, for example, a doped germanium substrate, an undoped germanium substrate or an insulator overlying (SOI) substrate. The doped germanium substrate can be P-type doped, N-type doped, or a combination thereof. In some embodiments, the substrate 100 further includes an inner dielectric layer and/or a contact window, but the invention is not limited thereto. In other embodiments, the substrate 100 includes an inner dielectric layer and/or a contact window, and further includes an inter-metal dielectric layer (IMD), a multi-metal interconnect conductor layer, and/or a via.

Next, a first dielectric layer 102 is formed on the substrate 100. The material of the first dielectric layer 102 is, for example, a dielectric material. The dielectric material is, for example, cerium oxide, tetraethoxy methoxy hydride (TEOS) cerium oxide, cerium nitride, cerium oxynitride, undoped bismuth glass (USG), borophosphoquinone glass (BPSG), phosphor bismuth glass ( PSG), a low dielectric constant material having a dielectric constant of less than 4, or a combination thereof. Low dielectric constant materials are, for example, fluorine-doped bismuth glass (FSG), sesquioxide, aromatic hydrocarbons, organic silicate glass, parylene, fluorinated polymers (Fluoro-Polymer), Poly(arylethers), Porous polymer, or a combination thereof. The oxime sesquioxide is, for example, Hydrogen Silsesquioxnane (HSQ), Methyl silsesquioxane (MSQ) or Hybrido-organo siloxane polymer (HOSP). The aromatic hydrocarbon is, for example, SiLK. The organic tellurite glass is, for example, black diamond (BD), 3MS or 4MS. Fluorinated polymers are, for example, PFCB, CYTOP, Teflon. The polyarylene ether is, for example, PAE-2 or FLARE. The porous polymer is, for example, XLK, Nanofoam, Awrogel or Coral. The formation method of the first dielectric layer 102 is, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), spin coating (SOG), or a combination thereof.

Then, a first trench 104 and a second trench 106 are formed in the first dielectric layer 102. In some embodiments, the first trench 104 and the second trench 106 may be formed in the first dielectric layer 102 by forming a patterned photoresist layer (not shown) on the first dielectric layer 102. Next, the first dielectric layer 102 exposed by the patterned photoresist layer is removed to form a first trench 104 and a second trench 106 in the first dielectric layer 102. Thereafter, the patterned photoresist layer is removed. The method of removing the first dielectric layer 102 exposed by the patterned photoresist layer may employ etching, such as dry etching, wet etching, or a combination thereof. A method of removing the patterned photoresist layer is, for example, an ashing process (Ash).

Then, the first trench 104 and the second trench 106 are filled with the conductive material layer 108, and the conductive material 108 also covers the first dielectric layer 102 and fills the first trench 104 and the second trench 106. The conductor material layer 108 is, for example, a metal, a metal alloy, a metal nitride, a metal halide, or a combination thereof. In some exemplary embodiments, the metal to metal alloy is, for example, copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), platinum (Pt), chromium (Cr), molybdenum ( Mo) or an alloy thereof. The metal nitride is, for example, titanium nitride, tungsten nitride, tantalum nitride, tantalum nitride (TaSiN), tantalum nitride nitride (TiSiN), tantalum tungsten nitride (WSiN), or a combination thereof. The metal halides are, for example, tungsten telluride, titanium telluride, cobalt telluride, zirconium telluride, platinum telluride, molybdenum telluride, copper telluride, nickel telluride or combinations thereof. The method of forming the conductor material layer 108 is, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination thereof.

Referring to FIG. 1A and FIG. 1B, the conductive material layer 108 on the first dielectric layer 102 is removed to form a conductive material layer 108a and a conductive material layer 108b in the first trench 104 and the second trench 106, respectively. The method of removing the conductive material layer 108 on the first dielectric layer 102 is, for example, a planarization process of the conductive material layer 108. The planarization process is, for example, a chemical mechanical polishing process (CMP). In some embodiments, the top surfaces of the conductive material layer 108a and the conductive material layer 108b are coplanar with the top surface of the first dielectric layer 102.

Referring to FIG. 1B and FIG. 1C, a portion of the conductive material layer 108a and the conductive material layer 108b are removed to form a first conductive layer 110 and a second conductive layer 112 in the first trench 104 and the second trench 106, respectively. The top surfaces of the one conductor layer 110 and the second conductor layer 112 are lower than the top surface of the first dielectric layer 102. That is, the top surfaces of the first conductor layer 110 and the second conductor layer 112 and the sidewalls of the first dielectric layer 102 define a recess 104a and a recess 106a, respectively. As a result, the minimum distance between the via 120 and the second conductor layer 112 electrically connected to the first conductor layer 110 can be expanded, so that even when the via 120 is formed, alignment deviation occurs. The distance between the via 120 and the second conductor layer 112 can still be greater than the offset threshold D _s . Therefore, in the case of a high operating voltage, the problem that the conductor ions (for example, metal ions) in the via 120 migrate to the second conductor layer 112 to cause a short circuit can be avoided, thereby improving the reliability of the interconnect structure. The offset threshold value D _s represents a minimum distance that conductor ions in the via 120 can not migrate to the second conductor layer 112 via the cap layer 114 and/or the first dielectric layer 102 . In some embodiments, the offset threshold value D _s can be obtained by the following formula (1): In the formula (1), D _s represents an offset threshold value; W110 represents the width of the first conductor layer 110; W120 represents the width of the via window 120; and W102 represents the first dielectric between the adjacent two conductor layers. The width of the layer (e.g., the width of the first dielectric layer 102 between the first conductor layer 110 and the second conductor layer 112); S120 represents the maximum overlap shift specification of the via 120.

For example, the width of the first conductor layer 110 is 161 nm; the width of the via 120 is 151 nm; the width of the first dielectric layer 102 between the first conductor layer 110 and the second conductor layer 112 is 15 nm. The maximum allowable offset error value of the via 120 is 12 nm, in which case the offset threshold D _s is 8 nm ([(161-151)] / 2 + 15-12).

In some embodiments, a portion of the conductor material layer 108a and a portion of the conductor material layer 108b may be removed by an etching back, but the invention is not limited thereto. In some embodiments, the conductive material layer 108b located in the second trench 106 may also be selectively removed such that the top surface of the second conductive layer 112 is lower than the top surface of the first dielectric layer 102, and the first conductor The top surface of layer 110 is then coplanar with the top surface of first dielectric layer 102.

Referring to FIG. 1C and FIG. 1D simultaneously, a cap layer 114 is formed on the first dielectric layer 102, the first conductor layer 110, and the second conductor layer 112. The material of the cap layer 114 is, for example, tantalum nitride (SiN), tantalum carbide (SiC), tantalum carbonitride (SiCO), tantalum nitride (SiNC) or a combination thereof, but the invention is not limited thereto. In some embodiments, the cap layer 114 is conformally formed on the surface of the recess 104a, the recess 106a, and the first dielectric layer 102. In other words, the cap layer 114 covers the sidewalls of the first trench 104 and the second trench 106 and the top surfaces of the first conductor layer 110, the second conductor layer 112, and the first dielectric layer 102. In other embodiments, the width W1 of the first trench 104 is greater than the width W2 of the second trench 106. Therefore, the thickness d of the cap layer 114 is greater than or equal to half the width W2 of the second trench 106 (d≧W2/2 In the case of the cover layer 114, the cap layer 114 is conformally formed on the surface of the recess 104a and the first dielectric layer 102, and fills the recess 106a. That is, the cap layer 114 covers not only the sidewalls of the first trench 104 and the second trench 106 but also the top surfaces of the first conductor layer 110, the second conductor layer 112, and the first dielectric layer 102, which also fills the second trench Slot 106. In some embodiments, the width W1 of the first trench 104 is 161 nm; the width W2 of the second trench 106 is 27 nm; the width of the first dielectric layer 102 between the first trench 104 and the second trench 106 is 15 Nm.

Referring to FIG. 1E, a second dielectric layer 116 is formed on the cap layer 114. The material of the second dielectric layer 116 is, for example, a dielectric material. The dielectric material is, for example, cerium oxide, tetraethoxy methoxy hydride (TEOS) cerium oxide, cerium nitride, cerium oxynitride, undoped bismuth glass (USG), borophosphoquinone glass (BPSG), phosphor bismuth glass ( PSG), a low dielectric constant material having a dielectric constant of less than 4, or a combination thereof. Low dielectric constant materials are, for example, fluorine-doped bismuth glass (FSG), sesquioxide, aromatic hydrocarbons, organic silicate glass, parylene, fluorinated polymers (Fluoro-Polymer), Poly(arylethers), Porous polymer, or a combination thereof. The oxime sesquioxide is, for example, Hydrogen Silsesquioxnane (HSQ), Methyl silsesquioxane (MSQ) or Hybrido-organo siloxane polymer (HOSP). The aromatic hydrocarbon is, for example, SiLK. The organic tellurite glass is, for example, black diamond (BD), 3MS or 4MS. Fluorinated polymers are, for example, PFCB, CYTOP, Teflon. The polyarylene ether is, for example, PAE-2 or FLARE. The porous polymer is, for example, XLK, Nanofoam, Awrogel or Coral. The method of forming the second dielectric layer 116 is, for example, ALD, CVD, SOG, or a combination thereof.

Referring to FIG. 1E and FIG. 1F simultaneously, a via 120 is formed in the cap layer 114 and the second dielectric layer 116. The via window 120 is formed on the first conductor layer 110 and the first dielectric layer 102 between the first conductor layer 110 and the second conductor layer 112 , and is electrically connected to the first conductor layer 110 . The material of the via 120 is, for example, a metal, a metal alloy, a metal nitride, a metal telluride or a combination thereof. In some exemplary embodiments, the metal to metal alloy is, for example, copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), platinum (Pt), chromium (Cr), molybdenum ( Mo) or an alloy thereof. The metal nitride is, for example, titanium nitride, tungsten nitride, tantalum nitride, tantalum nitride (TaSiN), tantalum nitride nitride (TiSiN), tantalum tungsten nitride (WSiN), or a combination thereof. The metal halides are, for example, tungsten telluride, titanium telluride, cobalt telluride, zirconium telluride, platinum telluride, molybdenum telluride, copper telluride, nickel telluride or combinations thereof. In some embodiments, the method of forming the via 120 may be to form the patterned photoresist layer 118 on the second dielectric layer 116. Next, the second dielectric layer 116 exposed by the patterned photoresist layer 118 is removed by using the cap layer 114 as an etch stop layer. Thereafter, the cap layer 114 exposed by the second dielectric layer 116 is removed to form a via opening 117 exposing the first conductor layer 110. The patterned photoresist layer 118 is then removed. Finally, a dielectric material (for example, a material such as a material of the via 120) is filled in the via opening 117 and planarized (eg, CMP) for the cap layer 114 and the second dielectric layer 116. A via window 120 is formed in the middle. The method of removing the second dielectric layer 116 may be by etching, such as dry etching, wet etching, or a combination thereof. In some embodiments, the method of removing the second dielectric layer 116 is to use a selective etch process, but the invention is not limited thereto. The method of removing the cap layer 114 may be by etching, such as dry etching, wet etching, or a combination thereof. In some embodiments, the method of removing the cap layer 114 is to use time mode etching, but the invention is not limited thereto. The method of filling the via material opening 117 with the conductor material is, for example, ALD, CVD, PVD, or a combination thereof. The method of removing the patterned photoresist layer 118 is, for example, an ashing process.

Referring to FIG. 1F and FIG. 2 simultaneously, the minimum distance between the via 120 and the second conductor layer 112 is greater than the offset threshold D _s . In this way, in the case of high operating voltage, the problem that the conductor ions (for example, metal ions) in the via 120 migrate to the second conductor layer 112 to cause a short circuit can be avoided, thereby improving the reliability of the interconnect structure. In some embodiments, the via 120 and the second conductor layer 112 have a first distance x and a second distance y in the X direction and the Y direction, respectively, as shown in FIG. 2 . In the case of y ≧ D _s , even if the via 120 covers the second conductor layer 112 (ie, x=0), the cap layer 114 between the via 120 and the second conductor layer 112 has sufficient thickness. Metal ions (e.g., copper ions) in the barrier window 120 are prevented from migrating to the second conductor layer 112 to prevent a short circuit from occurring. In other embodiments, as shown in FIG. 2, in the case where x ≧ D _s and y > 0 (the top surface of the second conductor layer 112 is lower than the top surface of the first dielectric layer 102), the via window 120 does not cover the second conductor layer 112, and the minimum distance between the via 120 and the second conductor layer 112 (the distance indicated by the dashed line, ie ) is greater than the offset threshold D _s . In addition, as the alignment offset error between the via 120 and the first conductor layer 110 is smaller (ie, x is larger), the minimum distance between the via 120 and the second conductor layer 112 is larger, There will be no short circuit problems. That is to say, by the design of the top surface of the second conductor layer 112 being lower than the top surface of the first dielectric layer 102 (y>0), the interconnect structure can not only maintain the miniaturization design, but also further improve the interface. The margin of overlap between the layer window 120 and the first conductor layer 110. In some embodiments, the maximum width of the via 120 (eg, the width of the via 120 on the first dielectric layer 102) is 151 nm.

For example, the offset threshold D _s between the via 120 and the second conductor layer 112 is 8 nm (ie, the maximum allowable offset error value of the via 120 is 12 nm). In the case where the top surface of the second conductor layer 112 and the top surface of the first dielectric layer 102 are coplanar (ie, y=0), and the first distance x is 6 nm (ie, the offset of the via 120 Greater than the maximum allowable offset error value), the minimum distance between the via 120 and the second conductor layer 112 is 6 nm, which is smaller than the offset threshold D _s , so that a short circuit problem is easily generated. However, in the case where the top surface of the second conductor layer 112 is lower than the top surface of the first dielectric layer 102 and the second distance y is 8 nm, the minimum distance between the via 120 and the second conductor layer 112 Increase from 6 nm to 10 nm ( ), which is greater than the offset threshold value D _s , so that even if the offset of the via 120 is greater than the maximum allowable offset error value, the problem of short circuit can be avoided. That is, without increasing the width W1 of the first conductor layer 110, even if the same process machine is used to form the interconnect structure (ie, the resolution limit of the machine is the same), the via 120 can be made. The minimum distance from the second conductor layer 112 is greater than or equal to the offset threshold value D _s .

In addition, as shown in FIG. 2, in some embodiments, since the cap layer 114 does not fill the second trench 106, the second dielectric layer 116 subsequently formed on the cap layer 114 fills the second trench 106. As such, in the process of forming the via opening 117, the step of removing the second dielectric layer 116 exposed by the patterned photoresist layer by using the cap layer 114 as an etch stop layer will cause the via The opening 117 extends downwardly onto the cap layer 114 located in the second trench 106, resulting in a shortened minimum distance between the via 120 and the second conductor layer 112. Therefore, in the case that the cap layer 114 is not filled in the second trench 106, the via 120 does not cover above the second conductor layer 112 (ie, x>0) to avoid the via 120 and the second conductor layer. The shortest distance between 112 becomes smaller and a problem of short circuit occurs.

In addition, as shown in FIG. 3, in some embodiments, the width of the via 320 is greater than the width of the first conductor layer 110, and the via 320 fills the recess 104a on the first conductor layer 110 (see FIG. 1C). ). That is, even if no alignment deviation occurs between the via 320 and the first conductor layer 110, the via 320 still covers the first dielectric layer 102 between the first conductor layer 110 and the second conductor layer 112. Even covering part of the second conductor layer 112. Therefore, by the design that the top surface of the second conductor layer 112 is lower than the top surface of the first dielectric layer 102, the minimum distance between the second conductor layer 112 and the via 320 can be enlarged (eg, the second distance y Therefore, it is still possible to avoid the problem that the distance between the two is smaller than the offset threshold and short circuit occurs.

Hereinafter, the interconnect structure of the present embodiment will be described with reference to FIGS. 1F and 2. Further, although the manufacturing method of the interconnect structure of the present embodiment is described by taking the above-described manufacturing method as an example, the method of manufacturing the interconnect structure of the present invention is not limited thereto.

Referring to FIG. 1F , the interconnect structure includes a first dielectric layer 102 , a first conductor layer 110 , a second conductor layer 112 , a cap layer 114 , and a via 120 . The first dielectric layer 102 has a first trench 104 and a second trench 106. The first conductor layer 110 is located in the first trench 104. The second conductor layer 112 is located in the second trench 106 , and the top surface of the second conductor layer 112 is lower than the top surface of the first dielectric layer 102 . The cap layer 114 covers the first dielectric layer 102, the first conductor layer 110, and the second conductor layer 112, and the cap layer 114 has a via opening 117 exposing a portion of the first conductor layer 110. The via 120 is located on the first conductor layer 110 and the first dielectric layer 102 between the first conductor layer 110 and the second conductor layer 112, and the via 120 is filled in the via opening 117 and electrically Connected to the first conductor layer 110. Furthermore, the minimum distance between the via 120 and the second conductor layer 112 is greater than or equal to the offset threshold D _s . In some embodiments, in the case where the cap layer 114 fills the second trench 106 and the via 120 covers the second conductor layer 112, the via 120 and the second conductor layer 112 have the first direction in the Y direction. Two distances y, and y≧D _s . In other embodiments, as shown in FIG. 2, in the case where the cap layer 114 covers the sidewall of the second trench 106 and the top surface of the second conductor layer 112 without filling the second trench 106, the via 120 The second conductor layer 112 has a first distance x and a second distance y in the X direction and the Y direction, respectively, and x>0 nm. As such, the distance between the via 120 and the second conductor layer 112 is the distance indicated by the dashed line (ie, ). In some embodiments, the offset threshold D _s is 8 nm. In some embodiments, the top surface of the first conductor layer 110 can be selectively lower than the top surface of the first dielectric layer 102. In some embodiments, the interconnect structure further includes a second dielectric layer 116 that covers the cap layer 114 and surrounds the via 120. In addition, the materials, arrangement, formation method and efficacy of each member in the interconnect structure have been described in detail in the above-described manufacturing method of FIGS. 1A to 1F, and thus will not be described herein.

In summary, in the interconnect structure and the manufacturing method thereof according to the above embodiments, since the top surface of the second conductor layer is lower than the top surface of the first dielectric layer, the second conductor layer and the via layer may be enlarged. The minimum distance between the windows avoids the problem that the distance between the two is less than the offset threshold and short circuit, so that the interconnect structure can still improve the via and the first conductor layer while maintaining the miniaturization design. The overlap margin between them increases the reliability of the interconnect structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base
102‧‧‧First dielectric layer
104‧‧‧First ditches
104a, 106a‧‧‧ dent
106‧‧‧Second ditches
108, 108a, 108b‧‧‧ conductor material layer
110‧‧‧First conductor layer
112‧‧‧Second conductor layer
114‧‧‧ cover
116‧‧‧Second dielectric layer
117, 317‧‧ ‧ through window opening
118‧‧‧ patterned photoresist layer
120, 320‧‧‧ through window
W1, W2‧‧‧ width
D‧‧‧thickness
D _s ‧‧‧Offset threshold
X‧‧‧X direction
Y‧‧‧Y direction
X‧‧‧first distance
y‧‧‧Second distance

1A-1F are schematic cross-sectional views showing a method of fabricating an interconnect structure in accordance with an embodiment of the present invention. 2 is a cross-sectional view showing an interconnect structure in accordance with another embodiment of the present invention. 3 is a cross-sectional view showing an interconnect structure in accordance with still another embodiment of the present invention.

Claims (10)

An interconnect structure includes: a first dielectric layer having a first trench and a second trench; a first conductor layer located in the first trench; a second conductor layer located in the second trench, and a top surface of the second conductor layer is lower than a top surface of the first dielectric layer; a cap layer covering the first dielectric layer, the first conductor layer, and the second conductor layer, and The cap layer has a via opening exposing a portion of the first conductor layer; and a via window on the first conductor layer and between the first conductor layer and the second conductor layer a first dielectric layer, and the via is filled in the via opening and electrically connected to the first conductor layer. The interconnect structure of claim 1, wherein a top surface of the first conductor layer is lower than a top surface of the first dielectric layer. The interconnect structure of claim 1, wherein a minimum distance between the via window and the second conductor layer is greater than or equal to an offset threshold value D _s and D _s = 8 nm. The interconnect structure of claim 3, wherein the cap layer covers a sidewall of the second trench and a top surface of the second conductor layer, the via and the second conductor The layers have a first distance x in the X direction and x > 0 nm. The interconnect structure of claim 3, wherein the cap layer fills the second trench, the via window covers the second conductor layer, the via window and the via The two conductor layers have a second distance y between the Y directions and y ≧ D _s . The interconnect structure as described in claim 1, further comprising: a second dielectric layer covering the cover layer and surrounding the via window. A method for fabricating an interconnect structure includes: forming a first trench and a second trench in the first dielectric layer; filling a conductive material layer in the first trench and the second trench; a conductive material layer for forming a first conductor layer and a second conductor layer in the first trench and the second trench, respectively, and a top surface of the first conductor layer and the second conductor layer is lower than a top surface of the first dielectric layer; a cap layer formed on the first dielectric layer, the first conductor layer, and the second conductor layer; a second dielectric layer formed on the cap layer And forming a via in the cap layer and the second dielectric layer, wherein the via is formed on the first conductor layer and the first conductor layer and the second conductor layer On the first dielectric layer between and electrically connected to the first conductor layer. The manufacturing method of the interconnect structure according to claim 7, wherein a minimum distance between the via window and the second conductor layer is greater than or equal to an offset threshold value D _s , and D _s = 8 nm. The method of manufacturing an interconnect structure according to claim 8, wherein the cap layer covers a sidewall of the second trench and a top surface of the second conductor layer, the via and the The second conductor layer has a first distance x in the X direction and x>0 nm. The method for manufacturing an interconnect structure according to claim 8, wherein the cap layer fills the second trench, the via cover covers the second conductor layer, and the via The second conductor layer has a second distance y in the Y direction, and y ≧ D _s .