TWI636540B - Semiconductor package and manufacturing method of semiconductor package - Google Patents

Semiconductor package and manufacturing method of semiconductor package Download PDF

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Publication number
TWI636540B
TWI636540B TW105140077A TW105140077A TWI636540B TW I636540 B TWI636540 B TW I636540B TW 105140077 A TW105140077 A TW 105140077A TW 105140077 A TW105140077 A TW 105140077A TW I636540 B TWI636540 B TW I636540B
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encapsulant
shielding
electronic component
component
semiconductor package
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TW105140077A
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TW201822324A (en
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方柏翔
賴佳助
張月瓊
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矽品精密工業股份有限公司
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Priority to TW105140077A priority Critical patent/TWI636540B/en
Priority to CN201611243330.9A priority patent/CN108155107B/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

一種半導體封裝件及半導體封裝件的製法,該半導體封裝件包含一載板、一第一封裝組件與一第二封裝組件,該第一封裝組件設置於該載板的設置面且包含至少一第一電子元件與包覆該至少一第一電子元件的一第一封裝膠體,該第二封裝組件設置於該載板的設置面且包含至少一第二電子元件與包覆該至少一第二電子元件的一第二封裝膠體,該第一封裝膠體的電磁波損耗率大於該第二封裝膠體的電磁波損耗率,使半導體封裝件能兼具抗電磁干擾以及良好的電磁輻射或感應效率。A semiconductor package and a semiconductor package, the semiconductor package comprising a carrier, a first package component and a second package component, the first package component being disposed on the mounting surface of the carrier and comprising at least one An electronic component and a first encapsulant covering the at least one first electronic component, the second package component being disposed on the mounting surface of the carrier and including at least one second electronic component and covering the at least one second electronic component A second encapsulant of the component, the electromagnetic loss rate of the first encapsulant is greater than the electromagnetic wave loss rate of the second encapsulant, so that the semiconductor package can have both electromagnetic interference resistance and good electromagnetic radiation or induction efficiency.

Description

半導體封裝件及半導體封裝件的製法Semiconductor package and semiconductor package manufacturing method

本創作是關於一種半導體封裝件及半導體封裝件的製法,特別是指兼具抗電磁干擾以及提升電磁輻射或感應效率的半導體封裝件及半導體封裝件的製法。 The present invention relates to a method of manufacturing a semiconductor package and a semiconductor package, and more particularly to a method of manufacturing a semiconductor package and a semiconductor package which are resistant to electromagnetic interference and enhance electromagnetic radiation or induction efficiency.

由於電子產業的蓬勃發展,電子產品朝向小型化及高速化的目標發展,尤其是無線通訊產業的發展已普遍運用整合於各類電子產品,例如行動電話、筆記型電腦、智慧型手機、平板電腦...等,故前述電子產品使用具無線通訊功能的半導體封裝件。部份半導體封裝件內部具有天線或是天線附屬電路,但天線可能相鄰設置數位積體電路、數位訊號處理器(Digital Signal Processor,DSP)、基頻(Base Band,BB)晶片或射頻(Radio Frequency,RF)晶片...等,造成電磁干擾的現象,因此必需進行電磁屏蔽(Electromagnetic Shielding)處理。 Due to the booming development of the electronics industry, the development of electronic products towards miniaturization and high speed, especially the development of the wireless communication industry has been widely used in various electronic products, such as mobile phones, notebook computers, smart phones, tablets. ...etc., the aforementioned electronic products use semiconductor packages with wireless communication functions. Some semiconductor packages have an antenna or an antenna accessory circuit inside, but the antenna may be adjacent to a digital integrated circuit, a digital signal processor (DSP), a baseband (BB) chip, or a radio frequency (Radio). Frequency, RF, etc., cause electromagnetic interference, so electromagnetic shielding (Electromagnetic Shielding) must be performed.

以下配合製法說明習知半導體封裝件,請參考圖1,於一載板10的一表面設置一第一電子元件11、一第二電子元件12與一屏蔽牆13,該屏蔽牆13可為金屬牆,其中該第一電子元件11與該第二電子元件12為分離設置,該屏蔽牆13位於該第一電子元件11與該第二電子元件12之間。該第一電子元件11可為需要抗電磁干擾處理的元件,例如前述的數位積體電路、數位訊號處理器、基頻晶片或射頻晶片...等,該第二電子元件12可為前述的天線。 Referring to FIG. 1 , a first electronic component 11 , a second electronic component 12 and a shielding wall 13 are disposed on a surface of a carrier 10 . The shielding wall 13 can be metal. The wall, wherein the first electronic component 11 and the second electronic component 12 are disposed separately, and the shielding wall 13 is located between the first electronic component 11 and the second electronic component 12. The first electronic component 12 can be an element that requires anti-electromagnetic interference processing, such as the aforementioned digital integrated circuit, digital signal processor, baseband chip or radio frequency chip, etc., and the second electronic component 12 can be as described above. antenna.

請參考圖2,在該載板10上形成一封裝膠體14,該封裝膠體14包覆該第一電子元件11、該第二電子元件12與該屏蔽牆13。請參考圖3,在該封裝膠體14的表面挖槽以形成一開口15,使該屏蔽牆13外露於該開口15。請參考圖4,在該封裝膠體14的表面對應於該第一電子元件11的部位形成一屏蔽層16,該屏蔽層16可為金屬層,且該屏蔽層16填入該開口15內以連接該屏蔽牆13,完成習知半導體封裝件100。需說明的是,半導體封裝件100可包含更多電子元件,在此僅以該第一電子元件11與該第二電子元件12為例說明;此外,該載板10可為線路板且電性連接該第一電子元件11與該第二電子元件12,且該載板10種類繁多並為業界的公知常識,在此不加以贅述。 Referring to FIG. 2 , an encapsulant 14 is formed on the carrier 10 , and the encapsulant 14 covers the first electronic component 11 , the second electronic component 12 , and the shielding wall 13 . Referring to FIG. 3, the surface of the encapsulant 14 is grooved to form an opening 15 to expose the shielding wall 13 to the opening 15. Referring to FIG. 4, a shielding layer 16 is formed on a surface of the encapsulant 14 corresponding to the first electronic component 11. The shielding layer 16 may be a metal layer, and the shielding layer 16 is filled in the opening 15 to be connected. The shield wall 13 completes the conventional semiconductor package 100. It should be noted that the semiconductor package 100 may include more electronic components, and only the first electronic component 11 and the second electronic component 12 are exemplified herein; in addition, the carrier 10 may be a circuit board and electrically The first electronic component 11 and the second electronic component 12 are connected, and the carrier 10 is of various types and is common knowledge in the industry, and details are not described herein.

如此一來,該第一電子元件11被該屏蔽牆13與該屏蔽層16包圍,故對於該第一電子元件11來說,該屏蔽牆13能屏蔽來自於該第二電子元件12的電磁波,該屏蔽層16能屏蔽來自於外界環境的電磁波,而能避免該第一電子元件11受到電磁干擾的問題;另一方面,該第二電子元件12沒有被屏蔽,故該第二電子元件12有效能對外輻射電磁波或感應外界電磁波。 In this way, the first electronic component 11 is surrounded by the shielding layer 13 and the shielding layer 16 , so that the shielding wall 13 can shield the electromagnetic wave from the second electronic component 12 for the first electronic component 11 . The shielding layer 16 can shield electromagnetic waves from the external environment, and can avoid the problem that the first electronic component 11 is subjected to electromagnetic interference; on the other hand, the second electronic component 12 is not shielded, so the second electronic component 12 is effective. It can radiate electromagnetic waves or induce external electromagnetic waves.

此外,該封裝膠體14也能採用具損耗電磁波功能的封裝膠體,例如該封裝膠體14可包含環氧樹脂(epoxy resin)與掺在環氧樹脂內而與環氧樹脂混合的抗電磁干擾材料,抗電磁干擾材料可為吸波材料或微金屬材料。 In addition, the encapsulant 14 can also adopt an encapsulant having a lossy electromagnetic wave function. For example, the encapsulant 14 can include an epoxy resin and an anti-electromagnetic interference material mixed with an epoxy resin and mixed with an epoxy resin. The anti-electromagnetic interference material may be an absorbing material or a micro metal material.

然而,因為該第一電子元件11與該第二電子元件12都被包覆在具相同抗電磁干擾材料的該封裝膠體14內,當該封裝膠體14的損耗電磁波能力較高,雖可有助於該第一電子元件11抗電磁干擾,但卻相對限制該第二電子元件12對外輻射電磁波或感應外界電磁波的效率;相反的,當該封裝膠體14的損耗電磁波能力較低,雖可有助於提升該第二電子元件12對外輻射電磁波或感應外界電磁波的效率,但卻相對降低該第一電子元件11抗電磁干擾的功能。是 以,該封裝膠體14的材質選用往往無法同時滿足該第一電子元件11與該第二電子元件12的需求。 However, since the first electronic component 11 and the second electronic component 12 are both encapsulated in the encapsulant 14 having the same anti-electromagnetic interference material, the encapsulation colloid 14 has a high loss of electromagnetic wave capability, which may be helpful. The first electronic component 11 is resistant to electromagnetic interference, but relatively restricts the efficiency of the second electronic component 12 to radiate electromagnetic waves or induce external electromagnetic waves; conversely, when the packaged colloid 14 has low loss of electromagnetic wave capability, it may be helpful. The function of radiating electromagnetic waves or inducing external electromagnetic waves by the second electronic component 12 is improved, but the function of the first electronic component 11 against electromagnetic interference is relatively reduced. Yes Therefore, the material of the encapsulant 14 is often unable to meet the requirements of the first electronic component 11 and the second electronic component 12 at the same time.

有鑒於此,本創作的主要目的是提供一種半導體封裝件與半導體封裝件的製法,使本創作半導體封裝件能兼具抗電磁干擾以及提升電磁輻射或感應的效率,克服先前技術所述問題。 In view of this, the main object of the present invention is to provide a method for fabricating a semiconductor package and a semiconductor package, which enables the present semiconductor package to have both electromagnetic interference resistance and efficiency of electromagnetic radiation or induction, overcoming the problems described in the prior art.

本創作半導體封裝件包含:一載板,具有一設置面;一第一封裝組件,設置於該載板的該設置面,該第一封裝組件包含至少一第一電子元件與包覆該至少一第一電子元件的一第一封裝膠體;以及一第二封裝組件,設置於該載板的該設置面,該第二封裝組件包含至少一第二電子元件與包覆該至少一第二電子元件的一第二封裝膠體,該第一封裝膠體的電磁波損耗率大於該第二封裝膠體的電磁波損耗率。 The semiconductor package of the present invention comprises: a carrier board having a mounting surface; a first package component disposed on the mounting surface of the carrier board, the first package component comprising at least one first electronic component and covering the at least one a first encapsulant of the first electronic component; and a second package component disposed on the mounting surface of the carrier, the second package component including at least one second electronic component and the at least one second electronic component The second encapsulant colloid has an electromagnetic wave loss rate greater than an electromagnetic wave loss rate of the second encapsulant.

根據本創作的結構,該第一封裝膠體與該第二封裝膠體分別為不同的封裝膠體,故本創作能依照該第一電子元件與該第二電子元件對於抗電磁干擾的需求而分別設定該第一封裝膠體與該第二封裝膠體的電磁波損耗率,進而同時滿足該第一電子元件與該第二電子元件的需求,達到雙贏狀態。此外,和先前技術相比,本創作未設置屏蔽牆,故本創作的成本能相對於習知半導體封裝件的成本更低。 According to the structure of the present invention, the first encapsulant and the second encapsulant are different encapsulants respectively, so the creation can be respectively set according to the requirements of the first electronic component and the second electronic component for anti-electromagnetic interference. The electromagnetic wave loss rate of the first encapsulant and the second encapsulant further satisfy the requirements of the first electronic component and the second electronic component to achieve a win-win state. In addition, compared with the prior art, the present invention does not have a shielding wall, so the cost of the creation can be lower than that of the conventional semiconductor package.

本創作半導體封裝件的製法包含:於一載板的一設置面設置至少一第一電子元件與至少一第二電子元件;於該載板的該設置面形成一第一封裝膠體,且使該第一封裝膠體包覆該至少一第一電子元件;以及 於該載板的該設置面形成一第二封裝膠體,且使該第二封裝膠體包覆該至少一第二電子元件,該第一封裝膠體的電磁波損耗率大於該第二封裝膠體的電磁波損耗率。 The method for manufacturing a semiconductor package includes: disposing at least one first electronic component and at least one second electronic component on a mounting surface of a carrier; forming a first encapsulant on the mounting surface of the carrier, and The first encapsulant encapsulates the at least one first electronic component; Forming a second encapsulant on the mounting surface of the carrier, and encapsulating the second encapsulant with the at least one second electronic component, the electromagnetic entrapment loss of the first encapsulant being greater than the electromagnetic loss of the second encapsulant rate.

根據本創作的製法,本創作不需在封裝膠體挖槽以形成開口,故本創作製法能相較於習知半導體封裝件的製法更為簡化。 According to the method of the present creation, the creation does not need to be grooved in the encapsulant to form an opening, so the creation method can be simplified compared with the conventional semiconductor package.

100‧‧‧半導體封裝件 100‧‧‧Semiconductor package

10‧‧‧載板 10‧‧‧ Carrier Board

11‧‧‧第一電子元件 11‧‧‧First electronic components

12‧‧‧第二電子元件 12‧‧‧Second electronic components

13‧‧‧屏蔽牆 13‧‧‧Shield wall

14‧‧‧封裝膠體 14‧‧‧Package colloid

15‧‧‧開口 15‧‧‧ openings

16‧‧‧屏蔽層 16‧‧‧Shield

20‧‧‧載板 20‧‧‧ Carrier Board

21‧‧‧設置面 21‧‧‧Setting surface

30‧‧‧第一封裝組件 30‧‧‧First package assembly

31‧‧‧第一電子元件 31‧‧‧First electronic component

32‧‧‧第一封裝膠體 32‧‧‧First encapsulant

33、35‧‧‧屏蔽元件 33, 35‧‧‧ Shielding components

34‧‧‧焊球 34‧‧‧ solder balls

351‧‧‧屏蔽底座 351‧‧‧Shield base

352‧‧‧屏蔽蓋 352‧‧‧Shield cover

40‧‧‧第二封裝組件 40‧‧‧Second package assembly

41‧‧‧第二電子元件 41‧‧‧Second electronic components

42‧‧‧第二封裝膠體 42‧‧‧Second encapsulant

50‧‧‧模具 50‧‧‧Mold

51‧‧‧第一模穴 51‧‧‧ first cavity

52‧‧‧第二模穴 52‧‧‧Second cavity

53‧‧‧封裝膠 53‧‧‧Package

圖1:習知半導體封裝件製法於載板的一表面設置第一電子元件、第二電子元件與屏蔽牆的示意圖。 FIG. 1 is a schematic view showing a conventional semiconductor package in which a first electronic component, a second electronic component, and a shield wall are disposed on a surface of a carrier.

圖2:於圖1的載板上形成封裝膠體的示意圖。 Figure 2: Schematic diagram of the formation of an encapsulant on the carrier of Figure 1.

圖3:於圖2的封裝膠體形成開口的示意圖。 Figure 3: Schematic representation of the formation of an opening in the encapsulant of Figure 2.

圖4:習知半導體封裝件的示意圖。 Figure 4: Schematic diagram of a conventional semiconductor package.

圖5:本創作半導體封裝件實施例的示意圖。 Figure 5: Schematic diagram of an embodiment of the present semiconductor package.

圖6:本創作半導體封裝件另一實施例的示意圖。 Figure 6 is a schematic illustration of another embodiment of the present semiconductor package.

圖7:本創作半導體封裝件製法於載板的設置面設置第一電子元件與第二電子元件的示意圖。 FIG. 7 is a schematic view showing the first electronic component and the second electronic component disposed on the mounting surface of the carrier board.

圖8:於圖6的載板上形成第一封裝膠體的示意圖。 Figure 8 is a schematic illustration of the formation of a first encapsulant on the carrier of Figure 6.

圖9:於圖7的第一封裝膠體上形成屏蔽元件之一實施例的示意圖。 Figure 9 is a schematic illustration of one embodiment of forming a shield member on the first encapsulant of Figure 7.

圖10:於圖7的第一封裝膠體上形成屏蔽元件之另一實施例的示意圖。 Figure 10 is a schematic illustration of another embodiment of forming a shield member on the first encapsulant of Figure 7.

圖11:本創作進行模壓的示意圖。 Figure 11: Schematic diagram of the molding of this creation.

請參考圖5,本創作半導體封裝件的實施例包含一載板20、一第一封裝組件30與一第二封裝組件40。 Referring to FIG. 5 , an embodiment of the present semiconductor package includes a carrier 20 , a first package component 30 , and a second package component 40 .

該載板20為線路板而具有導電線路,其種類繁多並為業界的公知常識,在此不加以贅述。該載板20具有一設置面21,該設置面21可為該載板20的頂面或底面。 The carrier board 20 is a circuit board and has a conductive line. The type of the board 20 is a common type of common knowledge in the industry and will not be described herein. The carrier 20 has a mounting surface 21 which can be the top or bottom surface of the carrier 20.

該第一封裝組件30設置於該載板20的設置面21,該第一封裝組件30包含至少一第一電子元件31與一第一封裝膠體32,或進一步包含一屏蔽元件33。該至少一第一電子元件31設置於該載板20的設置面21,其可以打線方式電性連接該載板20上的導電線路,或者以覆晶(flip-chip)方式設置於該載板20的設置面21,圖5是以覆晶方式設置於該載板20的一個第一電子元件31為例,該第一電子元件31通過焊球34而電性連接該載板20上的導電線路。該第一封裝膠體32設置於該載板20的設置面21並包覆該第一電子元件31,該屏蔽元件33係完全包覆該第一封裝膠體32。 The first package component 30 is disposed on the mounting surface 21 of the carrier 20 . The first package component 30 includes at least one first electronic component 31 and a first encapsulant 32 , or further includes a shielding component 33 . The at least one first electronic component 31 is disposed on the mounting surface 21 of the carrier 20, and can be electrically connected to the conductive line on the carrier 20 in a wire-bonding manner, or can be disposed on the carrier in a flip-chip manner. The setting surface 21 of FIG. 5 is an example of a first electronic component 31 that is flip-chip mounted on the carrier 20. The first electronic component 31 is electrically connected to the conductive layer on the carrier 20 by solder balls 34. line. The first encapsulant 32 is disposed on the mounting surface 21 of the carrier 20 and covers the first electronic component 31 . The shielding component 33 completely covers the first encapsulant 32 .

如圖5所示,該屏蔽元件33的一實施例可為一體成型的層狀金屬構件,該屏蔽元件33形成在該第一封裝膠體32的表面並延伸連接到該載板20的設置面21,故該屏蔽元件33係完全包覆該第一封裝膠體32。如圖6所示,該屏蔽元件35的另一實施例可為非一體成型的組件,例如為組合式組件,該屏蔽元件35可包含一屏蔽底座351與一屏蔽蓋352,該屏蔽底座351具有一容置空間,該屏蔽底座351設置於該載板20的設置面21,該第一封裝膠體32與該第一電子元件31位於該屏蔽底座351的該容置空間,該屏蔽蓋352設置於該屏蔽底座351以完全覆蓋該第一封裝膠體32與該第一電子元件31。其中,該屏蔽元件33、35、該屏蔽底座351與該屏蔽蓋352可為銅(Cu)層、鎳(Ni)層、鐵層(Fe)、鋁(Al)層或不鏽鋼層...等製成的構件。如圖5與圖6所示,該屏蔽元件33、35係直接接觸該第一封裝膠體32的頂面與側面。 As shown in FIG. 5, an embodiment of the shielding member 33 may be an integrally formed layered metal member formed on the surface of the first encapsulant 32 and extending to the mounting surface 21 of the carrier 20. Therefore, the shielding member 33 completely covers the first encapsulant 32. As shown in FIG. 6, another embodiment of the shielding member 35 can be a non-integral component, such as a modular assembly. The shielding component 35 can include a shielding base 351 and a shielding cover 352. The shielding base 351 has The shielding base 351 is disposed on the mounting surface 21 of the carrier 20, the first encapsulant 32 and the first electronic component 31 are located in the receiving space of the shielding base 351, and the shielding cover 352 is disposed on the shielding surface 351. The shielding base 351 completely covers the first encapsulant 32 and the first electronic component 31. The shielding member 33, 35, the shielding base 351 and the shielding cover 352 may be a copper (Cu) layer, a nickel (Ni) layer, an iron layer (Fe), an aluminum (Al) layer or a stainless steel layer, etc. Made of components. As shown in FIG. 5 and FIG. 6, the shielding members 33 and 35 directly contact the top surface and the side surface of the first encapsulant 32.

該第二封裝組件40設置於該載板20的設置面21,亦即該第二封裝組件40與該第一封裝組件30設置於該載板20的相同表面,且該第二封裝組件 40可鄰設該第一封裝組件30。該第二封裝組件40包含至少一第二電子元件41與一第二封裝膠體42,該至少一第二電子元件41設置於該載板20的設置面21且與該第一電子元件31分離設置。該第二封裝膠體42設置於該載板20的設置面21並包覆該至少一第二電子元件41,其中,如圖5所示,本創作實施例以一個第二電子元件41為例,且該第二封裝膠體42的側面可鄰設該屏蔽元件33、35的側面,如圖5與圖6所示,該屏蔽元件33、35接觸該第二封裝膠體42的側面。 The second package component 40 is disposed on the mounting surface 21 of the carrier 20, that is, the second package component 40 and the first package component 30 are disposed on the same surface of the carrier 20, and the second package component The first package component 30 can be adjacent to 40. The second package component 40 includes at least one second electronic component 41 and a second package component 42 . The at least one second electronic component 41 is disposed on the mounting surface 21 of the carrier 20 and is disposed separately from the first electronic component 31 . . The second encapsulant 42 is disposed on the mounting surface 21 of the carrier 20 and covers the at least one second electronic component 41. As shown in FIG. 5, the present embodiment uses a second electronic component 41 as an example. The side surface of the second encapsulant 42 can be adjacent to the side of the shielding member 33, 35. As shown in FIG. 5 and FIG. 6, the shielding member 33, 35 contacts the side of the second encapsulant 42.

本創作實施例中,該第一封裝膠體32的電磁波損耗率大於該第二封裝膠體42的電磁波損耗率。舉例而言,該第一封裝膠體32可包含環氧樹脂(epoxy resin)與掺在環氧樹脂內而與環氧樹脂混合的抗電磁干擾材料,或者,該第一封裝膠體32可包含聚合物材料(polymer material)與掺在聚合物材料內而與聚合物材料混合的抗電磁干擾材料;該第二封裝膠體42可為環氧樹脂(epoxy resin)或聚合物材料(polymer material)製成的構件。所述抗電磁干擾材料可為吸波材料或微金屬材料,所述微金屬材料可為鎂或鋁,而該第一封裝膠體32與該第二封裝膠體42整體仍為絕緣體。其中,所述抗電磁干擾材料係用以吸收或反射電磁波,故使含有抗電磁干擾材料的該第一封裝膠體32的電磁波損耗率能大於該第二封裝膠體42的電磁波損耗率。 In the present embodiment, the electromagnetic wave loss rate of the first encapsulant 32 is greater than the electromagnetic wave loss rate of the second encapsulant 42. For example, the first encapsulant 32 may comprise an epoxy resin and an anti-electromagnetic interference material mixed in the epoxy resin and mixed with the epoxy resin, or the first encapsulant 32 may comprise a polymer. A polymer material and an anti-electromagnetic interference material mixed with the polymer material and mixed with the polymer material; the second encapsulant 42 may be made of an epoxy resin or a polymer material. member. The EMI material may be an absorbing material or a micro metal material, and the micro metal material may be magnesium or aluminum, and the first encapsulant 32 and the second encapsulant 42 are still an insulator as a whole. Wherein, the anti-electromagnetic interference material is used for absorbing or reflecting electromagnetic waves, so that the electromagnetic wave loss rate of the first encapsulant 32 containing the anti-electromagnetic interference material can be greater than the electromagnetic wave loss rate of the second encapsulant 42.

根據本創作的結構,因為該第一封裝膠體32與該第二封裝膠體42分別為不同的兩個封裝膠體,故本創作能依照該第一電子元件31與該第二電子元件41對於抗電磁干擾的需求而分別設定該第一封裝膠體32與該第二封裝膠體42的電磁波損耗率,本創作實施例是以該第一電子元件31可為需要抗電磁干擾處理的元件,例如數位積體電路、數位訊號處理器、基頻晶片或射頻晶片...等為例,該第二電子元件12可為收及/或發電磁波構件,所述收及/或發電磁波構件可以天線為例。 According to the structure of the present invention, since the first encapsulant 32 and the second encapsulant 42 are respectively different encapsulants, the present invention can be electromagnetically resistant according to the first electronic component 31 and the second electronic component 41. The electromagnetic wave loss rate of the first encapsulant 32 and the second encapsulant 42 is set separately according to the requirement of interference. In the present embodiment, the first electronic component 31 can be an element that needs anti-electromagnetic interference processing, such as a digital integrated body. For example, a circuit, a digital signal processor, a baseband chip or a radio frequency chip, etc., the second electronic component 12 may be a receiving/transmitting electromagnetic wave component, and the receiving/transmitting electromagnetic wave component may be an antenna.

如此一來,對於該第一電子元件31來說,該第一封裝膠體32能損耗來自於該第二電子元件41與外界環境的電磁波,而能避免該第一電子元件31受到電磁干擾的問題;另一方面,該第二封裝膠體42可不具抗電磁干擾材料,故電磁波損耗率較低,使該第二電子元件41能有效對外輻射電磁波或感應外界電磁波。再者,本創作藉由該屏蔽元件33、35的設置,對於該第一電子元件31來說,該屏蔽元件33、35能進一步屏蔽來自於該第二電子元件41與外界環境的電磁波,因此本創作透過該第一封裝膠體32與該屏蔽元件33、35可有效對該第一電子元件31抗電磁干擾。 In this way, for the first electronic component 31, the first encapsulant 32 can consume electromagnetic waves from the second electronic component 41 and the external environment, and can avoid the electromagnetic interference of the first electronic component 31. On the other hand, the second encapsulant 42 may not have an anti-electromagnetic interference material, so the electromagnetic wave loss rate is low, so that the second electronic component 41 can effectively radiate electromagnetic waves or induce external electromagnetic waves. Furthermore, the present invention, by the arrangement of the shielding elements 33, 35, the shielding elements 33, 35 can further shield electromagnetic waves from the second electronic component 41 from the external environment for the first electronic component 31, The present invention is effective against electromagnetic interference of the first electronic component 31 through the first encapsulant 32 and the shielding members 33, 35.

以下配合製法說明本創作的半導體封裝件,請參考圖7,於一載板20的一設置面21設置至少一第一電子元件31與至少一第二電子元件41,該至少一第一電子元件31與該至少一第二電子元件41為分離設置。本創作實施例僅以一個第一電子元件31與一個第二電子元件41為例說明,但不以此為限。 The semiconductor package of the present invention is described in the following manner. Referring to FIG. 7, at least one first electronic component 31 and at least one second electronic component 41 are disposed on a mounting surface 21 of a carrier 20, and the at least one first electronic component is disposed. 31 is provided separately from the at least one second electronic component 41. The present embodiment is described by taking only one first electronic component 31 and one second electronic component 41 as an example, but is not limited thereto.

請參考圖8,於該載板20的設置面21形成一第一封裝膠體32,且使該第一封裝膠體32包覆該第一電子元件31。請參考圖9,本創作可進一步設置一屏蔽元件33,該屏蔽元件33的一實施例為一體成型的層狀金屬構件,該屏蔽元件33形成在該第一封裝膠體32的表面並延伸連接到該載板20的設置面21,該屏蔽元件33可為濺鍍(sputtering)成形的構件。請參考圖10,該屏蔽元件35的另一實施例可為組合式組件,例如該屏蔽元件35可包含設置在該載板20之設置面21的一屏蔽底座351與設置於該屏蔽底座351的一屏蔽蓋352,其中,該第一封裝膠體32與該第一電子元件31位於該屏蔽底座351內,該屏蔽蓋352設置於該屏蔽底座351以完全覆蓋該第一封裝膠體32與該第一電子元件31。如圖9與圖10所示,該屏蔽元件33、35係直接接觸該第一封裝膠體32的頂面與側面。 Referring to FIG. 8 , a first encapsulant 32 is formed on the mounting surface 21 of the carrier 20 , and the first encapsulant 32 is coated on the first electronic component 31 . Referring to FIG. 9, the present invention can further provide a shielding member 33. One embodiment of the shielding member 33 is an integrally formed layered metal member. The shielding member 33 is formed on the surface of the first encapsulant 32 and is connected to the surface. The shielding surface 33 of the carrier 20 may be a sputtering shaped member. Referring to FIG. 10 , another embodiment of the shielding component 35 can be a combined component. For example, the shielding component 35 can include a shielding base 351 disposed on the setting surface 21 of the carrier 20 and a shielding base 351 disposed on the shielding base 351 . a shielding cover 352, wherein the first encapsulant 32 and the first electronic component 31 are located in the shielding base 351, the shielding cover 352 is disposed on the shielding base 351 to completely cover the first encapsulant 32 and the first Electronic component 31. As shown in FIG. 9 and FIG. 10, the shielding members 33, 35 are in direct contact with the top surface and the side surface of the first encapsulant 32.

請參考圖5,於該載板20的設置面21形成一第二封裝膠體42,且使該第二封裝膠體42包覆該第二電子元件41,完成本創作的半導體封裝件。如圖5所示,該屏蔽元件33接觸該第二封裝膠體42的側面。 Referring to FIG. 5, a second encapsulant 42 is formed on the mounting surface 21 of the carrier 20, and the second encapsulant 42 is wrapped around the second electronic component 41 to complete the inventive semiconductor package. As shown in FIG. 5, the shielding member 33 contacts the side of the second encapsulant 42.

於本創作製法中,該第一封裝膠體32與該第二封裝膠體42可透過模壓方式或點膠方式製造而得,舉例來說,請配合參考圖11,模壓需準備一模具50,該模具50具有對應於該第一電子元件31的第一模穴51與對應於第二電子元件41的第二模穴52,其中該第一模穴51設有封裝膠53,該第二模穴52為空模穴。模壓時將該載板20結合於該模具50,使該第一電子元件31浸入第一模穴51的封裝膠53,且使該第二電子元件41位於該第二模穴52中。是以,當該封裝膠53固化成型,並分離該載板20與模具50,該封裝膠53即成為圖8所示的第一封裝膠體32。而當完成該第一封裝膠體32與圖9或圖10所示的屏蔽元件33、35後,可以點膠方式形成圖5所示的該第二封裝膠體42。 In the authoring method, the first encapsulant 32 and the second encapsulant 42 can be manufactured by molding or dispensing. For example, please refer to FIG. 11 , and a mold 50 is prepared for molding. 50 has a first cavity 51 corresponding to the first electronic component 31 and a second cavity 52 corresponding to the second electronic component 41, wherein the first cavity 51 is provided with an encapsulant 53, the second cavity 52 It is an empty cavity. The carrier 20 is bonded to the mold 50 during molding, so that the first electronic component 31 is immersed in the encapsulant 53 of the first cavity 51, and the second electronic component 41 is placed in the second cavity 52. Therefore, when the encapsulant 53 is cured and the carrier 20 and the mold 50 are separated, the encapsulant 53 becomes the first encapsulant 32 shown in FIG. When the first encapsulant 32 and the shielding members 33 and 35 shown in FIG. 9 or FIG. 10 are completed, the second encapsulant 42 shown in FIG. 5 can be formed in a dispensing manner.

以本創作的製法而言,和先前技術相比,本創作不需在圖3所示的封裝膠體14挖槽以形成開口15,故本創作製法能更為簡化,且成本更低。 In the manufacturing method of the present invention, compared with the prior art, the present invention does not need to be grooved in the encapsulant 14 shown in FIG. 3 to form the opening 15, so that the authoring method can be more simplified and the cost is lower.

需說明的是,本創作僅以該第一電子元件31與該第二電子元件41為例說明,所述半導體封裝件可包含更多電子元件,此為業界的公知常識,在此不加以贅述。 It should be noted that the first electronic component 31 and the second electronic component 41 are exemplified in the present invention. The semiconductor package may include more electronic components, which is common knowledge in the industry, and will not be described herein. .

Claims (20)

一種半導體封裝件,包含:一載板,具有一設置面;一第一封裝組件,設置於該載板的該設置面,該第一封裝組件包含至少一第一電子元件、包覆該至少一第一電子元件的一第一封裝膠體與一屏蔽元件,該第一封裝膠體包含抗電磁干擾材料;以及一第二封裝組件,設置於該載板的該設置面,該第二封裝組件包含至少一第二電子元件與包覆該至少一第二電子元件的一第二封裝膠體,該第一封裝膠體的電磁波損耗率大於該第二封裝膠體的電磁波損耗率;其中,該屏蔽元件係完整包覆該第一封裝膠體並直接接觸該第一封裝膠體的頂面與側面,且接觸該第二封裝膠體的側面。 A semiconductor package comprising: a carrier board having a mounting surface; a first package component disposed on the mounting surface of the carrier board, the first package component comprising at least one first electronic component, covering the at least one a first encapsulant of the first electronic component and a shielding component, the first encapsulant comprises an anti-electromagnetic interference material; and a second package component disposed on the mounting surface of the carrier, the second package component comprising at least a second electronic component and a second encapsulant covering the at least one second electronic component, wherein the first encapsulation colloid has an electromagnetic wave loss rate greater than an electromagnetic wave loss rate of the second encapsulant; wherein the shielding component is a complete package The first encapsulant is covered and directly contacts the top surface and the side surface of the first encapsulant and contacts the side surface of the second encapsulant. 如請求項1所述之半導體封裝件,該第一封裝組件鄰設該第二封裝組件。 The semiconductor package of claim 1, wherein the first package component is adjacent to the second package component. 如請求項2所述之半導體封裝件,該屏蔽元件係完全包覆該第一封裝膠體,且該第二封裝膠體的側面鄰設該屏蔽元件的側面。 The semiconductor package of claim 2, wherein the shielding component completely covers the first encapsulant, and a side of the second encapsulant is adjacent to a side of the shielding component. 如請求項3所述之半導體封裝件,該屏蔽元件為一體成型的層狀金屬構件,該屏蔽元件設置在該第一封裝膠體的表面並延伸連接到該載板的該設置面。 The semiconductor package of claim 3, wherein the shielding member is an integrally formed layered metal member disposed on a surface of the first encapsulant and extending to the mounting surface of the carrier. 如請求項3所述之半導體封裝件,該屏蔽元件為非一體成型的組件。 The semiconductor package of claim 3, wherein the shielding element is a non-integral component. 如請求項5所述之半導體封裝件,該屏蔽元件包含一屏蔽底座與一屏蔽蓋,該屏蔽底座具有一容置空間,該屏蔽底座設置於該載板的該設置面,該第一封裝膠體與該至少一第一電子元件位於該屏蔽底座的該容置空間,該屏蔽蓋設置於該屏蔽底座以覆蓋該第一封裝膠體與該至少一第一電子元件。 The semiconductor package of claim 5, the shielding component comprises a shielding base and a shielding cover, the shielding base has an accommodating space, the shielding base is disposed on the setting surface of the carrier, the first encapsulant The at least one first electronic component is located in the accommodating space of the shielding base, and the shielding cover is disposed on the shielding base to cover the first encapsulant and the at least one first electronic component. 如請求項1至6中任一項所述之半導體封裝件,所述抗電磁干擾材料為吸波材料或微金屬材料。 The semiconductor package of any one of claims 1 to 6, wherein the EMI material is an absorbing material or a micro metal material. 如請求項7所述之半導體封裝件,所述微金屬材料包含鎂或鋁。 The semiconductor package of claim 7, wherein the micro-metal material comprises magnesium or aluminum. 如請求項1所述之半導體封裝件,該至少一第二電子元件為收及/或發電磁波構件。 The semiconductor package of claim 1, wherein the at least one second electronic component is a receiving/transmitting electromagnetic wave member. 如請求項9所述之半導體封裝件,所述收及/或發電磁波構件為天線。 The semiconductor package of claim 9, wherein the receiving/transmitting electromagnetic wave member is an antenna. 一種半導體封裝件的製法,包含:於一載板的一設置面設置至少一第一電子元件與至少一第二電子元件;於該載板的該設置面形成一第一封裝膠體,且使該第一封裝膠體包覆該至少一第一電子元件,該第一封裝膠體包含抗電磁干擾材料;設置一屏蔽元件,該屏蔽元件係完整包覆該第一封裝膠體並直接接觸該第一封裝膠體的頂面與側面;以及於該載板的該設置面形成一第二封裝膠體,且使該第二封裝膠體包覆該至少一第二電子元件,該第一封裝膠體的電磁波損耗率大於該第二封裝膠體的電磁波損耗率,且該屏蔽元件接觸該第二封裝膠體的側面。 A method of manufacturing a semiconductor package, comprising: disposing at least one first electronic component and at least one second electronic component on a mounting surface of a carrier; forming a first encapsulant on the mounting surface of the carrier, and The first encapsulant encapsulates the at least one first electronic component, the first encapsulant comprises an anti-electromagnetic interference material; and a shielding component is disposed, the shielding component completely covers the first encapsulant and directly contacts the first encapsulant a top surface and a side surface; and a second encapsulant formed on the mounting surface of the carrier, and the second encapsulant encapsulates the at least one second electronic component, the first encapsulant having an electromagnetic wave loss ratio greater than the The electromagnetic wave loss rate of the second encapsulant, and the shielding element contacts the side of the second encapsulant. 如請求項11所述之半導體封裝件的製法,該屏蔽元件完全包覆該第一封裝膠體。 The method of fabricating a semiconductor package according to claim 11, wherein the shielding member completely covers the first encapsulant. 如請求項12所述之半導體封裝件的製法,該屏蔽元件為一體成型的層狀金屬構件,該屏蔽元件形成在該第一封裝膠體的表面並延伸連接到該載板的設置面。 The method of fabricating a semiconductor package according to claim 12, wherein the shielding member is an integrally formed layered metal member formed on a surface of the first encapsulant and extending to the mounting surface of the carrier. 如請求項13所述之半導體封裝件的製法,該屏蔽元件為濺鍍成形的構件。 The method of fabricating a semiconductor package according to claim 13, wherein the shielding member is a sputter-formed member. 如請求項12所述之半導體封裝件的製法,進一步設置一屏蔽元件,該屏蔽元件為非一體成型的組件。 In the method of fabricating the semiconductor package of claim 12, a shield member is further provided, the shield member being a non-integral component. 如請求項15所述之半導體封裝件的製法,該屏蔽元件包含一屏蔽底座與一屏蔽蓋,該屏蔽底座具有一容置空間,該屏蔽底座設置於該載板的該設置面,該第一封裝膠體與該至少一第一電子元件位於該屏蔽底座的該容置空間,該屏蔽蓋設置於該屏蔽底座以覆蓋該第一封裝膠體與該至少一第一電子元件。 The method of claim 15, wherein the shielding component comprises a shielding base and a shielding cover, the shielding base has an accommodating space, and the shielding base is disposed on the setting surface of the carrier, the first The encapsulant and the at least one first electronic component are located in the accommodating space of the shielding base, and the shielding cover is disposed on the shielding base to cover the first encapsulant and the at least one first electronic component. 如請求項11至16中任一項所述之半導體封裝件的製法,所述抗電磁干擾材料為吸波材料或微金屬材料。 The method of fabricating a semiconductor package according to any one of claims 11 to 16, wherein the EMI material is an absorbing material or a micro metal material. 如請求項17所述之半導體封裝件的製法,所述微金屬材料包含鎂或鋁。 The method of fabricating the semiconductor package of claim 17, wherein the micro-metal material comprises magnesium or aluminum. 如請求項11所述之半導體封裝件的製法,該至少一第二電子元件為收及/或發電磁波構件。 The method of fabricating the semiconductor package of claim 11, wherein the at least one second electronic component is a receiving/transmitting electromagnetic wave member. 如請求項19所述之半導體封裝件的製法,所述收及/或發電磁波構件為天線。 The method of fabricating the semiconductor package of claim 19, wherein the receiving/transmitting electromagnetic wave member is an antenna.
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