本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。 「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。 為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了實施方式之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於實施方式的內容，而是由申請專利範圍定義。 「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。 為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了實施方式之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於實施方式的內容，而是由申請專利範圍定義。 圖1為包括一致能元件12之一比較性的動態隨機存取記憶體（dynamic random access memory，DRAM）10之示意圖。參照圖1，DRAM 10除了致能元件12，還包括一電源14和一記憶體16。 記憶體16用以存儲資料。記憶體16包括第一記憶庫(bank)160以及第二記憶庫170，其中第一資料庫160及第二資料庫170都可視為多個記憶體單元中之一陣列。第一記憶庫160包括第一次陣列162以及第二次陣列164。第一次陣列162和第二次陣列164各包括一條或多條字元線。第二記憶庫170包括第三次陣列172以及第四次陣列174。第三次陣列172和第四次陣列174各包括一條或多條字元線。 電源14經配置以提供記憶體16足以讓記憶體16在致能時操作之電能。電源14包括彼此獨立之第一電荷幫浦140、第二電荷幫浦142以及第三電荷幫浦144。在一些實施例中，當第一電荷幫浦140、一第二電荷幫浦142以及一第三電荷幫浦144每一者被致能時，第一電荷幫浦140、一第二電荷幫浦142以及一第三電荷幫浦144每一者輸出相同量之電能。然而，本揭露並不限於此。 致能元件12僅能以相同之方式操作所有的第一電荷幫浦140、第二電荷幫浦142以及第三電荷幫浦144。換言之，致能元件12無法以不同方式個別地操作第一電荷幫浦140、第二電荷幫浦142以及第三電荷幫浦144。例如，當致能元件12致能所有的第一電荷幫浦140、第二電荷幫浦142以及第三電荷幫浦144時，所有的第一電荷幫浦140、第二電荷幫浦142以及第三電荷幫浦144皆被致能，無任一禁能。這種缺點可能係受限於致能元件12的簡單設計而引起。 更詳細地說，致能元件12無法獲得一資訊，該資訊係關於在第一次陣列160、第二次陣列162、第三次陣列170以及第四次陣列172中被操作的次陣列之數量。再者，致能元件12無法基於該資訊決定輸出多少量的電能。因而，致能元件12迫以相同方式操作所有的第一電荷幫浦140、第二電荷幫浦142以及第三電荷幫浦144。如此，由所有的第一電荷幫浦140、第二電荷幫浦142以及第三電荷幫浦144輸出之電能是不能調整的，所以電能無法被管理。結果，DRAM 10不能提供一電源管理功能，電能的使用上相對低效。 特別是當在第一次陣列160、第二次陣列162、第三次陣列170和第四次陣列172中之一個或多個不被操作之情況下，電源14仍輸出與所有的第一次陣列160、第二次陣列162、第三次陣列170和第四次陣列172都被操作時的相同電能，這部分參照圖2至圖4，將詳細描述。亦即，電源14輸出大於記憶體16所需之電能。電能的使用上相對低效。 圖2為圖1所示之比較DRAM 10之一操作示意圖。參照圖2，致能元件12因應於記憶體16一操作事件，例如藉著提供致能信號EN至第一電荷幫浦140、第二電荷幫浦142和第三電荷幫浦144，致能所有的第一電荷幫浦140、第二電荷幫浦142和第三電荷幫浦144。如此，所有的第一電荷幫浦140、第二電荷幫浦142和第三電荷幫浦144皆被致能而合併一起輸出（提供）記憶體16之電能。 圖3為圖1所示之比較DRAM 10另一操作示意圖。參照圖3，致能元件12因應於記憶體16一操作事件，儘管第四次陣列174不被操作，但仍致能所有的第一電荷幫浦140、第二電荷幫浦142以及第三電荷幫浦144。致能元件12使電源14輸出如圖2實施例中所輸出之相同電能。電源14輸出比記憶體16需要更大之電能。電能的使用上相對低效。 圖4為圖1所示之該比較DRAM 10之又另一操作示意圖。參照圖4，致能元件12因應於記憶體16一操作事件，儘管第三次陣列172和第四次陣列174不被操作，但仍致能所有的第一電荷幫浦140、第二電荷幫浦142和第三電荷幫浦144。致能元件12使電源14輸出如圖2實施例中所輸出之相同電能。電源14輸出比記憶體16需要更大之電能。電能的使用上相對低效。 圖5為根據本揭露之一些實施例，包括一控制元件22之動態隨機存取記憶體(DRAM)20示意圖。參照圖5，DRAM 20類似於圖1中所示之DRAM 10，差別在於DRAM 20包括控制元件22，以及DRAM 20包括包含一第一電荷幫浦240、一第二電荷幫浦242和一第三電荷幫浦244的一電源24。 控制元件22經配置以獲得一資訊，該資訊係關於第一次陣列162、第二次陣列164、第三次陣列172和第四次陣列174中之被操作的次陣列之數量。此外，控制元件22基於該資訊產生一決定，該決定係輸出多少量的電能，其細節將描述如下。更詳細地說，控制元件22能以不同的方式，個別地操作第一電荷幫浦240、第二電荷幫浦242和第三電荷幫浦244。例如，當禁能第三電荷幫浦244時，控制元件22可致能第一電荷幫浦240和第二電荷幫浦242。如此，由電源24所輸出之電能的量是可調整的，所以電能可以被管理。於是，DRAM 20可提供電源管理之功能，且電能的使用上相對是有效率的。在本實施例中，控制元件22是位於DRAM 20內中之一元件；然而，本揭露並不限於此。在另一個實施例中，控制元件22是位於DRAM 20外部之DRAM控制器上的一處理器。在一些實施例中，控制元件22是一組合邏輯。 基於控制元件22之決定，電源24經配置以輸出一結果量的電能。例如，如圖6所示，第一電荷幫浦240、第二電荷幫浦42和第三電荷幫浦244合併一起輸出一第一電能。 抑或是，第一電荷幫浦240獨自輸出小於第一電能之一第二電能，而第二電荷幫浦242或第三電荷幫浦244沒有輸出電能。又或者是，第一電荷幫浦240和第二電荷幫浦242合併一起輸出小於第一電能且大於第二電能之一第三電能，而第三電荷幫浦244沒有輸出電能，如圖7和圖8所示。在一實施例中，第一電荷幫浦240、第二電荷幫浦242和第三電荷幫浦244彼此獨立。 圖6為根據本揭露之一些實施例，如圖5所示之DRAM 20之操作示意圖。參照圖6，第一次陣列162、第二次陣列164、第三次陣列172、第四次陣列174被操作。控制元件22獲得一資訊，該資訊係關於被操作的次陣列之數量，且該資訊反映該被操作的次陣列之數量是4。控制元件22，基於反映被操作的次陣列之數量是4之該資訊，決定輸出相對高電能之第一電能。結果，控制元件22藉著致能所有第一電荷幫浦240、第二電荷幫浦242和第三電荷幫浦244，以增加被致能電荷幫浦之數量。第一電荷幫浦240、第二電荷幫浦242和第三電荷幫浦244合併一起輸出至（提供）記憶體16一結果量的電能，例如第一電能。控制元件22決定輸出第一電能所基於的被操作的次陣列之數量的4僅作為範例。同樣地，經配置以輸出第一電能之被致能電荷幫浦之數量的3也僅作為範例。本揭露並不限於此。上述聲明旨在表示當被操作的次陣列之數量相對較多時，由電源24所輸出之電能則相對較多。 在一實施例中，控制元件22經配置以接收一位址，該位址指出被操作的記憶庫之被操作的次陣列。該位址指示哪個記憶庫的哪個次陣列被操作。在圖6之實施例中，控制元件22分別接收第一次陣列162、第二次陣列164、第三次陣列172和第四次陣列174之位址ADDR1、ADDR2、ADDR3、ADDR4。位址ADDR1位於第一次陣列162上，其指示第一記憶庫160之第一次陣列162將被操作；位址ADDR2位於第二次陣列164上，其指示第一記憶庫160之第二次陣列164將被操作，依此類推。在一個實施例中，控制元件22包括用以記錄被操作的次陣列之位址之一表，其經配置以例如記錄位址ADDR1、ADDR2、ADDR3、ADDR4。 不但如此，控制元件22基於該位址，獲得關於被操作的次陣列之數量之該資訊。更詳細地，在一實施例中，控制元件22包括計數器（未示出）。計數器經配置以計數被操作的次陣列之位址之數量。例如，在本實施例中，由於計數器接收到四個不同次陣列162、164、172和174之四個位址ADDR1、ADDR2、ADDR3和ADDR4，所以計數數量為4。如此，控制元件22基於來自該計數器之該計數數量獲得該資訊。 此外，控制元件22基於一數量比與由一最高端點和一最低端點所定義之一比率範圍之間的比較，來決定輸出多少量的電能，其中該數量比為被操作的次陣列的數量比上次陣列之總數的比例。例如，為了易於討論，在接下來的討論中，假設最低端點大約是0.25，而最高端點大約是1。 在本實施例中，控制元件22判斷出一數量比為（4/4），其等於最高端點1，其中該數量比之分母表示次陣列之總數，且該數量比之分子則表示被操作的次陣列之數量。因此，控制元件22決定輸出相對較高電能之一第一電能。 圖7為根據本揭露之一些實施例，如圖5所示之DRAM 20之另一操作示意圖。遵循圖6中之實施例中所述之假設。參照圖7，第四次陣列174不被操作，而第一次陣列162、第二次陣列164和第三次陣列172被操作。控制元件22獲得一資訊，該資訊係關於被操作次陣列之數量，且該資訊反映被操作的次陣列之數量是3。基於反映出被操作的次陣列之數量是3之該資訊，控制元件22決定輸出作為中等電能之一第三電能。結果，控制元件22禁能第三電荷幫浦244，但致能第一電荷幫浦240和第二電荷幫浦242。第一電荷幫浦240和第二電荷幫浦242合併一起輸出（提供）記憶體陣列16該結果量的電能，也就是第三電能。 在一實施例中，控制元件22分別接收第一次陣列162、第二次陣列164和第三次陣列172之位址ADDR1、ADDR2和ADDR3。由於控制元件22沒有接收到位於第四次陣列174上之位址ADDR4，所以控制元件22判斷出第四次陣列174不被操作。由於控制元件22接收到位址ADDR1、ADDR2和ADDR3（這反映會有三個次陣列162、164和174被存取），計數器的計數數量為3。結果，控制元件22基於計數數量的3獲得該資訊。控制元件22判定出數量比為（3/4），其小於最高端點1且大於最低端點0.25，因此控制元件22決定輸出中等電能之第三電能。 圖8為根據本揭露之一些實施例，如圖5所示之DRAM之又另一操作示意圖。仍然遵循在圖6之實施例中所述之假設。參照圖8，第三次陣列172和第四次陣列174不被操作，而第一次陣列162和第二次陣列164被操作。控制元件22獲得一資訊，該資訊係關於被操作的次陣列之數量，且該資訊反映被操作的次陣列之數量是2。基於反映出被操作的次陣列之數量是2之該資訊，控制元件22決定輸出如圖7之實施例中所輸出相同電能之第三電能。於是，控制元件22，藉由禁能第三電荷幫浦244但致能第一電荷幫浦240和第二電荷幫浦242，保持等量之被致能電荷幫浦，如圖7之實施例中。第一電荷幫浦240和第二電荷幫浦242合併一起輸出（提供）記憶體陣列16該結果量的電能，亦即第三電能。 在一實施例中，控制元件22分別接收第一次陣列162和第二次陣列164之位址ADDR1和ADDR2。由於控制元件22沒有接收到位於第四次陣列174上之位址ADDR4和位於第三次陣列172上之位址ADDR3，所以控制元件22判斷出第四次陣列174和第三次陣列172不被操作。由於控制元件22接收到位址ADDR1和ADDR2（這反映會有兩個被存取之次陣列162和164），計數器的計數數量為2。於是，控制元件22基於計數數量的2獲得該資訊。控制元件22判斷出數量比為（2/4），其小於最高端點1且大於最低端點0.25，因此控制元件22決定輸出第三電能 圖9為根據本揭露之一些實施例，如圖5所示之DRAM 20之又再另一操作示意圖。依循在圖6之實施例中所述之假設。參照圖9，在第二次陣列164、第三次陣列172和第四次陣列174不被操作，但第一次陣列162被操作。控制元件22獲得一資訊，該資訊係關於被操作的次陣列之數量，且該資訊反映被操作的次陣列之數量是1。基於反映出被操作的次陣列之數量是2之該資訊，控制元件22決定輸出第二電能。結果，控制元件22，藉由禁能第二電荷幫浦242和第三電荷幫浦244及致能第一電荷幫浦240，減少被致能電荷幫浦之數量。只有第一電荷幫浦240獨自輸出（提供）記憶體陣列16結果量的電能，即第二電能。 在一個實施例中，控制元件22接收第一次陣列162之位址ADDR1。由於控制元件22沒有接收到位於第四次陣列174上之位址ADDR4、位於第三次陣列172上之位址ADDR3和位於第二次陣列164上之位址ADDR2，所以控制元件22判斷出第四次陣列174、第三次陣列172和第二次陣列164不操作。由於控制元件22接收位址ADDR1（這反映會有一個次陣列162要被存取），所以計數器的計數數量為1。如此，控制元件22基於計數數量的1獲得該資訊。控制元件22判定出數量比為（1/4），其等於最低端點0.25，因此控制元件22決定輸出第二電能。 從圖6至圖9之實施例，由於控制元件22能夠獲得一資訊，該資訊係關於被操作的次陣列之數量，且基於該資訊決定輸出多少量的電能，所以藉著電源24所輸出之電能是可調整的，因此可以被管理。於是，DRAM 20可提供一電源管理之功能，且電能的使用上相對有效率。特別是當被操作的次陣列之數量相對較低時，電源24可以輸出相對較低之電能。電能的使用上相對有效率。 圖10是根據本揭露之一些實施例，操作DRAM之一方法30的流程圖。參照圖10，方法30包括操作31、32、34和36。方法30開始於操作31，於其中提供複數個記憶庫。該等記憶庫各包括複數個次陣列。記憶庫用以存儲資料。方法30繼續於操作32，於其中獲得一資訊，該資訊係關於被操作的次陣列之數量。方法30接著到操作34，於其中基於該資訊產生一決定，該決定係輸出多少量的電能。當被操作的次陣列之數量相對較高時，所輸出之電能則相對較大，反之亦然。接續操作34，在操作36中，基於該決定輸出一結果量的電能。藉著使用本揭露之方法30，當被操作的次陣列之數量相對較低時，輸出相對低之電能。電能的使用上相對有效率。 圖11為根據本揭露之一些實施例，如圖10所示方法30之操作32流程圖。參照圖11，操作32包括操作320、322、324、326和328。操作32開始於操作320，於其中判斷一數量比是否大於或等於一比例範圍之一最高端點，其中該數量比係該等次陣列中被操作的次陣列之數量比上該等次陣列之數量的一比例。如果是肯定的話，則操作32進行到操作322，於其中決定輸出一相對較高電能之第一電能。如果是否定的話，則操作32進行至操作324。 在操作324中，判斷該數量比是否小於或等於該比例範圍之一最低端點。如果是肯定的話，則操作32進行到操作326。在操作326中，決定輸出小於該第一電能之一第二電能。如果是否定的話，則操作324進行到操作328，並於其中決定輸出大於第二電能且小於第一電能之一第三電能。 圖12為根據本揭露之一些實施例，還包括一分配元件44之一動態隨機存取存儲器（DRAM）40之示意圖。參照圖12，DRAM 40類似於參照圖5中所繪示出之DRAM 20，差別在於DRAM 40包括分配元件44，以及包括表420之控制元件42外。如前所述，表420用以記錄所接收之位址。此外，表420反映出每個記憶庫中之被操作的次陣列之數量。例如，參照圖7，與圖7之實施例相關聯之表420，如以下表1所示。
<TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> </td><td> 被操作的次陣列之數量 </td></tr><tr><td> 記憶庫 160 </td><td> 2 </td></tr><tr><td> 記憶庫170 </td><td> 1 </td></tr></TBODY></TABLE>表 1 基於表420，分配元件44用以分配結果量的電能至記憶庫160和記憶庫170。更詳細地，參照圖2，在記憶庫160中被操作的次陣列之數量大於在記憶庫170中之數量。據此，分配元件44分配比第二記憶庫170更多之電能至第一記憶庫160。總而言之，依這樣的分配方式，分配元件44分配結果量的電能至記憶庫。分配至記憶庫的電能的量正相關於被操作的次陣列之數量。 圖13為根據本揭露之一些實施例，操作DRAM之一方法50流程圖。參照圖13，方法50類似於參照圖10所繪示之方法10，差別在於方法50包括操作52、54和56外。在操作52中，接收複數個位址。每個位址指示哪個記憶庫之哪個次陣列被操作。在操作54中，基於該位址，獲得一資訊，該資訊係關於被操作的次陣列之數量。在操作56中，結果量的電能依照一分配方式被分配至記憶庫，該分配方式包括分配至記憶庫的電能的量正相關於被操作的次陣列之數量。 在本揭露中，控制元件22經配置以獲得一資訊，該資訊係關於被操作的次陣列之數量，且基於該資訊決定輸出多少量的電能。如此，由電源24輸出之電能是可調整的，因此可以被管理。結果，DRAM 20可提供一電源管理之功能，且電能的使用上相對有效率。特別是當該被操作的次陣列之數量相對較低時，電源24可以輸出一相對較低之電能。電能的使用上相對有效率。 相比之下，在比較性的DRAM 10中，致能元件12不能獲得一資訊，該資訊係關於被操作的次陣列之數量。再者，致能元件12不能基於該資訊來決定要輸出多少量的電能。所以，由所有的第一電荷幫浦140、第二電荷幫浦142和第三電荷幫浦144輸出之電能是不可調整的，因此不能被管理。結果，DRAM 10不能提供電源管理之功能，且電能的使用上相對低效。特別是在第一次陣列160、第二次陣列162、第三次陣列170和第四次陣列172中之一個或多個不操作之情況下，電源14仍輸出與在所有的第一次陣列160、第二次陣列162、第三次陣列170和第四次陣列172操作之情況下相同之電能。亦即，電源14輸出比記憶體16需要之更多之電能。電能的使用上相對低效。 本揭露之一實施例提供一種DRAM。該DRAM包括複數個記憶庫、一電源、一控制元件。該等記憶庫各包括複數個次陣列。該控制元件經配置以獲得一資訊。該資訊係關於該等次陣列中被操作的次陣列之數量。該控制元件基於該資產生一決定，該決定係輸出多少量的電能，其中該電源基於該控制元件之該決定輸出一結果量的電能。 本揭露之另一實施例提供一種動態隨機存取記憶體之電源管理方法。該電源管理方法包括提供複數個記憶庫，該等記憶庫各包括複數個次陣列；獲得一資訊，該資訊係關於在該等次陣列中被操作的次陣列之數量；基於該資訊，產生一決定，其中該決定係輸出多少量的電能；以及基於該決定，輸出一結果量的電能。 雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。 再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
The following description of this disclosure is accompanied by the drawings incorporated in and constitutes a part of the description to explain the embodiment of this disclosure, but this disclosure is not limited to this embodiment. In addition, the following embodiments can be appropriately integrated with the following embodiments to complete another embodiment. "One embodiment", "embodiment", "exemplified embodiment", "other embodiment", "another embodiment", etc. refer to the embodiment described in this disclosure may include specific features, structures, or characteristics, however Not every embodiment must include the particular feature, structure, or characteristic. Furthermore, the repeated use of the phrase "in the embodiment" does not necessarily refer to the same embodiment, but may be the same embodiment. In order that this disclosure may be fully understood, the following description provides detailed steps and structures. Obviously, the implementation of this disclosure does not limit the specific details known to those skilled in the art. In addition, the known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. The preferred embodiments of the present disclosure are detailed below. However, in addition to the embodiments, the disclosure can be widely implemented in other embodiments. The scope of this disclosure is not limited to the content of the embodiments, but is defined by the scope of patent application. "One embodiment", "embodiment", "exemplified embodiment", "other embodiment", "another embodiment", etc. refer to the embodiment described in this disclosure may include specific features, structures, or characteristics, however Not every embodiment must include the particular feature, structure, or characteristic. Furthermore, the repeated use of the phrase "in the embodiment" does not necessarily refer to the same embodiment, but may be the same embodiment. In order that this disclosure may be fully understood, the following description provides detailed steps and structures. Obviously, the implementation of this disclosure does not limit the specific details known to those skilled in the art. In addition, the known structures and steps are not described in detail, so as not to unnecessarily limit the present disclosure. The preferred embodiments of the present disclosure are detailed below. However, in addition to the embodiments, the disclosure can be widely implemented in other embodiments. The scope of this disclosure is not limited to the content of the embodiments, but is defined by the scope of patent application. FIG. 1 is a schematic diagram of a comparative dynamic random access memory (DRAM) 10 including one of the uniform energy elements 12. Referring to FIG. 1, in addition to the enabling element 12, the DRAM 10 further includes a power source 14 and a memory 16. The memory 16 is used for storing data. The memory 16 includes a first memory bank 160 and a second memory bank 170. The first data bank 160 and the second data bank 170 can both be regarded as an array of a plurality of memory cells. The first memory bank 160 includes a first array 162 and a second array 164. Each of the first array 162 and the second array 164 includes one or more word lines. The second memory bank 170 includes a third array 172 and a fourth array 174. The third array 172 and the fourth array 174 each include one or more word lines. The power source 14 is configured to provide power to the memory 16 sufficient for the memory 16 to operate when enabled. The power source 14 includes a first charge pump 140, a second charge pump 142, and a third charge pump 144 which are independent of each other. In some embodiments, when each of the first charge pump 140, a second charge pump 142, and a third charge pump 144 is enabled, the first charge pump 140, a second charge pump 140, and a second charge pump 144 are each enabled. Each of 142 and a third charge pump 144 outputs the same amount of power. However, this disclosure is not limited to this. The enabling element 12 can only operate all of the first charge pump 140, the second charge pump 142, and the third charge pump 144 in the same manner. In other words, the enabling element 12 cannot individually operate the first charge pump 140, the second charge pump 142, and the third charge pump 144 in different ways. For example, when the enabling element 12 enables all of the first charge pump 140, the second charge pump 142, and the third charge pump 144, all the first charge pumps 140, the second charge pump 142, and the first charge pump 140, All three charge pumps 144 are enabled without any disable. This disadvantage may be caused by the simple design of the enabling element 12. In more detail, the enabling element 12 cannot obtain information about the number of sub-arrays operated in the first array 160, the second array 162, the third array 170, and the fourth array 172. . Furthermore, the enabling element 12 cannot decide how much electric energy to output based on the information. Therefore, the enabling element 12 is forced to operate all of the first charge pump 140, the second charge pump 142, and the third charge pump 144 in the same manner. In this way, the electric energy output by all of the first charge pump 140, the second charge pump 142, and the third charge pump 144 cannot be adjusted, so the power cannot be managed. As a result, the DRAM 10 cannot provide a power management function, and the use of power is relatively inefficient. Especially when one or more of the first array 160, the second array 162, the third array 170, and the fourth array 172 are not operated, the power source 14 still outputs the same output voltage as all the first arrays. The same power when the array 160, the second array 162, the third array 170, and the fourth array 172 are operated. This part will be described in detail with reference to FIGS. 2 to 4. That is, the power source 14 outputs more power than the memory 16 requires. The use of electrical energy is relatively inefficient. FIG. 2 is a schematic diagram of an operation of the comparative DRAM 10 shown in FIG. 1. Referring to FIG. 2, the enabling element 12 responds to an operation event of the memory 16, for example, by providing an enabling signal EN to the first charge pump 140, the second charge pump 142, and the third charge pump 144, all of them are enabled. The first charge pump 140, the second charge pump 142, and the third charge pump 144. In this way, all of the first charge pump 140, the second charge pump 142, and the third charge pump 144 are enabled and combined to output (provide) the power of the memory 16. FIG. 3 is another schematic diagram of the comparison DRAM 10 shown in FIG. 1. Referring to FIG. 3, the enabling element 12 is in response to an operation event of the memory 16. Although the fourth array 174 is not operated, all the first charge pumps 140, the second charge pumps 142, and the third charges are enabled. Bangpu 144. The enabling element 12 causes the power source 14 to output the same electrical energy as that output in the embodiment of FIG. 2. The power source 14 requires more power than the memory 16. The use of electrical energy is relatively inefficient. FIG. 4 is another schematic operation diagram of the comparative DRAM 10 shown in FIG. 1. Referring to FIG. 4, in response to an operation event of the memory 16, although the third array 172 and the fourth array 174 are not operated, all the first charge pumps 140 and the second charge pumps are enabled. PU 142 and third charge pump 144. The enabling element 12 causes the power source 14 to output the same electrical energy as that output in the embodiment of FIG. 2. The power source 14 requires more power than the memory 16. The use of electrical energy is relatively inefficient. FIG. 5 is a schematic diagram of a dynamic random access memory (DRAM) 20 including a control element 22 according to some embodiments of the present disclosure. 5, the DRAM 20 is similar to the DRAM 10 shown in FIG. 1, except that the DRAM 20 includes a control element 22, and the DRAM 20 includes a first charge pump 240, a second charge pump 242, and a third A power source 24 of the charge pump 244. The control element 22 is configured to obtain information about the number of sub-arrays operated in the first array 162, the second array 164, the third array 172, and the fourth array 174. In addition, the control element 22 generates a decision based on the information, and the decision is how much electric energy is output, the details of which will be described below. In more detail, the control element 22 can individually operate the first charge pump 240, the second charge pump 242, and the third charge pump 244 in different ways. For example, when the third charge pump 244 is disabled, the control element 22 may enable the first charge pump 240 and the second charge pump 242. In this way, the amount of power output by the power source 24 is adjustable, so the power can be managed. Therefore, the DRAM 20 can provide a power management function, and the use of power is relatively efficient. In the present embodiment, the control element 22 is one of the elements located in the DRAM 20; however, the disclosure is not limited thereto. In another embodiment, the control element 22 is a processor on a DRAM controller external to the DRAM 20. In some embodiments, the control element 22 is a combinational logic. Based on the decision of the control element 22, the power source 24 is configured to output a resulting amount of power. For example, as shown in FIG. 6, the first charge pump 240, the second charge pump 42, and the third charge pump 244 are combined to output a first electric energy. Alternatively, the first charge pump 240 alone outputs a second power that is less than one of the first power, and the second charge pump 242 or the third charge pump 244 does not output power. Or alternatively, the first charge pump 240 and the second charge pump 242 are combined to output a third power that is less than the first power and larger than the second power, and the third charge pump 244 does not output power, as shown in FIG. Figure 8 shows. In one embodiment, the first charge pump 240, the second charge pump 242, and the third charge pump 244 are independent of each other. FIG. 6 is an operation diagram of the DRAM 20 shown in FIG. 5 according to some embodiments of the present disclosure. Referring to FIG. 6, the first-time array 162, the second-time array 164, the third-time array 172, and the fourth-time array 174 are operated. The control element 22 obtains information about the number of operated sub-arrays, and the information reflects that the number of operated sub-arrays is four. The control element 22 decides to output the first electric energy with a relatively high electric energy based on the information reflecting that the number of operated sub-arrays is four. As a result, the control element 22 increases the number of enabled charge pumps by enabling all of the first charge pumps 240, the second charge pumps 242, and the third charge pumps 244. The first electric charge pump 240, the second electric charge pump 242, and the third electric charge pump 244 are combined to output (provide) a quantity of electric energy to the memory 16, such as the first electric energy. The control element 22 decides 4 that is the number of operated sub-arrays on which the first electric energy is outputted as an example. Similarly, 3, which is the number of enabled charge pumps configured to output the first electrical energy, is only an example. This disclosure is not limited to this. The above statement is intended to indicate that when the number of sub-arrays being operated is relatively large, the power output by the power source 24 is relatively large. In one embodiment, the control element 22 is configured to receive a bit address that indicates the sub-array of the memory bank being operated on. This address indicates which subarray of which bank is operated. In the embodiment of FIG. 6, the control element 22 receives the addresses ADDR1, ADDR2, ADDR3, and ADDR4 of the first array 162, the second array 164, the third array 172, and the fourth array 174, respectively. The address ADDR1 is located on the first array 162, which indicates that the first array 162 of the first bank 160 will be operated; the address ADDR2 is located on the second array 164, which indicates the second time of the first bank 160 The array 164 will be operated, and so on. In one embodiment, the control element 22 includes a table for recording the addresses of the operated sub-arrays, which is configured to record the addresses ADDR1, ADDR2, ADDR3, ADDR4, for example. Moreover, based on the address, the control element 22 obtains this information about the number of sub-arrays operated. In more detail, in one embodiment, the control element 22 includes a counter (not shown). The counter is configured to count the number of addresses of the sub-arrays being operated. For example, in this embodiment, since the counter receives four addresses ADDR1, ADDR2, ADDR3, and ADDR4 of four different sub-arrays 162, 164, 172, and 174, the number of counts is four. As such, the control element 22 obtains the information based on the counted number from the counter. In addition, the control element 22 determines how much electrical energy is output based on a comparison between a quantity ratio and a ratio range defined by a highest endpoint and a lowest endpoint, where the quantity ratio is the The ratio of the number to the total number of the last array. For example, for ease of discussion, in the following discussion, assume that the lowest endpoint is approximately 0.25 and the highest endpoint is approximately 1. In this embodiment, the control element 22 determines that a quantity ratio is (4/4), which is equal to the highest end point 1. The denominator of the quantity ratio represents the total number of the sub-arrays, and the numerator of the quantity ratio represents the operation. The number of secondary arrays. Therefore, the control element 22 decides to output a first electric energy of a relatively high electric energy. FIG. 7 is another operation diagram of the DRAM 20 shown in FIG. 5 according to some embodiments of the present disclosure. The assumptions described in the example in FIG. 6 are followed. Referring to FIG. 7, the fourth-time array 174 is not operated, and the first-time array 162, the second-time array 164, and the third-time array 172 are operated. The control element 22 obtains information about the number of operated sub-arrays, and the information reflects that the number of operated sub-arrays is three. Based on the information reflecting that the number of operated sub-arrays is three, the control element 22 decides to output the third power as one of the medium powers. As a result, the control element 22 disables the third charge pump 244, but enables the first charge pump 240 and the second charge pump 242. The first charge pump 240 and the second charge pump 242 are combined to output (provide) the resulting amount of power of the memory array 16, that is, the third power. In one embodiment, the control element 22 receives the addresses ADDR1, ADDR2, and ADDR3 of the first array 162, the second array 164, and the third array 172, respectively. Since the control element 22 does not receive the address ADDR4 on the fourth array 174, the control element 22 determines that the fourth array 174 is not operated. Since the control element 22 receives the addresses ADDR1, ADDR2, and ADDR3 (this reflects that three sub-arrays 162, 164, and 174 will be accessed), the counter counts to three. As a result, the control element 22 obtains the information based on the counted number of 3. The control element 22 determines that the quantity ratio is (3/4), which is less than the highest end point 1 and greater than the lowest end point 0.25. Therefore, the control element 22 decides to output the third electric energy of medium electric energy. FIG. 8 is still another operation diagram of the DRAM shown in FIG. 5 according to some embodiments of the present disclosure. The assumptions described in the embodiment of FIG. 6 are still followed. Referring to FIG. 8, the third-time array 172 and the fourth-time array 174 are not operated, and the first-time array 162 and the second-time array 164 are operated. The control element 22 obtains information about the number of sub-arrays being operated, and the information reflects that the number of sub-arrays being operated is two. Based on the information reflecting that the number of operated sub-arrays is two, the control element 22 decides to output the third power with the same power as the output in the embodiment of FIG. 7. Therefore, the control element 22, by disabling the third charge pump 244 but enabling the first charge pump 240 and the second charge pump 242, maintains an equal amount of the enabled charge pump, as shown in the embodiment of FIG. 7 in. The first charge pump 240 and the second charge pump 242 are combined to output (provide) the resulting amount of power of the memory array 16, that is, the third power. In one embodiment, the control element 22 receives the addresses ADDR1 and ADDR2 of the first array 162 and the second array 164, respectively. Since the control element 22 does not receive the address ADDR4 on the fourth array 174 and the address ADDR3 on the third array 172, the control element 22 determines that the fourth array 174 and the third array 172 are not operating. Since the control element 22 receives the addresses ADDR1 and ADDR2 (this reflects that there will be two accessed sub-arrays 162 and 164), the counter counts to two. The control element 22 then obtains this information based on the counted number of two. The control element 22 determines that the quantity ratio is (2/4), which is less than the highest end point 1 and greater than the lowest end point 0.25. Therefore, the control element 22 decides to output the third power. FIG. 9 shows some embodiments according to the present disclosure, as shown in FIG. 5. The DRAM 20 is shown as yet another operation. Follow the assumptions described in the embodiment of FIG. 6. Referring to FIG. 9, the second array 164, the third array 172, and the fourth array 174 are not operated, but the first array 162 is operated. The control element 22 obtains information about the number of sub-arrays being operated, and the information reflects that the number of sub-arrays being operated is one. Based on the information reflecting that the number of operated sub-arrays is two, the control element 22 decides to output the second power. As a result, the control element 22 reduces the number of enabled charge pumps by disabling the second charge pump 242 and the third charge pump 244 and enabling the first charge pump 240. Only the first charge pump 240 independently outputs (provides) the amount of power of the memory array 16 as the second power. In one embodiment, the control element 22 receives the address ADDR1 of the first array 162. Since the control element 22 does not receive the address ADDR4 on the fourth array 174, the address ADDR3 on the third array 172, and the address ADDR2 on the second array 164, the control element 22 determines that the The quad array 174, the third array 172, and the second array 164 are not operational. Since the control element 22 receives the address ADDR1 (this reflects that there will be a sub-array 162 to be accessed), the counter counts as one. As such, the control element 22 obtains the information based on the counted number of 1. The control element 22 determines that the quantity ratio is (1/4), which is equal to the lowest endpoint 0.25, so the control element 22 decides to output the second electric energy. From the embodiment of FIG. 6 to FIG. 9, since the control element 22 can obtain information, the information is about the number of sub-arrays being operated, and based on the information, it determines how much electric energy is output. The electrical energy is adjustable so it can be managed. Therefore, the DRAM 20 can provide a power management function, and the use of power is relatively efficient. Especially when the number of operated sub-arrays is relatively low, the power source 24 can output relatively low power. The use of electrical energy is relatively efficient. FIG. 10 is a flowchart of a method 30 of operating a DRAM according to some embodiments of the disclosure. Referring to FIG. 10, the method 30 includes operations 31, 32, 34, and 36. The method 30 begins at operation 31 in which a plurality of banks are provided. The banks each include a plurality of sub-arrays. Memory is used to store data. The method 30 continues with operation 32 in which it obtains information about the number of sub-arrays being operated on. The method 30 then proceeds to operation 34, where a decision is generated based on the information, the decision being how much electrical energy is output. When the number of operated sub-arrays is relatively high, the power output is relatively large, and vice versa. Continuing with operation 34, in operation 36, a result amount of power is output based on the decision. By using the method 30 of the present disclosure, when the number of operated sub-arrays is relatively low, relatively low power is output. The use of electrical energy is relatively efficient. FIG. 11 is a flowchart of operations 32 of the method 30 shown in FIG. 10 according to some embodiments of the present disclosure. 11, operation 32 includes operations 320, 322, 324, 326, and 328. Operation 32 begins at operation 320, in which it is determined whether a quantity ratio is greater than or equal to one of the highest endpoints of a range of ratios, where the quantity ratio is the number of sub-arrays operated in the sub-arrays compared to the number of sub-arrays A proportion of the quantity. If it is affirmative, operation 32 proceeds to operation 322, where it is decided to output a first electrical energy of a relatively high electrical energy. If negative, operation 32 proceeds to operation 324. In operation 324, it is determined whether the number ratio is less than or equal to one of the lowest endpoints of the ratio range. If yes, operation 32 proceeds to operation 326. In operation 326, it is determined to output a second power that is less than one of the first power. If it is negative, operation 324 proceeds to operation 328, where it is decided to output a third power that is greater than the second power and less than one of the first power. FIG. 12 is a schematic diagram of a dynamic random access memory (DRAM) 40 including an allocation element 44 according to some embodiments of the present disclosure. Referring to FIG. 12, the DRAM 40 is similar to the DRAM 20 shown in FIG. 5 except that the DRAM 40 includes a distribution element 44 and a control element 42 including a table 420. As mentioned before, the table 420 is used to record the received addresses. In addition, table 420 reflects the number of sub-arrays operated in each bank. For example, referring to FIG. 7, a table 420 associated with the embodiment of FIG. 7 is shown in Table 1 below.
<TABLE border = "1" borderColor = "# 000000" width = "85%"> <TBODY> <tr> <td> </ td> <td> Number of sub-arrays operated on </ td> </ tr > <tr> <td> Memory 160 </ td> <td> 2 </ td> </ tr> <tr> <td> Memory 170 </ td> <td> 1 </ td> </ tr > </ TBODY> </ TABLE> Table 1 Based on the table 420, the distribution element 44 is used to distribute the resulting amount of power to the memory 160 and the memory 170. In more detail, referring to FIG. 2, the number of sub-arrays operated in the memory bank 160 is greater than the number in the memory bank 170. Accordingly, the distribution element 44 distributes more power to the first memory bank 160 than the second memory bank 170. All in all, according to such a distribution method, the distribution element 44 distributes the resulting amount of electric energy to the memory bank. The amount of power allocated to the memory bank is positively related to the number of sub-arrays being operated. FIG. 13 is a flowchart of a method 50 of operating a DRAM according to some embodiments of the disclosure. Referring to FIG. 13, the method 50 is similar to the method 10 illustrated with reference to FIG. 10, except that the method 50 includes operations 52, 54, and 56. In operation 52, a plurality of addresses are received. Each address indicates which subarray of which bank is operated. In operation 54, based on the address, information is obtained, which information is about the number of sub-arrays being operated on. In operation 56, the resulting amount of electrical energy is allocated to the memory bank according to an allocation method that includes that the amount of electrical energy allocated to the memory bank is positively related to the number of sub-arrays being operated. In the present disclosure, the control element 22 is configured to obtain information about the number of sub-arrays being operated, and based on the information, decide how much power to output. In this way, the electrical energy output by the power source 24 is adjustable and can therefore be managed. As a result, the DRAM 20 can provide a power management function, and the use of electrical energy is relatively efficient. Especially when the number of the operated sub-arrays is relatively low, the power source 24 can output a relatively low power. The use of electrical energy is relatively efficient. In contrast, in the comparative DRAM 10, the enabling element 12 cannot obtain information about the number of sub-arrays being operated. Furthermore, the enabling element 12 cannot determine how much electrical energy to output based on the information. Therefore, the electric energy output by all of the first charge pump 140, the second charge pump 142, and the third charge pump 144 is not adjustable and therefore cannot be managed. As a result, the DRAM 10 cannot provide a power management function, and the use of power is relatively inefficient. Especially in the case where one or more of the first array 160, the second array 162, the third array 170, and the fourth array 172 are not operated, the power source 14 still outputs the same output voltage as all the first arrays. 160, the second array 162, the third array 170, and the fourth array 172 operate with the same power. That is, the power source 14 outputs more power than the memory 16 requires. The use of electrical energy is relatively inefficient. An embodiment of the present disclosure provides a DRAM. The DRAM includes a plurality of memory banks, a power source, and a control element. The banks each include a plurality of sub-arrays. The control element is configured to obtain a message. The information is about the number of sub-arrays that were operated in the sub-arrays. The control element generates a decision based on the resource, the decision is how much electric energy is output, and the power source outputs a result amount of electric energy based on the decision of the control element. Another embodiment of the present disclosure provides a power management method of a dynamic random access memory. The power management method includes providing a plurality of memory banks, each of which includes a plurality of sub-arrays; obtaining an information about the number of sub-arrays operated in the sub-arrays; and generating a A decision, wherein the decision is how much power is output; and based on the decision, a result amount of power is output. Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the scope of the patent application. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced with other processes or combinations thereof. Moreover, the scope of the present application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods and steps described in the description. Those skilled in the art can understand from the disclosure of this disclosure that according to this disclosure, they can use existing, or future developmental processes, machinery, manufacturing, materials that have the same functions or achieve substantially the same results as the corresponding embodiments described herein. Composition, means, method, or step. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included in the scope of the patent application of this application.