TWI633660B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor element and a manufacturing method thereof. The semiconductor device includes a substrate, a gate dielectric layer, a gate, a drain, and a source. The substrate has a V-shaped groove. The gate dielectric layer is on a substrate. The gate dielectric layer has a first thickness on a sidewall of the trench and a second thickness on a substrate outside the trench. The first thickness is greater than the second thickness. The gate is located on the gate dielectric layer. The drain and source are located in substrates on opposite sides of the gate, respectively.

Description

Semiconductor element and manufacturing method thereof

The present invention relates to a semiconductor element, and more particularly to a transistor.

The high-voltage element includes a lateral diffuse metal-oxide-semiconductor (LDMOS) transistor. In particular, the manufacturing process of LDMOS transistors can be integrated with the manufacturing process of complementary metal-oxide-semiconductor (CMOS) transistors so that control elements, logic elements, and switching elements can be manufactured on a single chip.

In the LDMOS transistor, a field oxide layer is provided on the substrate between the gate and the drain to increase the distance the carriers move. In this way, the breakdown voltage of the LDMOS can be increased. However, this approach will increase the area occupied by LDMOS, that is, reduce the accumulation of LDMOS.

The invention provides a semiconductor device having a V-shaped groove in a substrate.

The invention provides a method for manufacturing a semiconductor device, which can form gate dielectric layers having different thicknesses by a simple process.

The semiconductor device of the present invention includes a substrate, a gate dielectric layer, a gate, a drain, and a source. The substrate has a V-shaped groove. The gate dielectric layer is on a substrate. The gate dielectric layer has a first thickness on a sidewall of the trench and a second thickness on a substrate outside the trench. The first thickness is greater than the second thickness. The gate is located on the gate dielectric layer. The drain and source are located in substrates on opposite sides of the gate, respectively.

In an embodiment of the present invention, a ratio of the first thickness to the second thickness may be in a range of 1.01 to 2.5.

In one embodiment of the present invention, the material of the substrate may be a silicon substrate. The surface of the substrate in the trench may belong to the {111} plane family, and the surface of the substrate outside the trench may belong to the {100} plane family. The extending direction of the groove may belong to the <110> direction family.

In an embodiment of the invention, the trench is relatively adjacent to the drain and relatively far from the source.

In an embodiment of the invention, the substrate may have a plurality of grooves. Adjacent trenches are separated from each other.

The method for manufacturing a semiconductor element of the present invention includes the following steps. A trench is formed in the substrate. The trench has a V-shaped cross section. A gate dielectric layer is formed on the substrate. The gate dielectric layer has a first thickness on a sidewall of the trench, and the gate dielectric layer has a second thickness on a substrate outside the trench, where the first thickness is greater than the second thickness. A gate is formed on the gate dielectric layer. A drain and a source are formed in substrates on opposite sides of the gate.

In one embodiment of the present invention, the material of the substrate may be a silicon substrate. The surface of the substrate can belong to the {100} plane family. The method of forming the trench may include the following steps. A patterned mask layer is formed on the substrate. The patterned mask layer has an opening, and the extending direction of the opening belongs to the <110> direction family of the base. The substrate exposed by the opening is removed by a wet etching method to form a trench.

In an embodiment of the present invention, the method of wet etching may include a method of wet etching having anisotropy.

In one embodiment of the present invention, the method for forming the gate dielectric layer may include a thermal oxidation method, a nitriding process, or a combination thereof.

In an embodiment of the present invention, the step of forming a trench may include forming a plurality of trenches on a surface of the substrate. Adjacent trenches are separated from each other.

Based on the above, the gate dielectric layers of the semiconductor elements of the present invention have different thicknesses. In particular, the thickness of the gate dielectric layer on the sidewall of the trench of the substrate is greater than its thickness on the substrate outside the trench, and the trench has a V-shaped cross-section. In this way, the larger thickness portion of the gate dielectric layer can make the semiconductor device have a higher breakdown voltage of the gate dielectric layer. A trench with a V-shaped profile can disperse the current distribution at the drain to avoid hot carrier effects. In addition, the smaller thickness of the gate dielectric layer allows the semiconductor element to maintain a lower initial voltage. In addition, by providing a trench in the substrate below the gate, the path length of the carrier moving between the drain and source can be increased while maintaining the distance between the gate and the drain. Therefore, the voltage that the semiconductor element can withstand can be increased and the degree of accumulation of the semiconductor element can be maintained.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

1A to 1E are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention. The method of manufacturing the semiconductor element 10 of this embodiment includes the following steps.

Referring to FIG. 1A, a deep well region 102, a first well region 104, and a second well region 106 are selectively formed in the substrate 100. The substrate 100 is, for example, a silicon substrate or a silicon on insulator (SOI) substrate. In this embodiment, the surface of the substrate 100 may belong to the {100} plane family. The substrate 100 and the first well region 104 may be doped to have a first conductivity type, and the deep well region 102 and the second well region 106 may be doped to have a second conductivity type. In some embodiments, the first conductivity type is a P-type and the second conductivity type is an N-type. In other embodiments, the first conductivity type may be an N type, and the second conductivity type may be a P type at this time. The N-type dopant may include phosphorus or arsenic or antimony, and the P-type dopant may include boron or indium. The first well region 104 and the second well region 106 are located separately from each other in the deep well region 102. In addition, the depth of the first well region 104 may be greater than the depth of the second well region 106.

Next, an isolation structure 108 surrounding the deep well region 102 is selectively formed. Viewed in cross-section, the isolation structure 108 spans a portion of the base 100, a portion of the deep well region 102, and a portion of the first well region 104 on the first side S1 of the deep well region 102. In addition, the isolation structure 108 spans a portion of the base 100, a portion of the deep well region 102, and a portion of the second well region 106 on the second side S2 of the deep well region 102. The first side S1 and the second side S2 of the deep well region 102 are opposed to each other. The isolation structure 108 may be a shallow trench isolation (STI) structure, a field oxide structure, or a local oxidation of silicon (LOCOS) structure.

Subsequently, referring to FIG. 1B, a patterned mask layer 110 is formed on the substrate 100. The patterned mask layer 110 has an opening P. The opening P exposes a portion of the deep well region 102 and a portion of the second well region 106. In other words, one side of the opening P is located on the deep well region 102 between the first well region 104 and the second well region 106, and the other side of the opening P is located on the second well region 106. In this embodiment, the surface of the substrate 100 belongs to the {100} plane family. In addition, from the above view, the extending direction of the opening P belongs to the <110> direction family.

Next, a trench 112 is formed in the substrate 100. The trench 112 has a V-shaped cross section. In particular, the method of forming the trench 112 may include removing the deep well region 102 and the second well region 106 exposed by the opening P using the patterned mask layer 110 as a mask. In some embodiments, the method of removing the deep well region 102 and the second well region 106 exposed by the opening P includes wet etching. The etchant for wet etching includes an etchant having anisotropic etching characteristics, such as tetramethylammonium hydroxide (TMAH), Ethylene Diamine Pyrochatechol (EDP), or mixture. In this embodiment, the substrate 100 is a silicon substrate, and the surface of the substrate 100 belongs to the {100} plane family. The etching rate of the {111} plane family of silicon is much lower than that of other plane families. Therefore, when the substrate 100 is wet-etched, a plurality of crystal planes belonging to the {111} plane family can be used as the termination surface of the wet-etching. In particular, the extension directions of the multiple crystal planes belonging to the {111} plane family are staggered with each other, so that the trench 112 is formed to have a V-shaped cross section. In this way, the surface of the substrate outside the trench 112 may belong to the {100} plane family, and the surface of the substrate 100 in the trench 112 may belong to the {111} plane family. The extending direction of the sidewall of the trench 112 has an included angle θ with the surface of the substrate outside the trench 112. The included angle θ may be an included angle between the {111} plane family and the {100} plane family, for example, 54.7 °. However, the included angle θ may change slightly as the process parameters change. In some embodiments, the included angle θ may be in a range of 50 ° to 60 °. As such, the ratio of the width W to the depth D of the trench 112 may be in the range of 1.16 to 1.68.

Referring to FIG. 1C, the patterned mask layer 110 can be removed. Subsequently, a gate dielectric layer 114 is formed on the substrate 100. The method for forming the gate dielectric layer 114 includes a thermal oxidation method, a nitriding process, or a combination thereof. The material of the gate dielectric layer 114 includes silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material (for example, a dielectric constant greater than 4), or a combination thereof. The formed gate dielectric layer 114 has a first thickness T1 on the sidewall of the trench 112 and a second thickness T2 on the substrate 110 outside the trench 112. The rate of growing a dielectric layer on a crystal plane belonging to the {111} plane family of silicon is higher than the rate of growing a dielectric layer on a crystal plane belonging to the {100} plane family of silicon. Therefore, in this embodiment, the first thickness T1 of the gate dielectric layer 114 on the sidewall of the trench 112 is greater than the second thickness T2 of the gate dielectric layer 114 on the substrate 100 outside the trench 112. In some embodiments, the ratio of the first thickness T1 to the second thickness T2 is in a range of 1.01 to 2.5. However, those with ordinary knowledge in the art can adjust the above-mentioned ratio range by controlling the process parameters, and the invention is not limited thereto. In addition, the bottom of the gate dielectric layer 114 in the trench 112 may be pointed or slightly curved.

Referring to FIG. 1D, a gate material layer is formed on the gate dielectric layer 114. Subsequently, the gate material layer is patterned to form the gate 116. The gate electrode 116 is formed to cover a portion of the first well region 104, a portion of the second well region 106, and a deep well region 102 between the first well region 104 and the second well region 106. In some embodiments, a side of the gate electrode 116 on the second well region 106 may contact a side of the trench 112 on the second well region 106. In other words, the side of the gate electrode 116 on the second well region 106 may be aligned with the side of the trench 112 on the second well region 106. In other embodiments, the side of the gate electrode 116 on the second well region 106 may not directly contact the side of the trench 112 on the second well region 106. In other words, the side of the gate electrode 116 on the second well region 106 may not be aligned with the side of the trench 112 on the second well region 106. The material of the gate 116 may include polycrystalline silicon, a metal, a metal alloy, or a metal compound. After the gate electrode 116 is formed, the gate dielectric layer 114 exposed by the gate electrode 116 can be removed as a mask to form the gate dielectric layer 114 a.

Referring to FIG. 1E, a drain electrode 118 is formed in the substrate 100 on one side of the gate electrode 116, and a source electrode 120 is formed in the substrate 100 on the other side of the gate electrode opposite to the drain electrode 118. In addition, a doped region 122 may be formed in the substrate 100 between the source electrode 120 and the isolation structure 108. The drain 118 and the source 120 may have a second conductivity type, and the doped region 122 may have a first conductivity type. In particular, the drain 118 may be located in the second well region 106. The source electrode 120 and the doped region 122 may be located in the first well region 104 and connected to each other. In some embodiments, the trench 112 is relatively adjacent to the drain 118 and relatively far from the source 120. In other words, the distance D1 between the bottom of the trench 112 and the drain 118 is smaller than the distance D2 between the bottom of the trench 112 and the source 120.

So far, the manufacturing of the semiconductor element 10 of this embodiment has been completed. The semiconductor element 10 may be a LDMOS transistor. After the semiconductor element 10 is turned on, a channel can be formed in the first well region 104 covered by the gate electrode 116. By applying a bias voltage between the drain electrode 118 and the source electrode 120, carriers can flow from the source electrode 120 to the drain electrode 118 through the channel, the deep well region 102, and the second well region 106, or the carriers can be self-drained. 118 flows to the source electrode 120 through the second well region 106, the deep well region 102, and the channel.

Based on the above, the first thickness T1 of the gate dielectric layer 114a on the sidewall of the trench 112 is greater than the second thickness T2 of the gate dielectric layer 114a on the substrate 100 outside the trench 112. In this way, the portion of the gate dielectric layer 114a having a larger thickness can make the semiconductor element 10 have a higher gate dielectric breakdown voltage. The trench 112 having a V-shaped cross section can disperse the current distribution at the drain 118 to avoid hot carrier effects. In addition, the portion of the gate dielectric layer 114a having a smaller thickness enables the semiconductor element 10 to maintain a lower initial voltage. In addition, by providing the trench 112 in the substrate 100 below the gate 116, it is possible to increase the carrier between the drain 118 and the source 120 while maintaining the distance between the gate 116 and the drain 118. The length of the path between moves. Therefore, the semiconductor element 10 can be subjected to a higher voltage and the degree of accumulation of the semiconductor element 10 can be maintained.

In some embodiments, the surface of the substrate 100 outside the trench 112 and the surface of the substrate 100 in the trench belong to different plane families. Dielectric layers are formed at different rates on different plane families of the same material. Therefore, the gate dielectric layer 114 having different thicknesses can be formed on the substrate 100 in a single step. In this way, the manufacturing method of the semiconductor element 10 can be simplified.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. The semiconductor element 20 and its manufacturing method of this embodiment are similar to the semiconductor element 10 and its manufacturing method shown in FIG. 1E. Only the differences will be described below, and the same or similar points will not be described again. In addition, in the following description, the same component symbols as those in FIG. 1E represent the same or similar components.

Referring to FIG. 2, the substrate 100 has a plurality of trenches 112. In some embodiments, the plurality of trenches 112 may include trenches 112a and 112b. Adjacent trenches 112a and 112b may be separated from each other. In some embodiments, the leftmost one of the trenches 112 of FIG. 2 is relatively adjacent to the drain 118 and relatively far from the source 120. In other words, the distance D3 between the bottom of the trench 112a and the drain 118 is smaller than the distance D4 between the bottom of the trench 112a and the source 120. In other embodiments, especially when the number of the trenches 112 is greater or the width and depth of the trenches 112 are larger, the leftmost one of the trenches 112 may be relatively far from the drain 118, and Relatively close to the source electrode 120. In other words, the distance between the bottom of the leftmost trench and the drain 118 may be greater than the distance between the bottom of the leftmost trench and the source 120. Further, at least one of the plurality of trenches 112 may be partially located in the second well region 106. For example, a portion of the trench 112 b near the drain 118 may be located in the second well region 106. By providing a plurality of trenches 112, the path length of the carrier moving between the drain 118 and the source 120 can be further increased. Therefore, it is possible to further increase the withstand voltage of the semiconductor element 20 while maintaining the degree of accumulation of the semiconductor element 20.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10, 20‧‧‧ semiconductor components

100‧‧‧ substrate

102‧‧‧Shenjing District

104‧‧‧The first well area

106‧‧‧Second Well District

108‧‧‧Isolation structure

110‧‧‧ patterned cover layer

112, 112a, 112b ‧‧‧ Trench

114, 114a‧‧‧ Gate dielectric layer

116‧‧‧Gate

118‧‧‧ Drain

120‧‧‧Source

122‧‧‧ doped region

D‧‧‧ Depth

D1, D2, D3, D4‧‧‧ pitch

P‧‧‧ opening

S1‧‧‧First side

S2‧‧‧Second side

T1‧‧‧first thickness

T2‧‧‧Second thickness

W‧‧‧Width

θ‧‧‧ angle

1A to 1E are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

Claims (7)

A semiconductor device includes a substrate having a V-shaped groove, wherein the substrate is a silicon substrate, a surface of the substrate in the groove belongs to a {111} plane family, and the substrate is located in a The surface outside the trench belongs to the {100} plane family, and the extending direction of the trench belongs to the <110> direction family; a gate dielectric layer is located on the substrate, wherein the gate dielectric layer is in the trench The side wall of the trench has a first thickness and a second thickness on the substrate outside the trench, the first thickness is greater than the second thickness; a gate electrode is located on the gate dielectric layer; And a source and a drain are respectively located in the substrate on opposite sides of the gate, wherein the trench is relatively adjacent to the drain and relatively far from the source. The semiconductor element according to item 1 of the scope of patent application, wherein a ratio of the first thickness to the second thickness is in a range of 1.01 to 2.5. The semiconductor device according to claim 1, wherein the substrate has a plurality of the trenches, and adjacent trenches are separated from each other. A method for manufacturing a semiconductor device includes forming a V-shaped groove in a substrate, wherein the substrate is a silicon substrate, and a surface of the substrate belongs to a {100} plane family. A method of forming the groove includes: Forming a patterned masking layer on the substrate, wherein the patterned masking layer has an opening, and the extending direction of the opening belongs to the <110> direction family; and removing the exposed by the opening by a wet etching method The substrate is formed to form the trench; a gate dielectric layer is formed on the substrate, wherein the gate dielectric layer has a first thickness on a sidewall of the trench, and the gate dielectric A layer having a second thickness on the substrate outside the trench, the first thickness being greater than the second thickness; forming a gate electrode on the gate dielectric layer; and two opposite sides of the gate electrode A drain and a source are formed in the substrate on the side, wherein the trench is relatively adjacent to the drain and relatively far from the source. The method for manufacturing a semiconductor device according to item 4 of the scope of patent application, wherein the method of wet etching includes a method of wet etching having anisotropy. The method for manufacturing a semiconductor device according to item 4 of the scope of patent application, wherein the method for forming the gate dielectric layer includes a thermal oxidation method, a nitriding process, or a combination thereof. The method for manufacturing a semiconductor element according to item 4 of the scope of patent application, wherein the step of forming the trench includes forming a plurality of the trenches on a surface of the substrate, and adjacent trenches are separated from each other.