TWI633627B - Process for copper metallization and process for forming a cobalt or a nickel silicide - Google Patents

Abstract

The subject matter of the present invention is a method for metallizing by copper, which uses a specific silicide to improve the adhesion of a copper deposit on a semiconductor substrate. In microelectronic applications, this method presents the advantages that can be used to fabricate three-dimensional integrated circuits by "post-piercing" technology. This is because this technology is temperature limited. In photovoltaic applications, the method of the invention makes it possible to produce silicide / nickel stacks in one step with a lower thermal budget. The method of the present invention includes a step including applying a rapid thermal treatment to a nickel-covered substrate to form an intervening layer between the nickel layer and the silicon layer, which constitutes an adhesion promoter between the substrate and the copper, and which includes SiM ₂ Stoichiometric silicide, M represents nickel, the silicide is formed by diffusing a part of the nickel into the silicon in order to leave a residual nickel layer on the surface, and the heat treatment is performed at a temperature below 350 ° C and Duration of less than 30 minutes.

Description

Method for copper metallization and method for forming cobalt or nickel silicide

Metal silicides have been used for a long time to manufacture integrated circuits to reduce the contact resistance between transistors and first metal interconnect layers, which are generally made of tungsten. The interconnects located only in the final layer of the integrated circuit are made of copper.

One nickel silicide (SiNi) has replaced cobalt disilicon (Si ₂ Co), and the resistance of cobalt disilicide has become too high to connect a transistor with a gate with a smaller size (65nm node).

The silicide SiNi is generally formed in two steps: depositing a nickel and platinum alloy, a first heat treatment to form SiNi ₂ and a second heat treatment to convert SiNi ₂ to SiNi.

For example, in patent US 6 406 743, nickel silicide SiNi is used as a conductor material in VLSI semiconductor devices. This document provides a method for producing nickel silicide by depositing nickel on silicon followed by heat treatment. This method involves activating a polycrystalline silicon surface at ambient temperature for about ten seconds by using a palladium chloride salt in a dissolved state in hydrofluoric acid and acetic acid. After this activation step, a nickel layer with a thickness of 180-220 nm is deposited via an electrodeless route, such as a solution using nickel sulfate and dimethylamine borane in the presence of a nickel complexing agent such as lactic acid and citric acid. Nickel silicide is formed by bringing the nickel to a high temperature (650 ° C) to allow nickel to migrate into the silicon. The non-migrating nickel is then removed by a chemical etching solution before being covered with tungsten.

Document US 6 566 254 describes a method for manufacturing MOS transistors using a mixture of CoSi and CoSi ₂ which is formed in situ by two steps of heat treatment: the first treatment is performed between 450 ° C and 550 ° C, and then the second The treatment is between 700 ° C and 800 ° C.

In most previous methods of manufacturing semiconductor or photovoltaic cells, stacks of silicon, silicide, and nickel must necessarily be manufactured in several steps: nickel is deposited on silicon, heat-treated to produce nickel silicide, and removed without migration to silicon Of the nickel remaining on the silicide surface, the surface of the silicide is cleaned and a new nickel layer is subsequently deposited. This is because, in the current method, the interface obtained from the result of the heat treatment step between the formed silicide and the non-migrated residual nickel has extremely poor quality that causes ordinary adhesion. So the only way to get good adhesion is to remove the residual nickel in order to redeposit a fresh layer of nickel attached to the silicide.

FIG. 1 shows an ion polishing of a sample profile obtained according to steps a) to e) of Example 1 in a case where the metal is nickel, the thermal annealing temperature is equal to 250 ° C., and the silicide is nickel silicide (SiNi2).

FIG. 2 is an SEM photograph of an ion polishing sample overview obtained according to steps a) to e) of Example 2 when the metal is cobalt, the thermal annealing temperature is 300 ° C., and the silicide is cobalt silicide (SiCo2).

The present invention relates generally to the manufacture of semiconductor electronic devices and more specifically to the generation of copper wires and silicon vias in silicon substrates or silicon dioxide substrates, for connecting components of integrated circuits or for conducting electricity in photovoltaic cells. .

The metallization method of the present invention consists in covering a silicon dioxide substrate or covering it with a silicon dioxide layer. Copper is formed in a silicon substrate in a pre-hollowed structure. The copper metallization step is preceded by another metallization step, which consists in forming a metal or metal alloy, the function of which is to form a barrier for diffusion of copper atoms during the operation of the device. This intermediate metal layer must meet three criteria: it exhibits sufficient conductivity when copper is to be deposited by electrolytic methods, on the one hand, it has a uniform thickness, and on the other hand it guarantees good adhesion to silicon dioxide.

In complex shapes that define non-planar topography, such as through-silicon vias and trenches, attempts are being made to increase the adhesion between silicon dioxide, which acts as an electrical insulator, and copper. In addition, the metallization method must result in a metal layer having a very uniform thickness (refer to high consistency). As the aspect ratio of the structure becomes higher and higher, these two requirements become more difficult to achieve.

Therefore, the inventors have attempted to solve this problem and they have found that silicon dinickel SiNi ₂ and silicon dicobalt SiCo ₂ are excellent adhesion promoters between silicon dioxide and copper and between silicon and copper. They have also proven that this is not the case with a nickel silicide.

Surprisingly, the inventors have discovered a novel method in this application to guarantee and even improve the adhesion of copper to silicon dioxide substrates by inserting specific materials that have never been used before.

The inventors have also discovered a method of making a stack of silicon, silicide, and nickel in a reduced number of steps that does not require depositing a fresh layer of nickel after the nickel silicide is formed.

Recently, a nickel silicide has been introduced into the manufacture of photovoltaic cells. This is because when silver is replaced with copper, an attempt is made to create an electrical contact with extremely high conductivity. In these devices, such as in transistors, nickel silicide is used to make contacts due to its good electrical conductivity. Nickel silicide is preferred over dinickel silicide because it exhibits greater electrical conductivity.

After nickel is deposited on silicon by non-electrolytic method, a nickel silicide interface is formed between nickel and silicon by high temperature heat treatment. During this heat treatment (at a temperature of approximately 400 ° C. to 750 ° C.), nickel migrates into the silicon substrate to form nickel silicide SiNi, where the stoichiometric ratio is 1: 1. Subsequently stripped Residual nickel not converted to nickel silicide. Fresh deposition of nickel on silicide is sometimes performed and serves as a substrate for copper deposition.

However, this method presents several disadvantages: it requires a high thermal budget and requires two steps in order to produce a nickel silicide / nickel stack with good adhesion.

In fact, contrary to following the methods so far, the inventors have found that the lower conductivity of dinickel silicide is greatly compensated by the conductivity of copper in the subject application of the invention, and it is possible to make nickel / nickel silicide in a single step Stacked, all this finding lowers the heat treatment temperature and at the same time stays within a time period compatible with industrial processes.

This is because multiple inventors have found a method for producing a nickel / silicide stack in a reduced number of steps, which required multiple steps in the prior art. This is because by using metal particles to activate the surface of silicon, it is possible to cause nickel to migrate uniformly and extremely quickly at low temperatures. As a result, heat treatment can be interrupted before all nickel is converted to nickel silicide, while a nickel layer with good quality is obtained And stacks with good adhesion.

The present invention is particularly advantageous for methods of manufacturing three-dimensional integrated circuit structures that cannot be exposed to temperatures greater than 350 ° C and even greater than 300 ° C, which would have the risk of weakening the interface between different layers assembled by bonding. In fact, due to this limitation in temperature, it has hitherto not been possible to produce a copper deposit with good adhesion, especially when silicon vias are manufactured according to a post-via method.

Description of the invention

Therefore, the first object of the present invention is a method for forming a silicide on a substrate. The method includes a step of providing a substrate covered by a silicon layer having an exposed silicon surface, and the following steps: i- on the exposed silicon surface Gold particles or palladium particles are formed on the surface to obtain an activated silicon surface, and ii- a metal or metal alloy in the form of a layer is formed on the surface of the activated silicon, the metal is selected from the group consisting of nickel and cobalt and the metal alloy is selected from the group consisting of nickel A group consisting of an alloy and a cobalt alloy, and obtaining a stacked assembly, iii- applying a rapid heat treatment to the stacked assembly obtained in step ii) between a) a metal layer or a metal alloy layer and b) a silicon layer An insertion layer is formed, which is in contact with the silicon layer and mainly contains SiM ₂ silicide, M represents nickel or cobalt, and the SiM ₂ silicide is formed by diffusing a metal or a metal alloy into the silicon layer so as to have an exposed surface. The remaining portion of the metal layer or the remaining metal alloy layer is in contact with the silicon layer, and the rapid heat treatment is performed at a rapid heat treatment temperature of less than or equal to 350 ° C.

According to this method, the inserted SiM ₂ silicide layer constitutes a copper-assisting adhesive and is advantageously in contact with the surface of the activated silicon.

For example, the method of the present invention includes forming a silicide SiNi ₂ material layer or a silicide SiCo ₂ material layer in contact with the surface of the activated silicon. In fact, the conditions above, such as the formation of an activated silicon surface and the application of a rapid heating temperature lower than expected, advantageously allow the formation of SiM ₂ silicide in direct contact with the silicon material. This is not the case with prior art methods of forming silicide.

Known methods for forming silicide between a silicon substrate and a nickel or cobalt layer use similar heating temperatures, but do not form a large amount of SiM ₂ silicide. In more detail, these prior art methods instead cause a large amount of SiM silicide to be formed between the silicon substrate and the metal M. In practice SiM ₂ silicide can be formed between the SiM silicon layer and the metal layer in one part of these methods. However, SiM ₂ silicides are formed at extremely low levels and never contact the silicon layer.

According to the method of the present invention, a small amount and preferably no SiM silicide is formed at the interface between the silicon layer and the metal M layer. Without being bound by any theory, the activation of gold or palladium on the surface of Xianxin silicon makes it easier for the metal to diffuse into the silicon and completely form a SiM ₂ silicide.

The present invention relates to improving the low adhesion of SiM silicide to silicon. Contact with silicon substrate SiM formation is undesirable.

According to the method of the present invention, when measuring the two adhesion values according to the same method and under the same conditions, the heat treatment step makes it possible to obtain a first adhesion between the substrate and the copper that is greater than or equal to the second adhesion value. The values are obtained under the same conditions, but in the case of nickel at a heat treatment temperature of 350 ° C or higher and in the case of cobalt at a heat treatment temperature of 400 ° C or higher. get on. Methods for measuring adhesion are known to those skilled in the art.

In a specific embodiment, the thickness of the metal layer or metal alloy deposited in step ii) is between 10 nm and 150 nm.

Subsequently, during step iii), the metal migrates into the silicon under heating. The heat treatment is interrupted before all amounts of metal deposits have migrated into the silicon and before all metals are converted to SiM ₂ stoichiometric silicides, where M represents nickel or cobalt. Therefore, the temperature, duration or both temperature and duration applied during the heat treatment is selected so that the thickness of the residual metal layer is preferably in the range of 5 nm to 100 nm, and / or the inter-silicide layer formed under the effect of heating ( A silicide containing a stoichiometric amount of SiM ₂ (M represents nickel or cobalt) has a thickness in a range of 10 nm to 200 nm, for example, 10 nm to 50 nm.

For example, the thickness of the residual metal layer is preferably between two values selected from the group consisting of: 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, and 100nm, and The thickness of the silicide intercalated silicide layer of SiM ₂ is between two values selected from the group consisting of: 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 100nm, 120nm, 140nm, 160nm, 180nm and 200nm.

Depending on the nature of the metal, depending on whether it is composed of nickel, nickel alloy, cobalt or cobalt alloy, the temperature will be adjusted to form a silicide of SiM ₂ stoichiometry in an amount sufficient to ensure the promotion of adhesion between silicon and copper, M represents nickel or cobalt.

In the context of the present invention, a SiM ₂ stoichiometry silicide is used as an adhesion promoter between silicon and copper, and makes it especially possible to obtain a silicide that is better than using another silicide (such as one of the SiM stoichiometry) The adhesion is much greater than the level of adhesion. The inventors have given evidence for the fact that the replacement of the inserted SiM ₂ layer with the inserted SiM layer in the same structure has reduced the adhesion force from 16/16 to 0/16 according to the standard ASTM 3359.

The temperature and / or duration of the heat treatment at step iii) can be selected so that the copper-to-substrate adhesion is between 5/16 and 16/16, preferably between 10/16 and 16, as measured by standard ASTM 3359. Between 16/16, more preferably between 12/16 and 16/16, and preferably equal to 16/16.

In a specific embodiment, the metal alloy is a nickel alloy having an element selected from the group consisting of boron, tungsten, and phosphorus. The metal may be a cobalt alloy having an element selected from the group consisting of boron, tungsten, and phosphorus. In these metal alloys, the element may mean that the metal alloy is between 0.1% and 10% by weight.

For example, the metal is a cobalt alloy with boron (for example, about 5 atomic% of boron), the heat treatment temperature is between 250 ° C and 350 ° C, preferably equal to 300 ° C, and the duration of the treatment is less than 30 minutes, for example About 10 minutes.

In another example, the metal is a nickel alloy containing boron (for example, about 6 wt% or 35 atomic% boron), the heat treatment temperature is between 200 ° C and 300 ° C, preferably equal to 250 ° C, and the duration of the treatment Less than 30 minutes, such as about 10 minutes.

The atmosphere in which the substrate is immersed is preferably a reducing atmosphere (such as a N ₂ + H ₂ (4% H ₂ ) mixture) under standard pressure conditions.

The silicon may be doped or undoped and selected from polycrystalline silicon, amorphous silicon, and crystalline silicon. In a specific example, the metal is deposited on polycrystalline silicon.

Step i)

Activation of the surface of the silicon layer by metal particles of gold (Au (0)) or palladium (Pd (0)) can be performed in several ways.

One of these methods is to contact the surface of the silicon layer with an aqueous solution containing metal ions and fluoride ions of gold or palladium.

In this patent application, the expressions "within ..." and "contains ... to" refer to ranges that include limit values. Represents the bounds of a range of values excluding between "and ...".

The aqueous solution preferably contains fluoride ions from 0.6M to 3.0M, more preferably 1.0M to 2.0M, and more preferably 1.4M to 1.6M.

Fluoride can be provided by hydrofluoric acid (HF), NH ₄ F, or a mixture of NH ₄ F / HF.

The aqueous solution preferably contains hydrofluoric acid (HF) from 0.6M to 3.0M, preferably from 1.0M to 2.0M and more preferably from 1.4M to 1.6M.

The aqueous solution preferably contains metal ions of 0.1 mM to 10 mM, preferably 0.1 mM to 5.0 mM and more preferably 0.5 mM to 1.0 mM. The metal ion concentration is, for example, between 0.65 mM and 0.75 mM.

The gold ion may be provided by a gold salt selected from a gold (I) salt and a gold (III) salt, such as gold (I) chloride, gold (III) chloride, or gold (III) bromide.

For example, select chloroauric acid (HAuCl ₄ ). The solution may contain a complexing agent for gold ions, such as an aromatic amine, such as bipyridine, terpyridine or phenanthroline.

The palladium ion may be provided in the form of a palladium salt or in the form of a palladium complex, such as diammonium (II) tetrachloropalladate.

The aqueous solution preferably contains 0.1 mM to 10 mM metal ions, preferably 0.1 mM to 5.0 mM And more preferably 0.5 mM to 1.0 mM metal ions. The metal ion concentration is, for example, between 0.65 mM and 0.75 mM.

According to a preferred embodiment, the aqueous solution contains: -0.1 mM to 10 mM, preferably 0.5 mM to 1.0 mM metal ions, and -0.6M to 3.0M, preferably 1.0 M to 2.0M fluoride ions.

The aqueous solution may contain organic or inorganic acid compounds, whether strong or weak, in order to change the erosion rate on the silicon, especially to increase or decrease the erosion rate. In one embodiment, the aqueous solution is free of CH ₃ COOH acetate.

The solution may additionally contain a surfactant. The surfactant may be selected from compounds containing at least one anionic or non-ionic polar group and an alkyl chain containing at least 10 carbon atoms (eg, 10 to 16 carbon atoms, preferably 10 to 14 carbon atoms). The alkyl chain is preferably a straight chain. It advantageously contains 12 carbon atoms (also known as dodecyl).

This specific surfactant makes it possible to stabilize the metal particles formed after the redox reaction with silicon. It also makes it possible to increase the number of metal particles and further disperse the metal particles on the surface of silicon. By adding this surfactant to the activation bath, the size of the metal particles can be reduced while increasing their density.

This distribution of metal particles makes it possible to deposit a nickel layer and then a nickel silicide layer, which are extremely thin and simultaneously continuous. The prior art method was not possible because it had to deposit a thicker nickel layer in order to guarantee the entire surface of silicon On the uniform deposition. The thickness of the nickel layer can be advantageously below 150 nm.

Anionic surfactants having a molecular weight between 100 g / mol and 1500 g / mol are preferred.

The polar group may be a nonionic group, preferably a polyoxyalkylene glycol group, such as a polyoxyethylene glycol group or a polyoxypropylene glycol group. In this embodiment, the surfactant may be selected from polyoxyalkylene glycol alkane The ether is preferably a polyoxyalkylene glycol alkyl ether comprising an alkyl chain having 10 to 16 carbon atoms, such as, for example, a polyoxyethylene glycol dodecyl ether.

Polar group may be anionic groups, such as sulfonate (-SO ₃ ^-), sulfate (-OSO ₃ ^-) or carboxylate (-COO ^-). Sulfate is preferred in the context of the present invention. Preferably surfactants of formula ₃ R-OSO ^- the alkyl sulfate, wherein R is from 10 to 14 carbon atoms, preferably 12 carbon atoms of straight-chain alkyl. The surfactant may be, for example, sodium lauryl sulfate.

The surfactant preferably represents 0.1 to 5% by weight of the solution, such as 2.5 to 3.5% by weight.

According to a preferred embodiment, the aqueous solution contains 0.5 mM to 1 mM chloroauric acid (HAuCl ₄ ), 1.0 M to 2.0 M hydrofluoric acid (HF), and optionally 2.5 to 3.5% by weight based on the weight of the composition Of sodium lauryl sulfate.

Preferably, the step of activating the silicon substrate by depositing metal particles on the surface of the silicon substrate is at a temperature between 15 ° C and 30 ° C, and more preferably at a temperature between 20 ° C and 25 ° C. get on.

The contact time between the aqueous solution and the silicon substrate is generally about 5 seconds to 5 minutes, preferably 10 seconds to 2 minutes, and more preferably between 20 seconds and 40 seconds. The duration of activation will be selected based on the size and number of metal particles that need to be formed on the surface of the silicon substrate. The size of the particles is about 5 nm to 15 nm, preferably about 10 nm, and will be advantageously selected.

The operation of bringing the surface of the substrate into contact with the activation solution is advantageously performed by immersing the substrate in the activation solution, and stirring is used as appropriate.

The treated substrate is thus advantageously rinsed in large quantities with deionized water and dried under a stream of nitrogen in order to remove any trace amounts of the activation solution.

Step ii)

The second step of the method of the present invention consists in forming a layer consisting essentially of nickel or cobalt on a substrate covered with gold particles or palladium particles. Basically understood as meaning greater than 90% by weight, other elements may be boron, phosphorus or tungsten.

A layer substantially formed of nickel or cobalt is advantageously uniform when covering a flat surface, and conformable when covering a three-dimensional structure (example of TSV vias and interconnects) that has been hollowed out in silicon. ).

Uniformity within the meaning of the invention is equal to the change in the thickness of the layer on the covering surface that is formed essentially of nickel or cobalt. The uniformity of the layer substantially formed of nickel or cobalt obtained according to the method of the present invention is advantageously less than 10%, preferably less than 5% and more preferably less than 1%.

Shape retention within the meaning of the present invention is equal to the ratio of the thickness of the layer at the top to the thickness of the layer at the bottom of the structure. The shape retention within the meaning of the present invention may also be equal to the change in the thickness of the layer on the assembly consisting of the top, side walls and bottom of the structure.

The shape retention of the layer substantially formed of nickel or cobalt obtained according to the method of the invention is advantageously between 90% and 110%, preferably more than 95%, more preferably more than 99%.

The trench is generally etched into the silicon and then metallized to the desired depth before the silicon wafer is thinned. The shape and size of the grooves can vary depending on the use of the device. The trench is generally characterized by its depth, its diameter at the opening, and the aspect ratio of the trench that defines the ratio of the depth to the diameter of the cavity. For example, a trench with an aspect ratio of 10: 1 has a diameter that is ten times smaller than its depth.

A layer formed essentially of nickel or cobalt is advantageously conformal when covering very deep structures: when the layer covers trenches with a high aspect ratio, especially greater than 5: 1, preferably greater than 10: 1, the top of the structure The coverage ratio to the bottom is advantageously between 90% and 110%.

The aspect ratio (expressed as the ratio of the depth of the cavity to the diameter of the opening) can vary from 5: 1 to 1000: 1, especially in the case of NAND memory devices, whose surface is composed of alternating layers of polycrystalline silicon and SiO ₂ . The method according to the invention advantageously makes it possible to deposit a layer of metallic nickel in a cavity exhibiting a particularly high aspect ratio (for example greater than 10: 1 and higher than 10: 1). The aspect ratio of the grooves can advantageously be extremely high and be between 10: 1 and 1000: 1, for example between 50: 1 and 500: 1 or between 100: 1 and 200: 1.

The method of the present invention makes it possible to cover a surface formed by nickel or cobalt at a surface recess (the diameter at its opening is in the range of 10 nm to 100 nm and the depth is in the range of 500 nm to 10 microns). The thickness is between 10nm and 150nm, and its shape retention is greater than 90%, preferably greater than 95%, and more preferably greater than 99%.

Metal deposits can be produced by a nonelectrochemical process that does not require an electroded substrate.

Usage can consist of a dry route (gas phase) method or a wet route (with aqueous solution) method.

Metal deposits can be nickel, cobalt, nickel-boron (NiB) alloy, cobalt-boron (CoB) alloy, nickel-phosphorus (NiP) alloy, cobalt-phosphorus (CoP) alloy, or cobalt-tungsten-phosphorus (CoWP) alloy .

Nickel deposits or cobalt deposits are preferably obtained via an electrodeless approach by exposing the activated substrate to an aqueous solution containing:-at least one metal salt of nickel or cobalt ions, preferably at a concentration between 10 ^-3 M Between 1M and 1M;-at least one reducing agent for nickel ions or cobalt ions, preferably in an amount between 10 ^-4 M and 1M; and-optionally at least one kind of stability for nickel ions or cobalt ions The agent is preferably in an amount between 10 ^-3 M and 1M.

The nickel or cobalt salt is preferably a water-soluble salt selected from the group consisting of chlorides, acetates, acetopyruvates, hexafluorophosphates, nitrates, perchlorates, sulfates And tetrafluoro Borate.

Preferred metal salts in the context of the present invention are selected from the group consisting of nickel sulfate or cobalt sulfate, nickel chloride or cobalt chloride, nickel acetate or cobalt acetate, or nickel amino besylate or cobalt amino besylate. For example, choose nickel sulfate hexahydrate.

Advantageously, the reducing agent may be selected from the group consisting of a phosphorus derivative, a boron derivative, glucose, formaldehyde and hydrazine.

The phosphorus derivative may be selected from hypophosphorous acid (H ₃ PO ₂ ) and a salt thereof and the boron derivative may be selected from a borane complex.

The reducing agent used is advantageously selected from borane derivatives and especially from dimethylamineborane, trimethylamineborane, triethylamineborane, pyridineborane, morpholineborane or tert-butylamineborane. Preferably, dimethylamine borane (DMAB) will be used.

The stabilizer may be selected from compounds which can be complexed with nickel ions or cobalt ions in order to prevent metal ions in the solution from being reduced by a reducing agent in the absence of a catalyst.

Stabilizers for metal ions can be selected from the group consisting of ethylenediamine, and acetate, propionate, succinate, glycolate, carotate, aminoacetate, malate, or citric acid salt. Preferably, one of citric acid or a salt thereof is selected so as to stabilize Ni ²⁺ ions or Co ²⁺ ions.

The pH of the aqueous solution can be acidic or basic and can be adjusted within the desired pH range by means of one or more pH modifying compounds (or buffers), such as described in Chemistry and Physics, published by CRC Press, David R. Lide Handbook - 84th Edition (Handbook of Chemistry and PhySics-84 th Edition) their pH "of the modified compound.

The aqueous solution may, for example, contain an agent, such as a non-polymeric amine, which makes it possible to adjust the pH to a value between 3 and 12, in order to adjust the pH between 8 and 12.

In general, the metal layer can be immersed in an aqueous solution as defined above by immersing the substrate at a temperature between 50 ° C and 90 ° C, preferably at 65 ° C, for a duration of 30 seconds to 30 depending on the required thickness of the layer Time period of minutes.

The basic steps of pre-wetting the substrate can be performed before exposing the substrate to the aqueous solution according to the invention. The substrate is, for example, immersed in an aqueous solution or a solution containing a metal salt, and the solution has a stabilizer for the metal salt and no reducing agent. Preferably, deionized water is used. The combination is subjected to a negative pressure of less than 500 mbar for 1 minute to 30 minutes, preferably 5 minutes to 15 minutes.

The nickel or cobalt layer can be deposited by rotating the substrate to be coated by applying ultrasound or megasound at a speed between 20 rpm and 600 rpm, or by Simple recycling of the applied aqueous solution is performed.

Using the aqueous solution described above within the above temperature range, a metal film exhibiting a thickness between 6 nm and 200 nm is obtained after contacting for a time period between 1 minute and 20 minutes.

According to one embodiment, the layer substantially formed of nickel or cobalt is a nickel-boron layer and is deposited by exposing the surface of the activated substrate to an aqueous solution containing a nickel salt, a boron-based reducing agent, and a stabilizer, the pH of the solution being between Between 9 and 12 and the temperature of the aqueous solution is between 50 ° C and 90 ° C.

The nickel salt-containing aqueous solution may advantageously additionally contain an inhibitor, which is adsorbed on the surface of the metal layer while the metal layer is being formed.

The inhibitor is preferably a polymer containing an "amine" group or a functional group especially selected from polymers and copolymers derived from: chitosan, poly (allylamine), poly (vinylamine), poly (ethylene) Pyridine), poly (aminostyrene), poly (ethyleneimine), poly (L-lysine) and acid (or protonated) forms of these polymers.

According to one embodiment of the invention, it is preferred to use a homopolymer or copolymer of poly (ethyleneimine) in a non-protonated form of poly (ethyleneimine).

The selection will consist of, for example, a linear poly (ethyleneimine) having a number average mole mass M _n between 500 g / mol and 25 000 g / mol.

The concentration of the polymer having an amine functional group used according to the invention is advantageously in the range of 1 ppm to 250 ppm, more specifically 1 ppm to 100 ppm, more preferably 1 ppm to 10 ppm, such as 1.5 ppm to 3 ppm (1 ppm is equivalent to 1 mg / kg of solution).

When the polymer having an amine functional group is poly (ethyleneimine), the pH of the aqueous solution is advantageously in the range of 8 to 12, preferably 8.5 to 10. It is especially about 9, for example between 8.9 and 9.1. In this case, it will be possible to use tetramethylammonium hydroxide (TMAH), triethanolamine, N, N-dimethylethanolamine or N-methylethanolamine as reagents, which makes it possible to adjust the pH.

The thickness of the nickel or cobalt layer is preferably uniform or conformal. It varies between 10 nm and 150 nm, more preferably between 10 nm and 100 nm, and in fact even between 10 nm and 40 nm. The thickness of the nickel or cobalt layer may even be between 10 nm and 20 nm.

Step iii)

Heat treatment can be performed in a tube furnace or on a heating plate.

The tube furnace is a heating electric boiler in the form of a tube, which makes it possible to accommodate samples with varying shapes and sizes. In the context of the present invention, a tube furnace contains a glass tube containing a sample by loading on a longitudinal axis. The selected and controlled gas flow can be combined with the heating of the assembly inside the glass tube.

In the context of a preferred application of the present invention, the method does not include the step of removing nickel or cobalt that has not migrated into the silicon and has been retained on the surface of the silicon substrate due to the heat treatment step.

Therefore, nickel or cobalt that does not migrate into the silicon caused by the heat treatment step is preferably removed without chemical cleaning.

This is because the method of the invention makes it extremely advantageous to obtain a thin and conformal nickel layer by interrupting the heat treatment. This nickel layer corresponds to the residual metal that has not migrated into the silicon. Inventors have discovered Specific conditions that make it possible to obtain silicide and metal stacks in a single step. This stack has so far been prepared in three steps: a long duration heat treatment to migrate the maximum amount of nickel into the silicon, chemically remove the nickel, clean the surface of the silicide and deposit a fresh layer of nickel. The method of the present invention makes it possible to reduce the amount of metal (nickel or cobalt) used, reduce the number of steps, and reduce the duration of the manufacturing method.

The substrate covered with the metal layer is subjected to rapid heat treatment at a temperature lower than or equal to 350 ° C, preferably lower than 300 ° C.

For example, the heat treatment temperature is between 200 ° C and 300 ° C, preferably between 210 ° C and 290 ° C, such as between 220 ° C and 270 ° C or between 230 ° C and 260 ° C. The duration of the treatment is advantageously less than 30 minutes, for example equal to 10 minutes.

In one embodiment, the metal is a nickel or cobalt alloy containing boron and is referred to as nickel-boron and cobalt-boron, respectively.

The boron content of the nickel-boron alloy or the cobalt-boron alloy is preferably 1 atomic% to 10 atomic%, for example, a boron content between two values selected from the group consisting of: 1 atomic%, 2 atomic%, 3 atomic%, 4 atomic%, 5 atomic%, 6 atomic%, 7 atomic%, 8 atomic%, 9 atomic%, and 10 atomic%.

For example, the boron content of a nickel-boron alloy or a cobalt-boron alloy may be 35 atomic% (which corresponds to 6 weight% for a nickel-boron alloy).

In the case of a nickel layer or a nickel-boron alloy layer, the rapid heat treatment temperature is preferably between 200 ° C and 325 ° C, and preferably between two values selected from the group consisting of 210 ° C, 220 ° C, 225 ° C, 230 ° C, 240 ° C, 250 ° C, 260 ° C, 270 ° C, 275 ° C, 280 ° C, 290 ° C, 300 ° C, 310 ° C, 320 ° C. The rapid heat treatment temperature is still preferably 240 ° C to 260 ° C, for example equal to 250 ° C. According to one embodiment, the metal alloy is nickel-boron, and the rapid heat treatment temperature is between 200 ° C and 325 ° C.

In the case of a cobalt layer or a cobalt-boron alloy layer, the rapid heat treatment temperature is preferably between 250 ° C and Between 375 ° C, and preferably between two values selected from the group consisting of: 250 ° C, 260 ° C, 270 ° C, 280 ° C, 290 ° C, 300 ° C, 310 ° C, 320 ° C, 330 ° C, 340 ℃, 350 ℃, 360 ℃, 370 ℃ and 375 ℃. The rapid heat treatment temperature is still preferably 250 ° C to 350 ° C, for example equal to 300 ° C. According to one embodiment, the metal alloy is cobalt-boron and the rapid heat treatment temperature is 250 ° C to 375 ° C, preferably 250 ° C to 350 ° C.

The duration of the rapid heat treatment is advantageously less than 30 minutes, such as less than 10 minutes, and can last from 1 minute to 10 minutes. The rapid heat treatment is preferably performed in a reducing atmosphere under standard pressure conditions (SPC).

The intercalation layer mainly contains the silicide of the stoichiometric SiM ₂ , M represents nickel or cobalt, which means that it contains a minimum weight percentage of SiM ₂ , wherein the minimum weight percentage based on the weight of the intercalation layer is selected from 50%, 60%, 70% , 80%, 85%, 90%, 95% and 99%. The intercalation layer is preferably composed of SiM ₂ .

Step iv)

The layer of residual metal is then covered with copper by conventional plating methods. These methods, which are well known to those skilled in the art, include the application of a current to the substrate and its immersion in an acidic or alkaline bath of copper ions. The plating composition used may correspond to a product sold under the aveni ^® , Sao ^® , Rhéa ^® or Janus ^® numbers.

Copper deposits can be in the form of "nucleated" layers of tens of nanometers or hundreds of nanometers, or in the form of deposits of approximately ten microns in thickness.

During this metallization step, the surface to be covered or the structure to be filled is in constant current mode (fixed applied current) or constant potential mode (fixed potential is applied, relative to the reference electrode as the case may be) or in pulse mode (to Current or voltage).

The second object of the present invention is used for manufacturing integrated circuits including interconnect lines and TSVs. A method comprising the steps of: A- providing a substrate covered by a silicon dioxide layer having an exposed silicon dioxide surface, B- finally etching a structure in the silicon dioxide layer, the structures intended to form the interconnections Line and these silicon perforations, C- forming a silicon layer on the exposed silicon oxide surface and obtaining an exposed silicon surface located at least inside the structure, D- the following steps, i- forming gold particles or palladium on the exposed silicon surface Particles to obtain an activated silicon surface, ii- forming a metal or metal alloy in the form of a layer on the activated silicon surface, the metal being selected from the group consisting of nickel and cobalt and the metal alloy being selected from the group consisting of nickel alloy and cobalt alloy And obtaining a stacked assembly, iii- applying a rapid heat treatment to the stacked assembly obtained in step ii), so as to form a contact with the silicon layer between a) the metal layer or the metal alloy layer and b) the silicon layer Insertion layer, which mainly contains SiM2 silicide, M represents nickel or cobalt, and the SiM2 silicide is formed by diffusing a metal or a metal alloy into a silicon layer, so that the residual portion of the metal layer or the residual metal having an exposed surface Close Layer in contact with the silicon layer, wherein the rapid thermal processing system in a rapid thermal processing temperature is less than or equal to 350 deg.] C the next, and iv- forming a copper layer on the exposed surface of the remaining part or residual portion of the metal alloy layer of the metal layer.

This method preferably does not include a step of stripping the residual metal after the heat treatment step and preferably does not include a step of depositing an additional nickel layer or a cobalt layer after the heat treatment step.

All features which have been disclosed in relation to the first object of the invention are applicable to the second object of the invention.

In the case of 3D IC devices, the structure depends on whether it meets the interconnect (or trench) or silicon through The function of the holes can be of various sizes. It is, for example, such that the width of the structure on the substrate surface or the diameter of the structure on the substrate surface is between 100 nm and 100 microns, and the depth of the structure is between 100 nm and 300 microns.

Silicon dioxide perforations can be manufactured by BEOL or FEOL (front-end process).

More specifically, the present invention aims at TSVs, that is, through-holes formed in integrated circuits after the BEOL (back-end process) step. In the method for manufacturing a TSV type, a TSV is generated, and a circuit including a silicon wafer is thinned before the TSV is generated.

One particularly advantageous embodiment of the present invention is a method of manufacturing an integrated circuit, which includes a step D of a heat treatment in a step subsequent to step C, which is performed at a temperature lower than the rapid heat treatment temperature of step iii). This is because some configurations of integrated circuits in three dimensions include stacking of materials, and the adhesion of the stack can be damaged due to excessively high processing temperatures, especially when the form of the integration is used in the steps after assembly of these materials. Method.

Therefore, the method of the present invention makes it possible to manufacture a stack of materials in a three-dimensional integrated circuit, and the adhesion of the stack is improved not only in the copper conductor network but also in the stacking of various layers. This may be exhibited by reducing the temperature applied in the steps following the step of assembling different integration layers.

The present invention also relates to a structure intended for manufacturing an electronic component in the third subject matter, which can be obtained according to the method according to the first or second objective of the present invention. The structure includes a stack of layers arranged in the following order: The silicon oxide layer, nickel silicide SiNi2 layer or cobalt silicide CoNi2 layer, cobalt-boron alloy layer or nickel-boron alloy layer, and copper layer, wherein the nickel silicide SiNi2 layer or the cobalt silicide CoNi2 layer and the silicon dioxide layer share a common surface.

For applications in the field of microelectronics, the substrate can be composed of: silicon coupons covered with a silicon dioxide (SiO ₂ ) layer with a thickness between 70nm and 110nm, followed by a thickness between 150nm and 2 microns Between layers of silicon, such as polycrystalline silicon.

Polycrystalline silicon, also commonly known as polysilicon or polySi, is understood to mean a specific form of silicon that is different from monocrystalline and amorphous silicon. In contrast to the first form (which consists of only one crystal) and the second form (which has no or very low crystalline coherence), polycrystalline silicon is composed of multiple small crystals with varying sizes and shapes.

The fourth object of the present invention relates to a method for manufacturing a photovoltaic cell, which includes a step of forming a copper wire by copper metallization of silicon according to the method of the second object of the present invention, which method is neither included in heat treatment The step of stripping the residual metal after the step does not include the step of depositing an additional layer of the metal after the heat treatment step.

All the features which have been disclosed in relation to the first object of the invention are applicable to the fourth object of the invention.

Unless otherwise indicated, these examples were performed under standard temperature and pressure conditions in ambient air (about 25 ° C at about 1 atom), and the reactants used were obtained directly commercially without additional purification.

Example 1: Activating a substrate covered with a polycrystalline silicon layer from a solution containing a gold salt, hydrofluoric acid, and an anionic surfactant as a starting material to obtain a nickel silicide (SiNi ₂ ) Attachment interface a) Surface cleaning:

Depending on the source of the substrate and the needs of the technicians, currently advanced technicians will know how to adjust the agreement applicable to clean surfaces. In our case, no cleaning is needed because the activating solution is also a slow etching solution. In this example, the substrate used is a silicon test piece having a side length of 1 cm × 2 cm and a thickness of 750 μm. The silicon test piece has a silicon dioxide (SiO ₂ ) layer with a thickness of about 260 nm and a thickness of about 100 nm. Covered with polycrystalline silicon.

b) Activation of substrate surface:

b1) Preparation of activation solution: 950 ml of deionized water and 50 ml of 49% by weight hydrofluoric acid are mixed in a clean plastic flask suitable for this type of mixing. 285 mg of gold (III) hydrochloride (HAuCl ₄ ) and 3 g of SDS (sodium dodecyl sulfate) were subsequently introduced. The solution then appeared bright yellow in color.

b2) Activation treatment on the substrate surface: The substrate described in step a) is immersed in the mixture prepared in step b1) for a given time of 30 seconds to 1 minute. The substrate thus treated was rinsed in large amounts with deionized water and dried under a stream of nitrogen.

c) NiB metal layer deposited by electrodeless method:

c1) Prepare electrodeless solution in advance: 31.11g of nickel sulfate hexahydrate (0.118mol), 44.67g of citric acid (0.232mol), 52.26g of N-methylethanolamine (0.700mol) and 2.5ppm, Mn = 600g / mol Polyethyleneimine (PEI) was sequentially introduced into a 1 liter container and a minimal amount of deionized water. The final pH was adjusted to 9 by alkali and the total volume was adjusted to 1 liter by deionized water.

Immediately before the following steps, one volume of the reducing solution was added to 9 volumes of the aforementioned solution. The reducing solution contained 28 g / l of dimethylamine borane (DMAB; 0.475 mol) and 60.00 g of N-methylethanolamine (0.798 mol).

c2) forming a NiB alloy layer on the polycrystalline silicon layer: a layer of NiB alloy is deposited on the surface of the substrate processed in step b), and the deposition is achieved by immersing the substrate in the electrodeless solution prepared previously and reaching 65 ° C, according to the The final thickness is required for a period of 30 seconds to 9 minutes. In this particular case, choose a time of 5.25 minutes.

d) formation of nickel silicide:

The sample obtained in step c) with the NiB alloy on top was subjected to rapid thermal annealing (RTA) under a reducing gas (4% H ₂ in N ₂ ) for 10 minutes. Several tests were performed when the temperature was changed from 250 ° C to 350 ° C. It can be operated with a tube furnace or a heating plate.

e) forming a copper layer:

By using a commercial solution (Aveni ^® AF600 or Janus ^®) of the copper layer is deposited in step d) of generating by coating the base plate. The electroplating method used in this example includes a step of copper growth, during which the processed substrate obtained from the result of step d) is cathodicly polarized in an electric mode and is simultaneously rotated at a speed of 60 rpm. The electrical protocol (DC; direct current) used was 16.25 mA / cm ² . The duration of this step is understood to depend on the desired thickness of the copper layer. This duration can be easily determined by those skilled in the art, and the growth of the membrane is a function of the charge passing through the circuit. Under the above conditions, the duration of the plating step of about 10 minutes makes it possible to obtain a coating having a thickness of about 2.4 microns. The copper-coated substrate was thus removed from the plating solution in about 2 seconds under zero speed rotation, and then rinsed with deionized water (18.2 Mohm / cm) and dried under a nitrogen rinse.

The metal stack thus obtained was annealed at 250 ° C. for 10 minutes in a reducing atmosphere (N ₂ + H ₂ mixture (4% H ₂ )).

f) Results:

FIG. 1 shows an ion polishing of an outline of a sample obtained according to steps a) to e) in a case where the thermal annealing temperature is equal to 250 ° C.

The profile of the samples observed by the SEM makes it possible to confirm the quality and thickness of the material stack: silicon (750 microns), silicon dioxide (260nm), polycrystalline silicon (35nm), SiNi ₂ (30nm), NiB (35nm), and copper ( 2.4 microns).

For each of the prepared samples, the adhesion of the stack was measured under the conditions of standard ASTM 3359. The results are summarized in the table below.

Example 2: Activating a substrate covered with a polycrystalline silicon layer, starting with a solution containing a gold salt, hydrofluoric acid and an anionic surfactant to obtain cobalt silicide (SiCo ₂ ) Attachment interface a) Surface cleaning:

This step is exactly the same as step a) of Example 1.

b) Activation of substrate surface:

This step with sub-steps b1) and b2) is identical to the other steps of Example 1.

c) Deposition of CoB metal layer by electrodeless method:

c1) Prepare electrodeless solution in advance: 5.8 g of cobalt chloride hexahydrate (0.025 mol), 8.9 g of citric acid (0.046 mol), 12 g of N-methylethanolamine (0.328 mol) and 2.5 ppm, Mn = 600 g / mol Polyethyleneimine (PEI) was sequentially introduced into a 200 ml container and a minimal amount of deionized water. The final pH was adjusted to 9 by alkali and the total volume was adjusted to 200 ml by deionized water.

Immediately before the following steps, one volume of the reducing solution was added to 9 volumes of the aforementioned solution. The reducing solution contained 28 g / l of dimethylamine borane (DMAB; 0.475 mol) and 60.00 g of N-methylethanolamine (0.798 mol).

c2) Forming a CoB alloy layer on the polycrystalline silicon layer: A layer of CoB metal alloy is prepared on the surface of the substrate treated in step b). The preparation is performed by immersing the substrate in the electrodeless solution previously prepared and reaching 74 ° C. The final thickness is required for a period of 30 seconds to 5 minutes. The duration of immersion in the electrodeless solution is determined in order to obtain a minimum thickness of cobalt with good uniformity and conductivity. In this example, the immersion period is 4 minutes and the CoB thickness is about 45 nm.

d) Formation of cobalt silicide (SiCo ₂ ):

As in step d) of Example 1, the sample obtained in step c) with a CoB alloy on top is placed in Rapid thermal annealing was performed at 250 ° C, 300 ° C, or 350 ° C for 10 minutes.

e) forming a copper layer:

This step is exactly the same as e) in Example 1.

f) Results:

FIG. 2 is an SEM photograph of an ion polishing showing an overview of a sample obtained according to steps a) to e) when the thermal annealing temperature is equal to 300 ° C.

The ion polishing according to the profile of the samples obtained in steps a) to e) allows the quality and thickness of the material stack to be confirmed: silicon (750 microns), silicon dioxide (260nm), polycrystalline silicon (35nm), SiCo ₂ (30nm ), CoB (35nm) and copper (2.4 microns).

Adhesion measurements on this stack according to standard ASTM 3359 provide 16/16 results, reinforcing the previously described concept. The Rs (resistivity) measurement at the end of the same step d) is about 10 ohms / square to 15 ohms / square.

Example 3: Activation of a substrate covered with a polycrystalline silicon layer, starting with a solution containing a gold (III) complex and hydrofluoric acid in order to obtain a nickel silicide (SiNi ₂ ) Attachment interface a) Surface cleaning:

This step is exactly the same as step a) according to Example 1.

b) Activation of substrate surface:

b1) Preparation of activation solution: 40 mg of gold (III) hydrochloride (HAuCl ₄ ), 20 mg of bipyridine and 10 ml of EDI were continuously introduced into a 25 ml round bottom flask. The mixture was brought to reflux for 5 to 10 minutes. The first yellow precipitate formed dissolved after a few minutes when the solution had reached the boiling point. This solution was then mixed with 40 ml of 2.5% HF.

b2) Activation treatment on the substrate surface: The substrate described in step a) is immersed in the mixture prepared in step b1) for a given time of 30 seconds to 1 minute. The processed substrate was thus rinsed in large amounts with deionized water and dried under a stream of nitrogen.

c) Deposition of metal NiB layer by electrodeless method:

This step is consistent with step c) of Example 1.

d) Formation of nickel silicide (SiNi ₂ ):

The sample obtained in step c) with a NiB alloy on top was subjected to rapid thermal annealing (RTA) under a reducing gas at 250 ° C. for ten minutes.

e) forming a copper layer:

This step is exactly the same as e) in Example 1.

f) Results:

Adhesion measurements on this stack according to standard ASTM 3359 provided a 16/16 result.

Claims (14)

A method for manufacturing an integrated circuit including interconnects and through-silicon vias. The method includes the following steps: A- providing a substrate covered by a silicon dioxide layer having an exposed silicon dioxide surface, and B- finally on the silicon dioxide Etching structures in layers, the structures are intended to form the interconnect lines and the silicon perforations, C- forming a silicon layer on the exposed silicon dioxide surface, and obtaining an exposed silicon surface located at least inside the structures, D- The following steps: i- forming gold particles or palladium particles on the exposed silicon surface to obtain an activated silicon surface, ii- forming a metal or metal alloy in the form of a layer on the activated silicon surface, the metal being selected from the group consisting of nickel and A group consisting of cobalt and the metal alloy is selected from the group consisting of nickel alloys and cobalt alloys and a stack of layers is obtained, iii- applying a rapid heat treatment to the stack of layers obtained in step ii) in order to a) the metal Layer or the metal alloy layer and b) the silicon layer forms an intervening layer which is in contact with the silicon layer and which mainly contains SiM ₂ silicide, M represents nickel or cobalt, and the SiM ₂ silicide is obtained by making the metal Or the metal alloy diffuses to the Forming a layer to contact the silicon layer with the remaining portion of the metal layer or the metal layer with the exposed surface, wherein the rapid heat treatment is performed at a rapid heat treatment temperature lower than or equal to 350 ° C, and iv- A copper layer is formed on the exposed surface of the remaining portion of the metal layer or the remaining portion of the metal alloy layer. The method of claim 1, wherein the thickness of the metal layer or the metal alloy layer deposited in step ii) is between 10 nm and 150 nm, and wherein the residual metal layer or the residual metal alloy layer is conformal and The thickness is 5 nm to 100 nm. The method of claim 1 or 2, wherein step i) comprises forming gold particles. The method of claim 1 or 2, wherein the intercalation layer comprises SiM ₂ and has a thickness of 10 nm to 200 nm. The method of claim 1 or 2, wherein the metal alloy is nickel-boron, and wherein the rapid heat treatment temperature is 200 ° C to 325 ° C, preferably 225 ° C to 275 ° C. The method of claim 1 or 2, wherein the metal alloy is cobalt-boron, and wherein the rapid heat treatment temperature is 250 ° C to 375 ° C, preferably 250 ° C to 350 ° C. The method according to claim 1 or 2, wherein the rapid heat treatment is performed in a reducing atmosphere for a period of time between 1 minute and 30 minutes, and preferably for a period of time between 1 minute and 10 minutes. The method of claim 1 or 2, wherein the silicon of the silicon layer is doped or undoped silicon, and is selected from the group consisting of polycrystalline silicon, amorphous silicon, and crystalline silicon. The method of claim 1 or 2, wherein the structures have a width or average diameter between 100 nm and 100 microns and a depth between 100 nm and 300 microns on the surface of the substrate. The method of claim 1 or 2, wherein step D is followed by step E, which comprises a heat treatment performed at a temperature lower than the rapid heat treatment temperature of step iii). If the method of item 1 or 2 is requested, the method does not include the step of forming an additional metal layer on the residual metal layer between steps iii) and iv), and the method does not include between step iii) and step iv) A step of forming an additional metal alloy layer on the residual metal alloy layer is included. A method for forming silicide on a substrate, the method comprising the steps of providing a substrate covered with a silicon layer having an exposed silicon surface, and the following steps: i- forming gold particles or palladium particles on the exposed silicon surface to obtain Activated silicon surface, ii- forming a metal or metal alloy in the form of a layer on the activated silicon surface, the metal being selected from the group consisting of nickel and cobalt and the metal alloy being selected from the group consisting of nickel alloy and cobalt alloy, and Obtaining a stack of layers, iii- applying a rapid thermal treatment to the stack of layers obtained in step ii) to form an intervening layer between a) the metal layer or the metal alloy layer and b) the silicon layer, which is in contact with the The silicon layer is in contact and it mainly contains SiM ₂ silicide, M represents nickel or cobalt, and the SiM ₂ silicide is formed by diffusing the metal or the metal alloy into the silicon layer in order to make the metal having an exposed surface The remaining portion of the layer or the residual metal alloy layer is in contact with the silicon layer, wherein the rapid heat treatment is performed at a rapid heat treatment temperature lower than or equal to 350 ° C. A structure intended for the manufacture of an electronic component, obtainable by a method as claimed in any one of claims 1 to 11 or by a method as claimed in claim 12, the structure comprising a stack of layers arranged in the following order: silicon layer, siliconized A nickel SiNi2 layer or a cobalt silicide CoNi2 layer, a cobalt-boron alloy layer or a nickel-boron alloy layer, and a copper layer, wherein the nickel silicide SiNi2 layer or the cobalt silicide CoNi2 layer shares a common surface with the silicon dioxide layer. A method for manufacturing a photovoltaic cell, comprising a step of forming a copper wire by copper metallization of a silicon substrate according to the method of claim 12, wherein the method for manufacturing a photovoltaic cell does not include stripping after a heat treatment step The step of residual metal does not include the step of depositing an additional layer of the metal after the heat treatment step.