TWI631459B - Memory device and method of operation - Google Patents

Abstract

The present invention provides a memory device including an instruction decoding unit, a control logic unit, a first memory unit, and a second memory unit. The instruction decoding unit decodes an input command and generates a decoded signal; the control logic unit outputs a control signal according to the decoded signal; the first memory unit has a first memory array and a first page buffer; A second memory unit has a second memory array and a second page buffer. Wherein, when the input command is a predetermined command, the predetermined command accesses the data in the first memory unit and the backup data in the second memory unit at the same time.

Description

Memory device and its operation method

The present invention relates to a memory device, and more particularly to a memory device having high-speed read/write and erase, and having high reliability.

With the development of the memory device, the capacity that the memory device can store is also increased, and the cost per unit storage space of the memory device is correspondingly reduced, thereby improving the processing efficiency and reliability of the memory device. The main goal is to make the data work correctly, safely, and quickly.

Please refer to FIG. 1A at the same time. FIG. 1A shows a schematic diagram of a memory device in the prior art reading (Read) one page of a memory array. As can be understood from FIG. 1A, since the input command IS of the prior art memory device 11 uses a command code 11a, an address 11b, and a confirm code C. The page buffer (Page Buffer) of the memory array 11c is enabled by the address code 11b to read the data stream of the memory array 11c, and the reading process is confirmed by the confirmation code C.

Please refer to FIG. 1B at the same time. FIG. 1B shows a schematic diagram of reading one of the two memory arrays by the memory device 11 of the prior art. It can be understood from FIG. 1B that when the user needs to read the two body arrays 11c and 12c, the input command needs to use two sets of Command Codes 11a and 12a and two sets of Address Codes 11b respectively. 12b, and the page buffers 11d and 12d of the memory arrays 11c and 12c are enabled by the address codes 11b and 12b, respectively, for reading Data streams within memory arrays 11c and 12c. Therefore, the time at which the memory device 11 processes its input command needs to be correspondingly increased.

Similarly, please refer to the 1C, 1D, 1E, and 1F diagrams at the same time. The 1C shows a schematic diagram of the prior art memory device writing data to one of the memory arrays. The 1D figure shows the prior art. The memory device writes the data into one of the two memory arrays. FIG. 1E shows a schematic diagram of the prior art memory device erase (Erase) data in a memory array, and FIG. 1F shows the prior art erase two. A schematic diagram of the data in a memory array. The operation principle is the same as the above, and will not be described again. Therefore, the existing memory device cannot simultaneously read, store, or erase a plurality of memory unit data in a single input command. In this way, if there is any omission or error in the data reading and writing process, the correctness of the data in the memory unit cannot be ensured. For example, the existing flash memory device does not have high reliability.

Therefore, if the existing memory device needs to read, store, or erase the data in a plurality of memory cells, it is necessary to input the command through a plurality of pens, so that the memory device needs to spend more. Time processing the input commands reduces the processing speed of the memory device.

One of the objects of the present invention is to provide a memory device that can simultaneously read, store, or erase data of a plurality of memory cells.

One of the objects of the present invention is to provide a memory device, With high speed processing speed.

One of the objects of the present invention is to provide a memory device with high reliability.

An embodiment of the present invention provides a memory device including an instruction decoding unit, a control logic unit, a first memory unit, and a second memory unit. The instruction decoding unit decodes an input command and generates a decoded signal; the control logic unit outputs a control signal according to the decoded signal; the first memory unit has a first memory array and a first page buffer; A second memory unit has a second memory array and a second page buffer. Wherein, when the input command is a predetermined command, the predetermined command accesses the data in the first memory unit and backs up the data in the second memory unit at the same time.

An embodiment of the present invention provides a memory operating method, including: decoding an input command and generating a decoded signal; and outputting a control signal according to the decoded signal; wherein, when the input command is a predetermined command, the predetermined command is for the same data At the same time, a material is accessed in a first memory unit and the data is backed up in a second memory unit.

Please refer to FIG. 2A. FIG. 2A is a schematic diagram showing an embodiment of a memory device of the present invention. The memory device 200 includes an instruction decoding unit 101, a control logic unit 102, a first memory unit 103, and a second memory unit 104.

Please note that the memory device 200 according to an embodiment of the present invention is implemented by a NAND flash memory. In another embodiment, the memory is The device 200 can be implemented as a Solid State Disk (SSD) and/or, and/or a memory card, and/or a flash drive.

The memory unit 103 has a first memory array 103a and a first page buffer 103b. The second memory unit 104 has a second memory array 104a and a second page buffer 104b. The first page buffer 103b is coupled to the control logic unit 102 and the first memory array 103a, and the second page buffer 104b is coupled to the control logic unit 102 and the second memory array 104a.

When the instruction decoding unit 101 receives an input instruction IS, the instruction decoding unit 101 decodes the input instruction IS. In other words, the instruction decoding unit 101 generates a decoded signal DS according to the input instruction IS. The control logic unit 102 outputs a control signal CS according to the decoded signal DS, and the control logic unit 102 causes the memory arrays 103a and 103b to read (read), write (program), erase (Erase) and the like through the control signal CS. .

Wherein, when the input command IS is a predetermined command PS, the predetermined reference PS command accesses the data in the first memory unit 103 and backs up the data in the second memory unit 104 at the same time for the same data; wherein the present invention The access system is defined as a data processing program for reading, writing, and erasing. The definition of the backup means that the second memory unit 104 performs the same operation as the first memory unit 103. In other words, when the input command IS is a predetermined command PS, the decoding unit 101 decodes the predetermined command PS and generates the decoded signal DS, and the control logic unit 102 outputs the control signal CS according to the decoded signal DS while enabling the first memory array 103a. First page buffer 103b, second memory array 104a, and second page buffer 104b performs processing procedures such as reading, writing, and erasing.

In an embodiment, the predetermined instruction PS can be regarded as an access backup instruction, and the access backup instruction includes a driving the first memory unit instruction and a driving the second memory unit instruction, so the access backup instruction can be used to enable The first memory unit 103 and the second memory unit 104 cause the first memory unit 103 and the second memory unit 104 to perform an operation of accessing and backing up.

Please note that in an embodiment, when the input command IS is not the predetermined command PS, that is, when the input command IS is the general command NS, the control logic unit 102 outputs the control signal CS according to the decoded signal DS. The first memory array 103a and the first page buffer 103b perform processing procedures such as reading, writing, and erasing, and the second memory array 104a and the second page buffer 104b are not enabled for reading and writing. Processing procedures such as entering and erasing.

Please refer to FIG. 2B at the same time. FIG. 2B is a schematic diagram showing an embodiment of a memory device according to the present invention, wherein the control logic unit 102 includes a determining unit 102a. The determining unit 102a is coupled to the instruction decoding unit 101, and the determining unit 102a can be used to determine that the input command IS is a predetermined command PS or a general command NS.

Please note that when the input command IS is the predetermined command PS, the decoded signal DS includes the enable signals ES1 and ES2.

In an embodiment of the invention, the determining unit 102a further includes a first AND gate 21 and a second AND gate 22. The first end of the first AND gate 21 is coupled to the instruction decoding unit 101, and receives an address code (Address) A. The second end of the first AND gate 21 is coupled to the enable signal ES1. The first end of the second AND gate 22 is coupled to the instruction decode list The element 101 receives the address code A, and the second end of the second AND gate is coupled to the enable signal ES2.

Please refer to FIG. 3A at the same time. FIG. 3A shows a schematic diagram of a memory device 200 according to an embodiment of the present invention simultaneously reading one page of two memory arrays through a predetermined command. The judging unit 102a of the present embodiment performs logical judgment using the first AND gate 21 and the second AND gate 22 to determine whether it is the predetermined command PS.

In an embodiment, if the input command IS is the predetermined command PS, the predetermined command PS is decoded by the command decoding unit 101, and the enable signals ES1 and ES2 are respectively signals of logic 1. In this way, the first AND gate 21 and the second AND gate 22 can select and enable one of the memory arrays 103a and 104a by the address code A in the decoded signal DS. In other words, the memory device 200 is re-transmitted. The address code 11b selects the page number to be read, and the first memory array 103a, the first page buffer 103b, the second memory array 104a, and the second page buffer 104b are simultaneously made by the address code A. It is enabled, in other words, the second memory unit 104 performs a program for reading with the first memory unit 103 at the same time, and confirms the reading process by the confirmation code C.

Conversely, if the input command IS is the general command NS, in this embodiment, the enable signal ES1 is a logic 1 signal, and the enable signal ES2 is a logic 0 signal, and the first AND gate 21 is further caused by the address code A. The first memory array 103a and the first page buffer 103b are enabled.

Therefore, when the input command IS is the predetermined command PS, the page numbers of the read memory arrays 103a and 104a are selected by the address code A, and the first AND gate 21 and the second AND gate 22 are enabled signals ES1. And the ES2 enable, in other words, the control signal CS simultaneously enables the first memory array 103a, the first page buffer 103b, the second memory array 104a, and the second page buffer 104b. Conversely, when the input command is IS for the general command NS, since the enable signal ES2 is logic 0, the second AND gate 22 is disabled, and the page number of the memory array 103a read by the address code A is selected by the address code A. The control signal CS enables the first memory array 103a and the first page buffer 103b.

In addition, in an embodiment of the present invention, the first memory unit 103 further includes a first row decoding unit 103c and a first column decoding unit 103d; the second memory unit 104 includes a second row decoding unit 104c, and a second Column decoding unit 104d. The first row decoding unit 103c is coupled to the control logic unit 102; the first column decoding unit 103d is coupled to the control logic unit 102; and the second row decoding unit 104c is coupled to the control logic unit 102; Unit 104d is coupled to control logic unit 102.

As described above, in an embodiment, when the input command IS is the predetermined command PS, the control signal CS of the control logic unit 102 simultaneously enables the first row decoding unit 103c, the first column decoding unit 103d, and the second row. The decoding unit 104c and the second column decoding unit 104d. In this way, the memory device 200 can read the data stream in the first memory array 103a and the second memory array 104a.

Please note that, in the prior art memory device 11, if two memory arrays 103a and 104a are to be read, the required instruction length of the input command IS is longer than the instruction length of the present invention. Therefore, in the prior art, the time required for the memory device 11 to process the input command IS is relative to the memory device 200 of the present invention. The pair is long, so that the memory device 200 is operated by the predetermined command PS of the present invention, and the reading speed of the memory device 200 can be improved.

Please refer to FIG. 3B at the same time. FIG. 3B is a schematic diagram showing that the memory device 200 according to an embodiment of the present invention simultaneously writes data into one of two memory arrays through a predetermined instruction. As described above, when the input command IS is the predetermined command PS, after the predetermined command PS is decoded by the command decoding unit 101, the enable signals ES1 and ES2 are respectively signals of logic 1. In this way, the first AND gate 21 and the second AND gate 22 can select and enable one of the memory arrays 103a and 104a by the address code A in the decoded signal DS. In other words, the memory device 200 is re-transmitted. The address code 11b selects the page number to be written, and the first memory array 103a, the first page buffer 103b, the second memory array 104a, and the second page buffer 104b are simultaneously enabled by the address code A. The input data IN is written to the memory arrays 103a and 104a. Therefore, the second memory unit 104 writes the input data D1 at the same time as the first memory unit 103, and confirms the writing process by the confirmation code C.

Therefore, if the memory device 11 of the prior art needs to write two memory arrays 103a and 104a, the required instruction length of the input command IS is longer than the instruction length of the present invention, so in the prior art The time required for the memory device 11 to process the input command IS is relatively long relative to the memory device 200 of the present invention. When the memory device 200 is operated by the predetermined command PS of the present invention, the memory device 200 can be upgraded. Write speed. In addition, the reliability of the memory device 200 can be improved by achieving the effect of multiple backups with a short command length.

Please refer to FIG. 3C at the same time. FIG. 3C is a schematic diagram showing the memory device 200 according to an embodiment of the present invention erasing two memory arrays simultaneously by a predetermined command. When the input command IS is the predetermined command PS, after the predetermined command PS is decoded by the command decoding unit 101, the enable signals ES1 and ES2 are respectively signals of logic 1. In this way, the first AND gate 21 and the second AND gate 22 can decode the address code A in the signal DS and enable all page numbers of the memory arrays 103a and 104a, in other words, the memory device 200 transmits the address code. 11b selects a memory block to be erased, and the first memory array 103a, the first page buffer 103b, the second memory array 104a, and the second page buffer 104b are simultaneously made by the address code A It is enabled and erased, and the erase code is confirmed by the confirmation code C.

Please refer to the flowchart of FIG. 4 at the same time. FIG. 4 is a flow chart showing a method for operating a memory according to the present invention, and the method for operating the memory is used in the operation of a non-volatile memory in one embodiment. The method includes the following steps: Step S401: Start; Step S402: Decode an input command and generate a decoded signal; Step S403: Output a control signal according to the decoded signal; Step S404: When the input command is a predetermined command, the predetermined command The PS system accesses a data in a first memory unit and backs up the data in a second memory unit at the same time; the step S405: the control signal simultaneously enables a first memory array, a first a page buffer, a second memory array, and a second page buffer; and step S406: ending.

In summary, the memory device and the memory operating method of the present invention perform a processing procedure of reading, writing, and erasing the first memory array and the second memory array simultaneously through a predetermined command PS. The memory device of the present invention operates through a predetermined instruction, and can directly process the first memory array and the second memory array at the same time, and solves the prior art requirement to use two general instructions at two different times to achieve the first memory. The effect of batch processing of the volume array and the second memory array. In addition, the command length of the predetermined command is shorter than that of the prior art, so that the time for processing the memory device can be saved. Moreover, the predetermined command can simultaneously read, write, and erase the first memory array and the second memory array at the same time, thereby improving the reliability of the memory device.

200, 11‧‧‧ memory devices

11a‧‧‧ instruction code

11b‧‧‧ address code

101‧‧‧ instruction decoding unit

102‧‧‧Control logic unit

102a‧‧‧judging unit

103‧‧‧First memory unit

103a, 11c‧‧‧ first memory array

103b, 11d‧‧‧ first page buffer

103c‧‧‧first line decoding unit

103d‧‧‧First column decoding unit

104‧‧‧Second memory unit

104a, 12c‧‧‧ second memory array

104b, 12d‧‧‧ second page buffer

104c‧‧‧second line decoding unit

104d‧‧‧Second column decoding unit

21‧‧‧First AND gate

22‧‧‧Second AND gate

IS‧‧‧ input instructions

DS‧‧‧ decoding signal

CS‧‧‧Control signal

PS‧‧‧Scheduled order

ES1, ES2‧‧‧ enable signal

C‧‧‧Confirmation code

D1‧‧‧ Input data

NS‧‧ General Instruction

A‧‧‧ address code

S401~S406‧‧‧Steps

Figure 1A shows a schematic diagram of a prior art memory device reading one page of a memory array, respectively.

Figure 1B shows a schematic diagram of a prior art memory device reading one of two memory arrays, respectively.

1C shows a schematic diagram of a prior art memory device writing data to one of a memory array.

Figure 1D shows a schematic diagram of a prior art memory device writing data to one of two memory arrays.

1E shows a schematic diagram of a prior art memory device erasing data in a memory array.

Figure 1F shows a schematic diagram of prior art erase data in two memory arrays.

Fig. 2A is a view showing an embodiment of a memory device of the present invention.

Fig. 2B is a view showing an embodiment of a memory device of the present invention.

FIG. 3A is a diagram showing a memory device of an embodiment of the present invention simultaneously reading one of two memory arrays through a predetermined command PS.

FIG. 3B is a diagram showing the memory device of the embodiment of the present invention simultaneously writing data to one of two memory arrays through a predetermined command PS.

FIG. 3C is a schematic diagram showing the memory device of the embodiment of the present invention erasing two memory arrays simultaneously through a predetermined command PS.

Figure 4 is a flow chart showing a method of operating a memory of the present invention.

Claims (12)

A memory device includes: an instruction decoding unit that decodes an input command and generates a decoded signal; a control logic unit that outputs a control signal according to the decoded signal; and a first memory unit having a first memory An array and a first page buffer; and a second memory unit having a second memory array and a second page buffer; wherein, when the input command is a predetermined command, the predetermined command is the same At the same time, the data is accessed by the first memory unit and accessed in the second memory unit, and the memory device is non-volatile memory. The memory device of claim 1, wherein the predetermined instruction is an access backup instruction, and the access backup instruction includes a driving the first memory unit instruction and a driving the second memory unit instruction. . The memory device according to claim 1, wherein the definition of the backup refers to performing the same operation in the second memory unit as in the first memory unit. The memory device of claim 1, wherein the control signal of the control logic unit simultaneously enables the first memory array and the first page when the input command is the predetermined command A code buffer, the second memory array, and the second page buffer. The memory device of claim 4, wherein, when the input command is a general command, the control signal of the control logic unit simultaneously enables the first memory array and the first page buffer . The memory device of claim 5, wherein the control logic unit comprises a determining unit, the determining unit is configured to determine that the input command is the predetermined command or the general command; and the decoded signal includes a The first consistent signal and the second enable signal. The memory device of claim 6, wherein the determining unit comprises: a first AND gate, a first end coupled to the address signal, and a second end coupled to the first enabler And a second AND gate, a third end coupled to the address signal and the first end, and a fourth end coupled to the second enable signal; wherein, when the input command is the predetermined command The first AND gate and the second AND gate are enabled by the first enable signal and the second enable signal, so that the control signal simultaneously enables the first memory array and the first page buffer The second memory array and the second page buffer; and, when the input command is the general command, the first AND gate is enabled, and the second AND gate is disabled, the control is enabled The signal simultaneously enables the first memory array and the first page buffer. The memory device of claim 7, wherein the first memory unit comprises: a first row decoding unit coupled to the control logic unit; and a first column decoding unit coupled to The control logic unit, and the second memory unit includes: a second row decoding unit coupled to the control logic unit; and a second column decoding unit coupled to the control logic unit; When the input command is the predetermined command, the control signal of the control logic unit simultaneously enables the first row decoding unit, the first column decoding unit, the second row decoding unit, and the second column decoding unit. The memory device of claim 7, wherein the predetermined instruction is for reading a program, writing a program, and erasing a program. The memory device of claim 8, wherein the memory device is a NAND flash memory. The memory device of claim 9, wherein the memory device is a solid state drive and/or a memory card and/or a flash drive. A method for operating a memory, comprising: decoding an input command and generating a decoded signal; and outputting a control signal according to the decoded signal; wherein, when the input command is a predetermined command, the predetermined command is for the same data at the same time In a first memory unit Accessing a data and accessing the data in a second memory unit is used to operate the non-volatile memory.