TWI630616B - Row decoder and memory system using the same - Google Patents

Abstract

A column decoder includes a plurality of address lines, a first selection circuit, and a second selection circuit. The first selection circuit is coupled to the address lines and has a latch function for enabling and latching the first selection signal to select the first word line in the first memory cell array. The second selection circuit coupled to the address lines does not have a latching function for enabling the second selection signal to select the second word line in the second memory cell array.

Description

Column decoder and memory system using the same

The present disclosure generally relates to a column decoder and a memory system using the same.

Memory devices have been widely used in various electronic products. A typical memory device includes a plurality of word lines, bit lines, and memory cells coupled to the word lines and bit lines. When a word line is selected, the memory cells coupled to the selected word line will be accessed. In general, the selection of word lines can be accomplished by decoding the address information by the column decoder.

In order to improve memory performance, the memory device can employ a shared row decoder. Through the shared column decoder, two or more memory cell arrays in the memory device can perform independent operations at the same time, such as read while read or read while write operations. However, conventional shared column decoders require a large number of address lines to operate independently on each memory cell array, which would occupy a large circuit area and line routing.

The disclosure relates to a column decoder and a memory system using the same. The column decoder may include one or more selection circuit pairs to select word lines in the first memory cell array and the second memory cell array in the memory device. Each of the selection circuit groups includes a first selection circuit and a second selection circuit. The first selection circuit can include a first word line driver having a latching function. The second selection circuit can include a second word line driver that does not have a latching function. The address control logic can sequentially provide the address signals to a set of address lines for independent operation of the first and second memory cell arrays at the same time, such as reading in a read or in a read. operating. Through the column decoder proposed in the disclosure, the first selection circuit and the second selection circuit in one selection circuit group can share the same group address line, so that the address line and the required circuit area can be effectively saved.

According to an embodiment, a column decoder is proposed. The column decoder includes a plurality of address lines, a first selection circuit, and a second selection circuit. The first selection circuit is coupled to the address lines and has a latch function for enabling and latching the first selection signal to select the first word line in the first memory cell array. The second selection circuit coupled to the address lines does not have a latching function for enabling the second selection signal to select the second word line in the second memory cell array.

According to another embodiment, a memory system is proposed. The memory system includes a first memory cell array, a second memory cell array, address translation logic, and a column decoder. The first memory cell array includes a first word line. The second memory cell array includes a second word line. The address conversion logic is configured to provide a plurality of address signals for accessing the first memory cell array and the second memory cell array, the address signals including the first address signal and the second address signal. The column decoder is coupled to the first memory cell array and the second memory cell array. The column decoder includes a plurality of address lines, a first selection circuit, and a second selection circuit. The address lines are coupled to the address translation logic for sequentially receiving the address signals from the address translation logic. The first selection circuit is coupled to the address lines and has a latch function for responding to the first address signal enable and latching the first selection signal to select the first word line. The second selection circuit coupled to the address lines does not have a latching function for enabling the second selection signal in response to the second address signal to select the second word line.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

FIG. 1 is a block diagram of a memory system 10 in accordance with an embodiment of the present disclosure. The memory system 10 includes a first memory cell array 102, a second memory cell array 104, address translation logic 106, and a column decoder 108.

Each of the first memory cell array 102 and the second memory cell array 104 can include a plurality of memory cells at the intersection of the word line and the bit line. In this example, the first memory cell array 102 includes a plurality of word lines WLR_1~WLR_m, and the second memory cell array 104 includes a plurality of word lines WLL_1~WLL_m, where m is a positive integer. In a read cycle, when a word line is selected, the data in the memory cell coupled to the selected word line will be output via a bit line (not shown).

The address translation logic 106 can provide an address signal to the address line ADDL in response to one or more requests from the host device 12. The address signals correspond to a physical location in the first memory cell array 102 or the second memory cell array 104. Address translation logic 106 can be implemented, for example, by logic circuitry.

The column decoder 108 is coupled to the first memory cell array 102 and the second memory cell array 104. Column decoder 108 may select word lines in first memory cell array 102 and/or second memory cell array 104 in response to address signals provided from address translation logic 106.

The column decoder 108 includes a plurality of address lines ADDL, a plurality of selection circuits 1082_1 to 1082_m for the first memory cell array 102, and a plurality of selection circuits 1084_1 to 1084_m for the second memory cell array 104.

The selection circuits 1082_1 to 1082_m share the address line ADDL with the selection circuits 1084_1 to 1084_m. Each selection circuit can be responsive to the matched address signal to enable selection of a selection signal for the corresponding word line.

For example, when the selection circuit 1082_1 receives the matched address signal from the address line ADDL, the selection circuit 1082_1 will enable the selection signal for selecting the word line WLR_1 such that the word line WLR_1 is selected. If the selection signal for the word line WLR_1 becomes disabled, the word line WLR_1 is deselected.

In this embodiment, a pair of selection circuits corresponding to the same column of word lines in the first and second memory cell arrays 102, 104 is regarded as a selection circuit group. For example, the selection circuits 1082_1 and 1084_1 can be regarded as a selection circuit group for selecting the word lines WLR_1 and WLL_1 of the first column of the first and second memory cells 102, 104.

According to an embodiment of the present disclosure, for a two selection circuit in a selection circuit group, a selection circuit is implemented by a word line driver having a latch function (hereinafter, the selection circuit is a first selection circuit). The other selection circuit is implemented by a word line driver that does not have a latch function (hereinafter referred to as the second selection circuit). Taking the first figure as an example, in one embodiment, the selection circuits 1082_1~1082_m for the first memory cell array 102 are both the first selection circuit, and the selection circuits 1084_1~1084_m for the second memory cell array 104 are the first Two selection circuits. In another embodiment, the selection circuits 1082_1~1082_m are both used as the second selection circuit, and the selection circuits 1084_1~1084_m are all used as the first selection circuit. In another embodiment, a part of the selection circuits 1082_1~1082_m is used as the first selection circuit, and the other part is used as the second selection circuit, and a part of the selection circuits 1084_1~1084_m is used as the second selection circuit, and the other part is The first selection circuit.

The first selection circuit can maintain the state of a selected word line even if an unmatched address signal is received. Through this feature, the first and second selection circuits are sequentially provided with matching address signals, so that the first and second memory cells 102 and 104 can operate independently at the same time. Since the first and second selection circuits share the same set of address lines ADDL, the address traces and the required circuit area can be effectively reduced.

FIG. 2 is a block diagram of a column decoder 20 in accordance with an embodiment of the present disclosure. Column decoder 20 may include one or more selection circuit groups. In this example, the column decoder 20 is shown to include only one selection circuit group.

As shown in FIG. 2, the selection circuit group includes a first selection circuit 22 for selecting the first word line WLR and a second selection circuit 24 for selecting the second word line WLL.

Taking FIG. 1 as an example, if the first selection circuit 22 and the second selection circuit 24 are the selection circuits 1082_1 and 1084_1, respectively, the first word line WLR represents the word line WLR_1, and the second word line WLL represents the word. Yuan line WLL_1. It is to be understood that the present invention is not intended to limit the invention. In some embodiments, the first word line WLR may be the i-th column word line in the first memory cell array 102 and selected by the corresponding selection circuit 1082_i, and the second word line WLL may be the second The j-th column of word cells in the memory cell array 104 is selected by a corresponding selection circuit 1084_j, wherein the values of i, j may be the same or different.

The first selection circuit 22 and the second selection circuit 24 share the same set of address lines ADDL and receive address signals from the address line ADDL. The address signal provided on the address line ADDL may include a first address signal and a second address signal.

The first selection circuit 22 is coupled to the address line ADDL and has a latch function for enabling and latching the first selection signal SE1 to select the first word line WLR in the first memory cell array 102.

As shown in FIG. 2, the first selection circuit 22 includes first decoding logic 222 and a first word line driver 224. The first decoding logic 222 is coupled to the address line ADDL for responding to the first address signal to enable the first driving signal DS1, and is responsive to other address signals (eg, the second address signal) on the address line ADDL. The first drive signal DS1.

The first word line driver 224 is coupled to the first decoding logic 222 and includes a latch circuit 2242. The latch circuit 2242 is controlled by the latch control signal ENB. The latching circuit 2242 can enable the first selection signal SE1 when the first driving signal DS1 is enabled during the period when the latching control signal ENB is enabled, and after the latching control signal ENB becomes disabled, The first selection signal SE1 that maintains the output enable is maintained.

In this disclosure, the terms "enable" and "disabled" refer to different signal states. In an exemplary and non-limiting example, when a signal is pulled high, the signal is enabled; when a signal is pulled low, the signal is disabled.

The second selection circuit 24 is coupled to the address line ADDL and has no latch function for enabling the second selection signal SE2 to select the second word line WLL in the second memory cell array 104.

The second selection circuit 24 includes a second decode logic 242 and a second word line driver 244. The second decoding logic 242 is coupled to the address line ADDL for enabling the second driving signal DS2 in response to the second address signal, and is responsive to other address signals (eg, the first address signal) on the address line ADDL. The second drive signal DS2.

The second word line driver 244 is coupled to the second decoding logic 242. The second word line driver 244 can enable the second selection signal SE2 to select the second word line WLL when the second driving signal DS2 is enabled, and disable the second driving signal DS2 when the second driving signal DS2 is disabled. The second selection signal SE2 is used to deselect the second word line WLL.

FIG. 3 is a circuit diagram of a decoder 20 in accordance with an embodiment of the present disclosure.

As shown in FIG. 3, the first word line driver 224 mainly includes inverters IN0 to IN2 and transistors M1 to M3. The transistors M1 to M3 may be N-type metal oxide semiconductor field effect transistors (NMOS). Control terminals (e.g., gates) of transistors M1 and M2 are coupled to the output of inverter IN0 and the output of first decoding logic 222, respectively. The input end and the output end of the inverter IN1 are respectively coupled to the output end and the input end of the inverter IN2 to form a latch circuit 2242. The latch circuit 2242 is coupled between the first end of the transistor M1 (such as a drain) and the first end of the transistor M2 (such as a drain). The latch circuit is further coupled to the first word line WLR to apply the first selection signal SE1 thereto.

The second ends (such as the source) of the transistors M1 and M2 are connected to each other and coupled to the transistor M3. The transistor M3 is controlled by the latch control signal ENB. When the latch control signal ENB is enabled, the state of the first selection signal SE1 (eg, enable/disable) will follow the state of the first drive signal DS1. When the latch control signal ENB is disabled, the state of the first selection signal SE1 will be latched and does not change with the first drive signal DS1.

The second word line driver 244 includes an inverter IN3 and transistors M4 to M7. The transistors M4 and M5 are, for example, NMOS, and the transistors M6 and M7 are, for example, P-type metal oxide semiconductor field effect transistors (PMOS). As shown in Fig. 3, the transistors M4 to M7 are arranged as a level shifter.

It should be noted that the circuit structure of the column decoder 20 is not limited to the above examples. For example, the first word line driver 224 in the column decoder 20 can be implemented by combining a latch circuit with a known word line driver structure. The second word line driver 244 can then be implemented based on various levels of shifters.

FIG. 4 is a diagram showing related signal waveforms of the decoder 20 according to an embodiment of the present disclosure.

Please also refer to Figures 2 and 4. In the time interval t0~t2, the address signal ADD on the address line ADDL is the first address signal ADD1. At time t2, the first address signal 1 is changed to the second address signal ADD2. The first address signal ADD1 matches the first selection circuit 22. The second address signal ADD2 matches the second selection circuit 24. Therefore, the first driving signal DS1 provided by the first decoding logic 222 in the first selection circuit 22 is enabled in the time interval t0~t2, and becomes disabled after the time point t2. Conversely, the second driving signal DS2 provided by the second decoding logic 242 in the second selection circuit 24 is disabled in the time interval t0~t2, and becomes enabled after the time point t2.

When the second driving signal DS2 is disabled, the second word line driver 244 disables the second selection signal SE2 to deselect the second word line WLL. Conversely, when the second drive signal DS2 is enabled, the second word line driver 244 will enable the second selection signal SE2 to select the second word line WLL.

In the time interval t0~t1, the latching control signal ENB is enabled. During this period, the first word line driver 224 enables the first selection signal SE1 when the first driving signal DS1 is enabled.

In this example, the pulse period (t0~t1) of the enable pulse signal ENB is shorter than the pulse period (t0~t2) of the first drive signal DS1.

In the time interval t1~t3, the latch control signal ENB is disabled. During this period, regardless of whether the first drive signal DS1 is enabled or disabled, the first word line driver 224 latches the enabled first selection signal SE1 to maintain the first word line WLR selected.

At time t2, the first address signal ADD1 on the address line ADDL is switched to match the second address signal ADD2 of the second selection circuit 24. At the same time, the first selection signal SE1 is still latched in the enabled state.

At time t3, the latch control signal ENB is switched back to enable. At this time, the latch circuit 2242 will respond to the first disable signal DS1 that is disabled, and disable the first select signal SE1 to deselect the first word line WLR.

In summary, the present disclosure provides a column decoder and a memory system using the same. The column decoder may include one or more selection circuit sets to select word lines in the first memory cell array and the second memory cell array in the memory device. Each of the selection circuit groups includes a first selection circuit and a second selection circuit. The first selection circuit includes a first word line driver having a latching function. The second selection circuit includes a second word line driver that does not have a latch function. The address control logic can sequentially provide the address signals to a set of address lines to simultaneously operate the first and second memory cell arrays, such as a read-in-read or a read-in-write operation. . Through the column decoder proposed in the disclosure, the first selection circuit and the second selection circuit in one selection circuit group can share the same group address line, so that the address line and the required circuit area can be effectively saved.

Although the present invention has been disclosed above by way of example, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧ memory system
102‧‧‧ memory cell array
104‧‧‧Second memory cell array
106‧‧‧ Address Conversion Logic
108, 20‧‧‧ column decoder
11082_1~1082_m, 1084_1~1084_m‧‧‧Selection circuit
WLR_1~WLR_m, WLL_1~WLL_m‧‧‧ character line
ADDL‧‧‧ address line
12‧‧‧Host device
22‧‧‧First selection circuit
24‧‧‧Second selection circuit
WLR‧‧‧first character line
WLL‧‧‧second character line
222‧‧‧First decoding logic
242‧‧‧Second decoding logic
224‧‧‧first word line driver
244‧‧‧Second word line driver
DS1‧‧‧ first drive signal
DS2‧‧‧second drive signal
SE1‧‧‧ first choice signal
SE2‧‧‧ second choice signal
2242‧‧‧Latch circuit
IN0~IN3‧‧‧ reverser
M1~M7‧‧‧O crystal
ENB‧‧‧Latch control signal
ADD‧‧‧ address signal
ADD1‧‧‧ first address signal
ADD2‧‧‧ second address signal
T0, t1, t2, t3‧‧‧ time points

FIG. 1 is a block diagram of a memory system in accordance with an embodiment of the present disclosure. FIG. 2 is a block diagram of a column decoder according to an embodiment of the present disclosure. FIG. 3 is a circuit diagram of a decoder according to an embodiment of the present disclosure. FIG. 4 is a diagram showing waveforms of related signals of a decoder according to an embodiment of the present disclosure.

Claims (15)

A column decoder includes: a plurality of address lines; a first selection circuit coupled to the address lines and having a latch function for enabling and latching a first selection signal to select a first word line in the first memory cell array; and a second selection circuit coupled to the address lines and having the latching function to enable a second selection signal to select a second A second word line in the memory cell array. The decoder according to claim 1, wherein the first selection circuit comprises: a first decoding logic coupled to the address lines for responding to a first address on the address lines The signal enables a first driving signal, and a second address signal on the address lines is disabled to disable the first driving signal; and a first word line driver coupled to the first decoding logic, the first The word line driver includes: a latching circuit controlled by a latching control signal, wherein the latching circuit is configured to enable the first driving signal during the period in which the latching control signal is enabled The first selection signal is enabled, and the first selection signal is latched during the period when the latch control signal is disabled. The decoder of claim 2, wherein the period during which the latch control signal is enabled overlaps with the period during which the first drive signal is enabled. The decoder according to claim 2, wherein the first address signal provided on the address lines is switched to the second address signal while the latch control signal is disabled . The decoder of claim 2, wherein the latching circuit disables the first selection signal when the first driving signal is disabled while the latching control signal is enabled. The decoder according to claim 1, wherein the second selection circuit comprises: a second decoding logic coupled to the address lines for responding to a second address on the address lines The signal enables a second driving signal, and a first address signal on the address lines is disabled to disable the second driving signal; and a second word line driver is coupled to the second decoding logic for When the second driving signal is enabled, the second selection signal is enabled to select the second character line, and when the second driving signal is disabled, the second selection signal is disabled to deselect the second driving signal. The second word line. The decoder according to claim 6, wherein the first address signal and the second address signal are sequentially provided to the address lines. The decoder according to claim 1, wherein the column decoder is coupled between the first memory cell array and the second memory cell array. A memory system includes: a first memory cell array including a first word line; a second memory cell array including a second word line; and address conversion logic for providing access to the first a plurality of address signals of the memory cell array and the second memory cell array, the address signals include a first address signal and a second address signal; and a column decoder coupled to the first memory cell array And the second memory cell array, the column decoder includes: a plurality of address lines coupled to the address conversion logic for sequentially receiving the address signals from the address conversion logic; a circuit, coupled to the address lines and having a latch function for responding to the first address signal enable and latching a first select signal to select the first word line; The second selection circuit, coupled to the address lines, does not have the latching function, and is configured to respond to the second address signal to enable a second selection signal to select the second word line. The memory system of claim 9, wherein the first selection circuit comprises: a first decoding logic coupled to the address lines for responding to the first address signal enabling Driving the signal, and returning the second address signal to disable the first driving signal; and a first word line driver coupled to the first decoding logic, the first word line driver comprising: a latch circuit, Controlled by a latching control signal, the latching circuit is configured to enable the first selection signal when the first driving signal is enabled during the period in which the latching control signal is enabled, and to enable the first selection signal The first selection signal is latched during the period when the lock control signal is disabled. The memory system of claim 10, wherein the period during which the latching control signal is enabled overlaps with the period during which the first driving signal is enabled. The memory system of claim 10, wherein the first address signal provided on the address lines is switched to the second address signal while the latch control signal is disabled . The memory system of claim 10, wherein the latching circuit disables the first selection signal when the first driving signal is disabled while the latching control signal is enabled. The memory system of claim 9, wherein the second selection circuit comprises: a second decoding logic coupled to the address lines for responding to the second address signal enabling a second Driving the signal, and returning the first address signal to disable the second driving signal; and a second word line driver coupled to the second decoding logic for enabling the second driving signal when The second selection signal can be selected to select the second word line, and when the second driving signal is disabled, the second selection signal is disabled to deselect the second word line. The memory system of claim 9, wherein the column decoder is coupled between the first memory cell array and the second memory cell array.