TWI629684B - Column decoder of memory device - Google Patents

Abstract

A row decoder of a memory device includes a first selection circuit, a second selection circuit, and a decoding circuit. The first selection circuit, the second selection circuit, and the memory array in the memory device are stacked one on another. The decoding circuit receives a row address including a first subaddress and a second subaddress. The decoding circuit generates first decoded data and second decoded data for controlling the first selection circuit and the second selection circuit based on the first sub-address and the second sub-address. A first decoder in the decoding circuit decodes the first sub-address into a first decoded material, and the first decoded data is inverted in response to a change in the first preset bit in the second sub-address.

Description

Row decoder of memory device

The present invention relates to a decoding technique for a memory device, and more particularly to a row decoder for a memory device.

Generally, the memory device can select a memory cell in the memory array through a row decoder and a column decoder to perform a read operation, a verification operation, or a program operation on the selected memory cell. In addition, during a read operation, a verify operation, or a program operation, the control logic in the memory device continuously accumulates the row address of the memory cell to correspond to the preset block in the memory array. Operation.

The existing row decoder can decode the row address into the first to third decoded data to respectively control the first to third selection circuits therein. In addition, in the process of processing consecutive accumulated row addresses, the decoded data decoded by the existing row decoder tends to have multiple simultaneous transitions. For example, in the case of the existing row decoder, when the row address is accumulated from {000000} one by one to {111111}, the number of times the first to third decoded data are simultaneously transitioned is 4, and the first The number of simultaneous transitions of the two decoded data in the third decoded data is 12. However, when the state of the decoded material is simultaneously changed, it means that the more switches in the first to third selection circuits are simultaneously switched. Therefore, the more times the decoded data occurs at the same time, the more power switching loss will be caused, thereby increasing the power consumption of the row decoder and reducing the decoding speed of the row decoder. What's more, it may also make the decoded data unable to complete the transition within the agreed time, which will cause the row decoder to fail, which will reduce the reliability of the row decoder.

The present invention provides a row decoder of a memory device, wherein a first decoder in the decoding circuit can decode the first sub-address into the first decoded data according to the first preset bit in the second sub-address. Thereby, the power consumption of the row decoder can be reduced and the decoding speed and reliability of the row decoder can be increased.

The row decoder of the memory device of the present invention includes a first selection circuit, a second selection circuit and a decoding circuit, and the decoding circuit includes a first decoder. The first selection circuit, the second selection circuit, and the memory array in the memory device are stacked one on another. The decoding circuit is electrically connected to the first selection circuit and the second selection circuit, and receives a row address including the first sub-address and the second sub-address. The decoding circuit generates a first decoded data for controlling the first selection circuit based on the first sub-address, and generates second decoded data for controlling the second selection circuit based on the second sub-address. The first decoder decodes the first sub-address into the first decoded data, and the first decoded data is inverted in response to the change of the first preset bit in the second sub-address.

In an embodiment of the invention, the row decoder of the memory device further includes a third selection circuit. The third selection circuit is electrically connected to the decoding circuit and electrically connected to the first selection circuit by the second selection circuit. The row address further includes a third sub-address, and the first preset bit is the least significant bit of the second sub-address. The decoding circuit further generates third decoded data for controlling the third selection circuit based on the third sub-address. The decoding circuit further includes a second decoder and a third decoder. The second decoder decodes the second sub-address into the second decoded material. The third decoder decodes the third sub-address into a third decoded material.

Based on the above, the decoding circuit in the row decoder of the present invention can receive the row address including the first subaddress and the second subaddress. Furthermore, the first decoder in the decoding circuit can decode the first sub-address into the first decoded data, and the first decoded data is inverted in response to the change of the first preset bit in the second sub-address. . Thereby, the power consumption of the row decoder can be reduced and the decoding speed and reliability of the row decoder can be increased.

The above described features and advantages of the invention will be apparent from the following description.

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention. As shown in FIG. 1, the memory device 100 includes a memory array 110 and a row decoder 120, and the row decoder 120 includes a decoding circuit 130 and first to third selection circuits 141 to 143. The first to third selection circuits 141 to 143 and the memory array 110 are stacked one on another and have a hierarchical structure. In addition, the first selection circuit 141 includes N ² selectors (eg, selectors 151 15 15N, 16 16 16 N), and each of the N ² selectors is electrically connected to N area bit lines ( Local bit line). The second selection circuit 142 includes N selectors 171~17N, and each of the selectors 171~17N is electrically connected to the first selection circuit 141 through N global bit lines. The third selection circuit 143 includes a selector 180. In addition, the selector 180 is electrically connected to the data line DL1 and electrically connected to the second selection circuit 142 through the N local data lines. Furthermore, each of the first to third selection circuits 141 to 143 includes N switches. Where N is a positive integer and the number of switches can be selected according to the selected decoding relationship.

The decoding circuit 130 is electrically connected to the first to third selection circuits 141 to 143 and receives The row address of the bit is A[3K-1:0], where N=2 ^K and K is a positive integer. The decoding circuit 130 decodes the row address A[3K-1:0] into first to third decoded data X[N-1:0], Y[N-1:0], and Z[, respectively, having N bits. N-1:0] to control the first to third selection circuits 141 to 143, respectively. For example, each selector in the first selection circuit 141 is controlled by the first decoded material X[N-1:0]. Each of the second selection circuits 142 is controlled by the second decoded material Y[N-1:0]. The selector 180 in the third selection circuit 143 is controlled by the third decoded material Z[N-1:0].

Under the control of the decoding circuit 130, the first to third selection circuits 141 to 143 may select one of the connected N ³ area bit lines and turn on the selected area bit line to the data line DL1. In addition, the memory device 100 can conduct the data line DL1 to the sense amplifier 102 or the voltage generator 103 in response to the switching of the selection switch 101. Thereby, through the switching of the selection switch 101, the selected region bit line can be further turned on to the sense amplifier 102 or the voltage generator 103, thereby causing the memory device 100 to make a preset to the memory array 110. Operations (for example: read operations, verify operations, or stylized operations).

For example, when the selected area bit line is turned on to the voltage generator 103 through the selection switch 101, the selected area bit line can be maintained at a high voltage level, thereby causing the memory device 100 to be compatible with the memory. The array 110 performs a programmatic operation. On the other hand, when the selected region bit line is turned on to the sense amplifier 102 through the selection switch 101, the sense amplifier 102 can compare the voltage from the selected bit line to the reference voltage VR1, thereby causing the memory. The body device 100 can perform a read operation or a verify operation on the memory array 110.

2 is a partial schematic diagram of a row decoder in accordance with an embodiment of the present invention, and for convenience of explanation, the embodiment of FIG. 2 illustrates the operation of the row decoder in a state of K=2 and N=4. As shown in FIG. 2, the decoding circuit 130 includes a first decoder 211, a second decoder 212, and a third decoder 213. Each of the first selection circuits 141 (for example, the selectors 151 to 154) includes four switches 221 to 224. Each of the second selection circuits 142 (e.g., selector 171) includes four switches 231-234. The selector 180 in the third selection circuit 143 includes four switches, of which FIG. 2 only shows the switch 241 in the selector 180.

The row address A[5:0] received by the decoding circuit 130 includes a first sub-address A[1:0], a second sub-address A[3:2], and a third sub-address A[5:4 ]. Furthermore, the decoding circuit 130 generates a first decoded data X[3:0] for controlling the first selection circuit 141 based on the first sub-address A[1:0], and based on the second sub-address A[3:2 Generating a second decoded data Y[3:0] for controlling the second selection circuit 142, and generating a third decoded data Z for controlling the third selection circuit 143 based on the third sub-address A[5:4] [3:0].

Specifically, the first decoder 211 inverts the first decoded material X[3:0] in response to the change of the first preset bit A2 in the second sub-address A[3:2]. The first preset bit A2 is the least significant bit (Least Significant Bit) of the second sub-address A[3:2]. The second decoder 212 decodes the second sub-address A[3:2] into the second decoded material Y[3:0]. The third decoder 213 decodes the third sub-address A[5:4] into the third decoded material Z[3:0].

For example, FIG. 3 is a truth table of a decoding circuit in accordance with an embodiment of the present invention. As shown in FIG. 3, the bit values of the row address A[5:0] are accumulated one by one from {000000} to {111111}. Since the first decoder 211 is controlled by the first preset bit A2, the first decoder 211 can decode different first decoded data X[3 for the same first sub-address A[1:0]: 0]. For example, in the period T31, that is, when the first preset bit A2 is {0}, and the first sub-address A[1:0] is accumulated from {00} one by one to {11}, The first decoded data X[3:0] decoded by the first decoder 211 are {0001}, {0010}, {0100}, and {1000}, respectively. In the period T41, that is, when the first preset bit A2 is {1}, and the first sub-address A[1:0] is accumulated from {00} one by one to {11}, the first decoder The first decoded data X[3:0] decoded by 211 are {1000}, {0100}, {0010}, and {0001}, respectively.

In other words, the first decoded material X[3:0] may be inverted in response to a change in the state of the first preset bit A2. Therefore, the first decoder 211 in the period T41 corresponds to the bit order in which the first decoded material X[3:0] is inverted, compared to the first decoded material X[3:0] in the period T31. By analogy, in the period T32~T38, the first preset bit A2 is {0}, and the first decoded data X[3:0] are {0001}, {0010}, {0100} and {1000 respectively. }. In the period T42~T48, the first preset bit A2 is {1}, and the first decoder 211 inverts the first decoded data X[3:0], thereby causing the first decoded data X[3:0 ] are {1000}, {0100}, {0010}, and {0001}, respectively.

It is worth noting that in the process of row address A[5:0] being accumulated from {000000} one by one to {111111}, the first to third decoded data X[3:0], Y[3:0] and Z[3:0] does not generate the transition state at the same time, and the second and third decoded data Y[3:0] and Z[3:0] only generate the transition state at the transition point P30~P33, respectively. For example, when the row address A[5:0] transitions from {001111} to {010000}, that is, at the transition point P31, two of the second decoded data Y[3:0] The states of the elements Y3 and Y0 are changed, and the states of the two bits Z1 and Z0 in the third decoded material Z[3:0] are changed. At this time, each of the second selection circuits 142 (for example, the selector 171) will simultaneously switch the state of the two switches 234 and 231 in its interior in response to the transition of the bits Y3 and Y0. Further, the selector 180 in the third selection circuit 143 also switches the states of the two switches therein.

In other words, in the process of accumulating the row address A[5:0] from {000000} one by one to {111111}, the first to third decoded data simultaneously generate the number of transitions of 0, and the first to third decoded data The number of transitions in the two decoded data at the same time is 4. Therefore, the row decoder 120 in the embodiment of FIG. 2 can avoid the simultaneous transition of the first to third decoded data, and can reduce two of the first to third decoded data, compared to the existing row decoder. The probability of a transition is also present in the decoded data. As a result, the number of switches in the first to third selection circuits 141 to 143 that are simultaneously switched can be greatly reduced, thereby reducing the switching loss of the first to third selection circuits 141 to 143, thereby facilitating The power consumption of the row decoder 120 is reduced and helps to increase the decoding speed of the row decoder 120. In addition, the failure of the row decoder 120 can also be avoided, thereby helping to increase the reliability of the row decoder 120.

4 is a schematic diagram of a first decoder in accordance with an embodiment of the present invention. As shown in FIG. 4, the first decoder 211 includes first and second inverters 411 and 412, first to fourth multiplexers 421 to 424, and first to fourth NAND gates 431 to 434. The first inverter 411 receives the first bit A0 of the first sub-address A[1:0]. The first and second multiplexers 421 and 422 receive the output bits of the first bit A0 and the first inverter 411, respectively. The second inverter 412 receives the second bit A1 of the first sub-address A[1:0]. The third and fourth multiplexers 423 and 424 receive the output bits of the second bit A1 and the second inverter 412, respectively.

The first to fourth multiplexers 421 to 424 are respectively controlled by the first preset bit A2. Thereby, the output bits of the first and second multiplexers 421 and 422 will be mutually inverted, and the output bits of the third and fourth multiplexers 423 and 424 will be inverted from each other. The first AND gate 431 is electrically connected to the outputs of the first and third multiplexers 421 and 423, and generates a bit X0 in the first decoded data X[3:0]. The second AND gate 432 is electrically coupled to the outputs of the second and third multiplexers 422 and 423 and generates a bit X1 in the first decoded data X[3:0]. The third AND gate 433 is electrically connected to the outputs of the first and fourth multiplexers 421 and 424, and generates the bit X2 in the first decoded data X[3:0]. The fourth sum gate 434 is electrically coupled to the outputs of the second and fourth multiplexers 422 and 424 and generates a bit X3 in the first decoded data X[3:0].

FIG. 5 is a diagram showing a truth table of the first decoder according to an embodiment of the present invention, and B0 and B1 in the truth table of FIG. 5 are outputs of the second and fourth multiplexers 422 and 424, respectively. Bit. Referring to FIG. 4 and FIG. 5 simultaneously, the first to fourth multiplexers 421 to 424 are interspersed between the first sub-address A[1:0] and the first to fourth and gates 431-434. In addition, the first to fourth multiplexers 421 424 424 can adjust their output bits in response to the first preset bit A2, and the first to fourth NAND gates 431 434 434 can respond to the first to fourth multiplexes The output bits of the tools 421~424 generate the first decoded data X[3:0]. Thereby, the first preset bit A2 will correspond to the inverted information of the first decoder 211. For example, when the first preset bit A2 is {0}, and the first sub-address A[1:0] is {00}, {01}, {10}, and {11}, respectively, the first The decoded data X[3:0] will be {0001}, {0010}, {0100} and {1000}, respectively. On the other hand, when the first preset bit A2 is {1}, and the first sub-address A[1:0] is {00}, {01}, {10}, and {11}, respectively, the first The decoded data X[3:0] will be {1000}, {0100}, {0010} and {0001}, respectively.

6 is a schematic diagram of a first decoder in accordance with another embodiment of the present invention. As shown in FIG. 6, the first decoder 211 includes first and second anti-mutation gates 611 and 612, first and second inverters 621 and 622, and first to fourth gates 631 to 634. The first anti-mutation or gate 611 receives the first bit A0 and the first preset bit A2 of the first sub-address A[1:0]. The second anti-mutation or gate 612 receives the second bit A1 and the first preset bit A2 of the first sub-address A[1:0].

The first inverter 621 is electrically connected to the output of the first anti-mutation or gate 611. The second inverter 622 is electrically connected to the output of the second anti-mutation or gate 612. The first AND gate 631 is electrically connected to the output of the first anti-mutation gate 611 and the output of the second anti-mutation gate 612. The second AND gate 632 is electrically connected to the output end of the second anti-mutation gate 612 and the output end of the first inverter 621. The third sum gate 633 is electrically connected to the output end of the first anti-mutation gate 611 and the output end of the second inverter 622. The fourth sum gate 634 is electrically connected to the output end of the first inverter 621 and the output end of the second inverter 622. In addition, the first to fourth gates 631-634 generate the first decoded data X[3:0].

FIG. 7 is a diagram showing a truth table of a first decoder according to another embodiment of the present invention, and C0 and C1 in the truth table of FIG. 7 are first and second exclusive mutex or gate 611, respectively. Output bit of 612. Referring to FIG. 6 and FIG. 7 simultaneously, under the control of the first preset bit A2, the first and second anti-mutation gates 611 and 612 can directly output the first sub-address A[1:0] or The inverted signal of the first sub-address A[1:0] is generated. Thereby, the first preset bit A2 will correspond to the inverted information of the first decoder 211. For example, when the first preset bit A2 is {0} and the first sub-address A[1:0] is {00}, {01}, {10}, and {11}, respectively, the first decoded data X[3:0] will be {0001}, {0010}, {0100}, and {1000}, respectively. On the other hand, when the first preset bit A2 is {1}, and the first sub-address A[1:0] is {00}, {01}, {10}, and {11}, respectively, the first The decoded data X[3:0] will be {1000}, {0100}, {0010} and {0001}, respectively.

FIG. 8 is a partial schematic diagram of a row decoder in accordance with another embodiment of the present invention. The second decoder 810 in the decoding circuit 130 of FIG. 8 is different from the second decoder 212 in FIG. 2 in comparison to the FIG. 2 embodiment. Specifically, the second decoder 810 inverts the second decoded material Y[3:0] in response to the change of the second preset bit A4 in the third sub-address A[5:4]. In addition, the second preset bit A4 is the least significant bit of the third sub-address A[5:4].

For example, Figure 9 is a truth table of a decoding circuit in accordance with another embodiment of the present invention. As shown in FIG. 9, the bit values of the row address A[5:0] are cumulatively added from {000000} to {111111}. Since the second decoder 810 is controlled by the second preset bit A4, the second decoder 810 can decode different second decoded data Y[3 for the same second sub-address A[3:2]: 0]. For example, in the periods T91 and T93, that is, when the second preset bit A4 is {0}, and the second sub-address A[3:2] is {00}, {01}, {10, respectively } and {11}, the second decoded data Y[3:0] decoded by the second decoder 810 are {0001}, {0010}, {0100}, and {1000}, respectively. On the other hand, in the periods T92 and T94, that is, when the second preset bit A4 is {1}, and the second sub-address A[3:2] is {00}, {01}, {10, respectively } and {11}, the second decoded data Y[3:0] decoded by the second decoder 810 are {1000}, {0100}, {0010}, and {0001}, respectively.

In other words, compared to the second decoded material Y[3:0] in the periods T91 and T93, the second decoder 810 in the periods T92 and T94 corresponds to the second decoded data Y[3:0] inverted. Bit order. In addition, similar to the embodiment of FIG. 2, in the period T91~T94, the first decoder 211 can decide whether to invert the first decoded data X[3:0] according to the first preset bit A2. In this way, in the process of accumulating the row address A[5:0] from {000000} one by one to {111111}, that is, in the period T91~T94, the first to third decoded data X[3:0] Any two decoded data in Y[3:0] and Z[3:0] will not simultaneously produce a transition state.

In this way, in the embodiment of FIG. 8, in the process of accumulating the row address A[5:0] from {000000} one by one to {111111}, the number of transitions of the first to third decoded data simultaneously is 0, and the number of times the two decoded data in the first to third decoded data simultaneously generate the transition state is also zero. In other words, when one of the first to third decoded data produces a transition, the remaining two decoded data will remain unchanged. Thereby, the power consumption of the row decoder 120 can be reduced and the decoding speed and reliability of the row decoder 120 can be increased. The detailed configuration and operation of the remaining components in the embodiment of FIG. 8 are included in the above embodiments, and thus will not be described herein.

10 is a schematic diagram of a second decoder in accordance with an embodiment of the present invention. As shown in FIG. 10, the second decoder 810 includes first and second inverters 1011 and 1012, first to fourth multiplexers 1021 to 1024, and first to fourth gates 1031 to 1034. The first inverter 1011 receives the first bit A2 (ie, the least significant bit) in the second sub-address A[3:2]. The first and second multiplexers 1021 and 1022 receive the output bits of the first bit A2 and the first inverter 1011, respectively. The second inverter 1012 receives the second bit A3 of the second sub-address A[3:2]. The third and fourth multiplexers 1023 and 1024 receive the output bits of the second bit A3 and the second inverter 1012, respectively.

The first to fourth multiplexers 1021 to 1024 are respectively controlled by the second preset bit A4. Thereby, the output bits of the first and second multiplexers 1021 and 1022 will be mutually inverted, and the output bits of the third and fourth multiplexers 1023 and 1024 will be inverted from each other. The first sum gate 1031 is electrically connected to the output ends of the first and third multiplexers 1021 and 1023. The second AND gate 1032 is electrically connected to the outputs of the second and third multiplexers 1022 and 1023. The third sum gate 1033 is electrically connected to the outputs of the first and fourth multiplexers 1021 and 1024. The fourth sum gate 1034 is electrically connected to the outputs of the second and fourth multiplexers 1022 and 1024. The first to fourth gates 1031 to 1034 generate second decoded data Y[3:0]. In addition, the operation of the second decoder of FIG. 10 is similar to the first decoder in the embodiment of FIG. 4, and thus will not be described herein.

11 is a schematic diagram of a second decoder in accordance with another embodiment of the present invention. As shown in FIG. 11, the second decoder 810 includes first and second anti-mutation gates 1111 and 1112, first and second inverters 1121 and 1122, and first to fourth gates 1131 to 1134. The first anti-mutual repulsion gate 1111 receives the first bit A2 (ie, the least significant bit) of the second sub-address A[3:2] and the second preset bit A4. The second anti-mutation or gate 1112 receives the second bit A3 and the second preset bit A4 of the second sub-address A[3:2]. The first inverter 1121 is electrically connected to the output end of the first anti-mutation gate 1111. The second inverter 1122 is electrically connected to the output of the second anti-mutation or gate 1112.

The first AND gate 1131 is electrically connected to the output end of the first anti-mutation gate 1111 and the output end of the second anti-mutation gate 1112. The second AND gate 1132 is electrically connected to the output end of the second anti-mutation gate 1112 and the output end of the first inverter 1121. The third sum gate 1133 is electrically connected to the output end of the first anti-mutation gate 1111 and the output end of the second inverter 1122. The fourth sum gate 1134 is electrically connected to the output end of the first inverter 1121 and the output end of the second inverter 1122. The first to fourth gates 1131 to 1134 generate second decoded data Y[3:0]. In addition, the operation of the second decoder of FIG. 11 is similar to the first decoder in the embodiment of FIG. 6, and therefore will not be described herein.

In summary, the decoding circuit in the row decoder of the present invention can receive a row address including M sub-addresses, and the i-1th decoded data generated by the i-1th decoder in the decoding circuit is based on The i-1th subaddress is further inverted in response to a change in a preset bit (e.g., least significant bit) in the i th subaddress. That is, in response to the change of the preset bit in the i-th sub-address, the i-1th decoder in the decoding circuit outputs the inverted i-1th decoded material. Where i is a positive integer greater than 1 and less than or equal to M. Thereby, the power consumption of the row decoder can be reduced and the decoding speed and reliability of the row decoder can be increased.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory device

110‧‧‧Memory array

120‧‧‧ line decoder

130‧‧‧Decoding circuit

141~143‧‧‧first to third selection circuits

151~15N, 161~16N, 171~17N, 180‧‧‧ selector

101‧‧‧Selection switch

102‧‧‧Sense Amplifier

103‧‧‧Voltage generator

DL1‧‧‧ data line

VR1‧‧‧ reference voltage

A[3K-1:0], A[5:0]‧‧‧ addresses

X[N-1:0], X[3:0]‧‧‧ first decoding data

Y[N-1:0], Y[3:0]‧‧‧ second decoding data

Z[N-1:0], Z[3:0]‧‧‧ third decoding data

211‧‧‧First decoder

212, 810‧‧‧ second decoder

213‧‧‧ third decoder

221~224, 231~234, 241‧‧ ‧ switch

A[1:0]‧‧‧ first subaddress

A[3:2]‧‧‧ second sub-address

A[5:4]‧‧‧ third sub-address

X0~X3, Y0~Y3, Z0~Z3, A0~A5‧‧‧ bits

During T31~T38, T41~T48, T91~T94‧‧

P30~P33‧‧‧Transition point

411, 621, 1011, 1121‧‧‧ first inverter

412, 622, 1012, 1122‧‧‧ second inverter

421, 1021‧‧‧ first multiplexer

422, 1022‧‧‧ second multiplexer

423, 1023‧‧‧ third multiplexer

424, 1024‧‧‧ fourth multiplexer

431, 631, 1031, 1131‧‧‧ first gate

432, 632, 1032, 1132‧‧‧ second gate

433, 633, 1033, 1133‧‧‧ third gate

434, 634, 1034, 1134‧‧‧ fourth and gate

B0‧‧‧ output multiplexer of the second multiplexer

Output bit of B1‧‧‧ fourth multiplexer

611, 1111‧‧‧ first anti-mutation or gate

612, 1112‧‧‧ second anti-mutation or gate

C0‧‧‧ output bin of the first anti-mutation or gate

C1‧‧‧2nd anti-mutual or gate output bit

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention. 2 is a partial schematic diagram of a row decoder in accordance with an embodiment of the present invention. 3 is a truth table of a decoding circuit in accordance with an embodiment of the present invention. 4 is a schematic diagram of a first decoder in accordance with an embodiment of the present invention. FIG. 5 is a table of truth values for illustrating a first decoder in accordance with an embodiment of the present invention. 6 is a schematic diagram of a first decoder in accordance with another embodiment of the present invention. FIG. 7 is a diagram showing a truth table of a first decoder in accordance with another embodiment of the present invention. FIG. 8 is a partial schematic diagram of a row decoder in accordance with another embodiment of the present invention. 9 is a truth table of a decoding circuit in accordance with another embodiment of the present invention. 10 is a schematic diagram of a second decoder in accordance with an embodiment of the present invention. 11 is a schematic diagram of a second decoder in accordance with another embodiment of the present invention.

Claims (11)

A row decoder of a memory device, comprising: a first selection circuit and a second selection circuit, and a memory array in the memory device are stacked in series; and a decoding circuit electrically connecting the first selection a circuit and the second selection circuit, and receiving a row address including a first sub-address and a second sub-address, the decoding circuit generating a first one for controlling the first selection circuit based on the first sub-address Decoding data, and generating a second decoded data for controlling the second selection circuit based on the second sub-address, and the decoding circuit comprises: a first decoder, decoding the first sub-address into the First decoding data, and the first decoded data is inverted in response to a change of a first preset bit in the second sub-address. The row decoder of the memory device of claim 1, wherein the first preset bit is the least significant bit of the second sub-address. The row decoder of the memory device of claim 2, wherein the first decoder comprises: a first inverter, receiving a first bit in the first sub-address; a second inverter receiving a second bit in the first sub-address; a first multiplexer and a second multiplexer respectively receiving the output of the first bit and the first inverter a bit, and the first multiplexer and the second multiplexer are respectively controlled by the first preset bit, so that the first multiplexer and the output bit of the second multiplexer are mutually Inverted a third multiplexer and a fourth multiplexer respectively receiving the second bit and the output bit of the second inverter, and the third multiplexer and the fourth multiplexer are respectively controlled In the first preset bit, so that the third multiplexer and the output bit of the fourth multiplexer are mutually inverted; a first NAND gate is electrically connected to the first multiplexer and the An output end of the third multiplexer; a second damper electrically connected to the output end of the second multiplexer and the third multiplexer; and a third damper electrically connected to the first multiplexer And an output end of the fourth multiplexer; and a fourth damper electrically connected to the output ends of the second multiplexer and the fourth multiplexer, and the first damper to the fourth damper The first decoded data is generated. The row decoder of the memory device of claim 2, wherein the first decoder comprises: a first anti-mutation or gate, receiving a first bit in the first sub-address and The first preset bit; a second anti-mutation or gate, receiving a second bit in the first sub-address and the first preset bit; a first inverter, electrically connected An output of the first anti-mutation or gate; a second inverter electrically connected to the output of the second anti-mutation or gate; a first gate, electrically connected to the first anti-mutation or An output end of the gate and an output of the second anti-mutation or gate; a second gate is electrically connected to the output end of the second anti-mutation gate and the output end of the first inverter; a third gate is electrically connected to the output of the first anti-mutation or gate And an output terminal of the second inverter; and a fourth gate, electrically connecting the output end of the first inverter and the output end of the second inverter, and the first gate to the first The fourth gate generates the first decoded data. The row decoder of the memory device of claim 2, further comprising a third selection circuit electrically connected to the decoding circuit and electrically connected to the first selection circuit by the second selection circuit, wherein The row address further includes a third sub-address, and the decoding circuit further generates a third decoded data for controlling the third selection circuit based on the third sub-address, the decoding circuit further comprising: a second decoding Decoding the second sub-address into the second decoded data; and a third decoder decoding the third sub-address into the third decoded data. The row decoder of the memory device according to claim 5, wherein the row address has (3×K) bits, and the N ² selectors in the first selection circuit are respectively controlled by the first a decoding data, wherein the N selectors in the second selection circuit are respectively controlled by the second decoding data, a selector of the third selection circuit is controlled by the third decoding data, and the first selection circuit The N ² selectors, the N selectors of the second selection circuit, and the selectors of the third selection circuit respectively include N switches, where N=2 ^K and K is A positive integer. The row decoder of the memory device of claim 6, wherein the N ² selectors in the first selection circuit are electrically connected to the N area bit lines in the memory array, respectively. The selector in the third selection circuit is electrically connected to a selection switch in the memory device through a data line, and the memory device turns on the data line to a sensing in response to the switching of the selection switch. The amplifier is either a voltage generator. The row decoder of the memory device of claim 5, wherein the second decoder decodes the second sub-address into the second decoded data, and the second decoded data is responsive to the The change of a second preset bit in the three subaddresses is reversed. The row decoder of the memory device of claim 8, wherein the second preset bit is the least significant bit of the third subaddress. The row decoder of the memory device of claim 8, wherein the second decoder comprises: a first inverter, receiving a first bit in the second sub-address; a second inverter receiving a second bit of the second sub-address; a first and a second multiplexer respectively receiving the first bit and an output bit of the first inverter, and The first and second multiplexers are respectively controlled by the second preset bit, so that the output bits of the first and second multiplexers are mutually inverted; a third and fourth multiplexer Receiving the second bit and the output bit of the second inverter, respectively, and the third and fourth multiplexers are respectively controlled by the second preset bit to cause the third and fourth The output bits of the multiplexer are inverted with each other; a first gate is electrically connected to the output ends of the first and third multiplexers; a second gate is electrically connected to the output ends of the second and third multiplexers; and a third gate is connected Electrically connecting the output ends of the first and fourth multiplexers; and a fourth damper electrically connecting the outputs of the second and fourth multiplexers, and the first to fourth dampers generate the Second decoded data. The row decoder of the memory device of claim 8, wherein the second decoder comprises: a first anti-mutation or gate, receiving a first bit in the second sub-address and The second preset bit; a second anti-mutation or gate, receiving a second bit in the second sub-address and the second preset bit; a first inverter, electrically connected An output of the first anti-mutation or gate; a second inverter electrically connected to the output of the second anti-mutation or gate; a first gate, electrically connected to the first anti-mutation or An output end of the gate and an output end of the second anti-mutation or gate; a second AND gate electrically connected to the output end of the second anti-mutation or gate and the output end of the first inverter; a third gate, electrically connecting the output end of the first anti-mutation or gate and the output end of the second inverter; and a fourth gate, electrically connecting the output end of the first inverter and the An output of the second inverter, and the first to fourth gates generate the second decoded data.