TWI629683B - Non-volatile memory with overwrite capability and low write amplification - Google Patents

Abstract

The invention provides a non-volatile memory architecture of a storage system with overwrite capability and low write amplification. By way of example, the memory array includes blocks and sub-blocks of two terminal memory units. In some embodiments, the two terminal memory cells can be overwritten directly, which causes the write amplification value to be 1. In addition, the memory array may have an input-output multiplexer configuration to reduce the latent path current in the memory architecture during the memory operation.

Description

Non-volatile memory with overwrite capability and low write amplification [Cross Reference of Related Applications]

The present invention claims priority to US Provisional Patent Application No. 61 / 785,979, filed March 14, 2013, which is incorporated herein by reference.

The invention relates to a non-volatile memory, in particular to a non-volatile memory structure which is convenient for overwriting and low write amplification.

The most recent innovation in integrated circuit technology is resistive switching memory. Although many resistive switching memory technologies are in the development stage, different technical concepts for resistive switching memory have been demonstrated by the patentee of the present invention, and related theories have been proven or refuted in one or more verification stages. Even so, resistive switching memory technology is expected to hold huge advantages in the semiconductor electronics industry's competitive technology.

Resistive random access memory (RRAM) is one of the types of resistive memory. The inventors believe that RRAM has the potential to become a high-density non-volatile information storage technology for higher-density semiconductor-type devices. Generally, RRAM stores information by controllable switching between different resistance states. One theoretical example of an RRAM device includes providing an insulating layer between a pair of electrodes. The device is properly configured to exhibit Electrical pulses induce the effect of hysteresis power bank switching.

Resistive switching is interpreted (in some theories) as a result of forming another electronically insulating medium within the conductive structure. The conductive structure may be formed of ions adjacent to the electrode, for example, with free ions. In some theories, field-assisted diffusion of ions can occur corresponding to a suitable potential or current applied to an RRAM memory cell. According to other theories, filament formation can correspond to Joule heating and electrochemical processes of binary oxides (such as NiO, TiO ₂ or similar), or by ions containing oxides, chalcogenides, polymers, etc. Conductor redox process.

The inventors expect good resistance and life cycle based on electrodes, insulators, electrode models, and resistive devices including those formed from polycrystalline silicon. Furthermore, the inventors anticipate that these devices will have very high on-wafer densities. Accordingly, the resistive element can be a viable substitute for metal-oxide semiconductor (MOS) for digital information storage. The inventors of the main patent application, for example, believe that the resistive switching memory device model provides many potential advantages over non-volatile FLASH MOS devices.

Based on the above, the inventors hope to make further improvements in memory technology and resistive memory.

A brief overview of this specification is presented below to provide a basic understanding of some of the concepts in this specification. This summary is not an exhaustive description of this specification. It neither identifies key or important elements of this specification nor delineates the scope of any particular embodiment in this specification or in any scope of the claims. Its purpose is to present some concepts of the specification in a simplified form as a prelude to the more detailed description of the invention.

Various embodiments disclosed herein provide a method for a memory storage system. Non-volatile memory architecture with low write amplification and overwrite capability. In some disclosed embodiments, the write amplification may be 2 or lower. In at least one embodiment, the write amplification can be as low as one.

In a further embodiment, a non-volatile memory array with high granularity of memory cells with write and overwrite capabilities is provided. A non-volatile memory array can be, for example, a group of memory cells written as small as one word (e.g., two-byte or four-byte, four-word eight-byte, or similar, according to Such as programming operation logic or restrictions). In one embodiment, non-volatile memory can be written into a group of memory cells as small as one byte. In at least one other embodiment, the non-volatile memory can be written into a single memory unit.

Further to the above, different embodiments disclosed include providing a write capability with low write amplification (eg, no write amplification) to a memory storage system. The overwrite capability includes a programming process that directly changes the information of a memory cell stored at one or more addresses without erasing a page or block containing the address memory cell. Directly changing information means a programming process that does not require (or reduce) garbage collection, average erase, memory location mapping, or other processes that do not directly complete overwriting, by converting data from the first memory location to the second memory Location instead of changing or refreshing the information stored in the first memory location. In some embodiments, the write amplification for overwrite can be as low as 1, while in other embodiments, when one or more additional functions related to overwrite (such as garbage collection, average erase, memory When position mapping, etc. is implemented, write amplification can be higher than one. The overwrite ability provides the memory storage system with low write amplification and improves the performance of the corresponding system. This can be done by avoiding the use of copy-corrected data in different locations of memory storage; replacement data is corrected at the original address location. By overwriting the original address location, traditional algorithms such as garbage collection, average erase, memory location mapping, etc., increasing write amplification can be significantly reduced or eliminated.

In other embodiments, non-volatile memory systems have low write amplification. Contains an array of double-ended memory cells. In some embodiments, the dual-ended memory may include resistive memory, such as resistive switching memory technology. In one or more further concepts, the non-volatile memory may include an array of one or more RRAMs.

In still other embodiments, the non-volatile memory system has a low write amplification, sub-20nm resistive cell technology, and can be implemented as a digital storage device. In some concepts, the digital storage device may be removably connected to the host computer device, and may operate as a flash drive in a similar manner in alternative or other concepts. For example, non-volatile memory can be programmatically arranged in a NAND or NOR logic array (although other logic arrays are known or those skilled in the art can be familiar with the context of this disclosure and are considered to be the invention Within range).

In at least one embodiment, the disclosed storage device includes a non-volatile double-ended resistive switching memory. The storage device may be a secondary 20 nanometer technology with write amplification. In at least one embodiment, the storage device may include a plurality of double-ended resistive switching memory arrays stacked in a three-dimensional array. The storage device can be operated at the same time, including overwrite, a large number of memory units (such as pages, blocks, etc.), or a small amount of memory units (such as words, bytes, or a group of bits or even a single bit). Yuan), or both large and small amounts. According to this, the storage device can include special flexibility for the memory process to achieve high writing and erasing performance, and fast, target overwriting or refreshing performance.

In a further embodiment, the disclosed digital storage device may have a cell write speed between about 5 ns and about 5 μs. In still other embodiments, the disclosed digital storage device may have a cell read speed between approximately 30 ns and 1 μs. In alternative or additional concepts, the disclosed storage device may include the ability to erase and overwrite pages, the ability to erase and overwrite words, the ability to erase or overwrite bytes, or the erasure of bits Or overwrite capabilities. In at least one revealed concept, The write amplification of the erase / overwrite capability can be as small as one.

The following description and accompanying drawings detail certain illustrative aspects of the disclosed subject matter. However, these aspects indicate only a few of the various ways in which the principles of the innovation can be used, and the disclosed subject matter is intended to include all such aspects and their equivalents. When considered in conjunction with the drawings, other advantages and novel features of the disclosed subject matter will become apparent from the detailed description of the innovation below.

100‧‧‧Memory Architecture

102‧‧‧bit line

104‧‧‧Word line

106‧‧‧Unit

108‧‧‧ regional word line

110‧‧‧Word line selection

112‧‧‧Source Line

200‧‧‧Memory Architecture

202‧‧‧bit line

204‧‧‧Word line

206‧‧‧Selected columns

Unit 208‧‧‧

210‧‧‧ regional word line

212‧‧‧Word line selection

214‧‧‧Source Line

300‧‧‧Memory device

318‧‧‧RAM

302‧‧‧controller

312‧‧‧ Error Correction Element

314‧‧‧Buffer

316‧‧‧Central Processing Unit

310‧‧‧Host Interface

306‧‧‧Memory Interface

304‧‧‧Memory

308‧‧‧Memory Link / Data Bus

400‧‧‧ Multiplexer

140‧‧‧input / output switch

412‧‧‧ bias signal switch

414‧‧‧input / output contact

416‧‧‧ bias signal

418‧‧‧sensing circuit

500‧‧‧Input / output memory configuration

516A‧‧‧First input / output contact

516B‧‧‧Second input / output contact

516C‧‧‧Y ^th input / output contact

518A‧‧‧Multiplexer

518B‧‧‧Multiplexer

518C‧‧‧Multiplexer

502‧‧‧Sub-block 1

504‧‧‧Sub-block 2

506‧‧‧Sub-block Y

510‧‧‧bit line selected

600‧‧‧Memory (memory) operation

Many concepts or features of the present invention are described with reference to the drawings, wherein similar reference numerals are used to represent the same elements. In this specification, numerous specific details are set forth in order to provide an understanding of the present invention. It should be understood that certain concepts disclosed herein can be implemented without these specific details, or by other methods, components, materials, and the like. In other embodiments, well-known structures and devices are shown in block diagram form in order to facilitate describing the subject matter of the present invention.

FIG. 1 is a schematic diagram of an embodiment of a memory circuit with high element density supporting low write amplification (WA) according to the present invention.

FIG. 2 is a schematic diagram of an embodiment in which the memory circuit in FIG. 1 includes a row of memory selected from a memory operation.

FIG. 3 is a block diagram of an embodiment of an electronic memory system with low read amplification and instant read and write capabilities according to the present invention.

FIG. 4 is a schematic diagram of an embodiment of a multiplexer that promotes an input / output-based memory architecture according to the present invention.

FIG. 5 is a schematic diagram of a circuit embodiment of a memory architecture for an input / output basis of the present invention.

FIG. 6 is a schematic diagram of an embodiment of the invention for writing and overwriting operations of a 3-bit digital information unit Illustration.

FIG. 7 is a flowchart of an embodiment of a method for manufacturing a memory system with low write amplification according to the present invention.

FIG. 8 is a flowchart of an embodiment of a method for manufacturing a digital storage device and further providing a low write amplification memory system according to the present invention.

FIG. 9 is a flowchart of an embodiment of a method for overwriting a subset of a dual-ended digital storage device according to the present invention.

FIG. 10 is a block diagram of an embodiment of an operating environment convenient for implementation of the present invention.

FIG. 11 is a block diagram of a computer environment according to an embodiment of the present invention.

The invention discloses a double-ended memory unit for digital information storage. In some embodiments, the double-ended memory unit may include resistive technology, such as a resistive switching double-ended memory unit. A resistive switching dual-end memory unit (also referred to as a resistive switching memory unit or a resistive switching memory), as used herein, includes two conductive contacts with an active area between the two contacts (here Can also be considered as an electrode or terminal) circuit element. The active area of the double-ended memory device, the resistive switching memory in the text, shows a plurality of stable or semi-stable resistance states, each of which has a unique resistance. In addition, each of the plurality of states may be formed or activated corresponding to a suitable electronic signal applied to the two conductive contacts. A suitable electronic signal may be a voltage value, a current value, a voltage or current polarity or the like, or a suitable combination thereof. An example of a resistive switching double-ended memory device, although not exhaustive, may include resistive random access memory (RRAM).

Embodiments disclosed by this subject matter can provide a filament-based memory unit. An example of a filament-based memory cell may include: a p-type or n-type silicon (Si) layer (such as p-type or n-type polycrystalline silicon, p-type or n-type silicon germanium, etc.), a resistive switching layer ( RSL) and active metal layer Provides filamentous formation ions to the RSL. The p-type or n-type silicon-containing layer may include p-type or n-type polycrystalline silicon, p-type or n-type silicon germanium, or the like. The RSL (can also be regarded as a resistive switching medium (RSM) in the art) may include, for example, an undoped amorphous silicon layer, a semiconductor layer with intrinsic characteristics, a silicon suboxide, and the like. The active metal layer may include, in particular: silver (Ag), gold (Au), titanium (Ti), nickel (Ni), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), and palladium (Pd). Other suitable conductive materials, as well as the compounds and the above-mentioned compositions, can be used in the active metal layer of the present invention to reveal certain concepts. Some details regarding the subject disclosure similar to the foregoing exemplary embodiments can be found in the following US patent applications, the patentees of which have been granted patents to this application: US Patent Application No. 11 /, filed October 19, 2007 875,541 and US Patent Application No. 12 / 575,921, filed October 8, 2009, each of which is incorporated herein by reference in its entirety and for all purposes.

The subject disclosure provides a double-ended memory structure with high element density and low write amplification (WA). In some concepts, double-ended memory may include 20 nanometer (nanometer, nm) technology, but in other concepts, double-ended memory may include sub-20 nanometer technology (eg, 15nm, 10nm, 5nm, and others). Furthermore, the double-ended memory may have an element area smaller than 5F ² . In some concepts, a three-dimensional stack of double-ended memory arrays may be provided to reduce element area. For example, a 4.28F ² device may have an active element area of 2.14F ² for a three-dimensional device with two stacked layers. As another example, a three-dimensional device 4.28F ² having four stacked layers of the device may have an effective element region 1.07F ^2, and so on.

In other embodiments disclosed herein, a digital storage device including double-ended memory is provided. In some embodiments, such a digital storage device may be a removable connection to a computer device (eg, a host computer). In other embodiments, the digital storage device can communicate with a computer Devices (e.g., read-only memory, random access memory, etc.). In a specific embodiment, the digital storage device may be a FLASH device that can be connected to a memory interface on the host computer (eg, a host interface such as USB, or other suitable interfaces; such as FIG. 10 and FIG. 11, below) and Information can be stored and retrieved, and stored information can be erased, corresponding to commands issued by the host device.

The inventor considers the FLASH device as a framework with two unique logics, NAND and NOR architectures, both of which are based on different arrangements of semiconductor transistors. Each logical architecture has different attributes, including their respective advantages and disadvantages. NAND is the most commonly used consumer FLASH driver application, however, mostly due to its memory density and low cost.

NAND FLASH is used for small-scale FLASH devices, USB devices, SD cards, solid state drives (SSDs), storage and memory, and other structural factors. NAND has proven to be a successful technology in driving drives to smaller sizes and higher chip densities over the past decade. However, as the technology scales down the past 72nm memory cell technology, the inventors of the present application believe that some structural and electrical problems become very obvious. For example, bit error rates (BERs) increase significantly, while memory cycles (in terms of memory tolerance) decrease.

In addition to shrinking the size to smaller technical issues, FLASH also has some inherent disadvantages. One limitation of NAND FLASH technology is that one page of memory (such as a memory cell connected to a single global word line in a memory device, such as 4kB) cannot directly modify or rewrite (such as 2MB) without processing the entire block of memory ). Furthermore, multiple block processing involves rewriting pages of memory. As an example, modifying a memory page may involve backing up the block where the memory page is located, erasing the block and writing the backup data, including the modified memory page-back to the block. as As shown in this example, NAND FLASH cannot be updated without erasing first, regardless of the memory granularity (such as block, page, word, byte, bit, etc.).

In order to continue the example of page overwriting, reducing the P / E cycle of the memory block may involve writing backup data to the second block of memory by modifying the memory page, which is different from the block where the page is located. Although this involves writing two blocks to memory, it removes the erase procedure of the first block and reduces the number of overwrite operations involving two blocks (such as erase block, rewrite block) A page-to-block operation of a memory (eg, a write to a second block) as a whole memory operation. In this example, the logical-to-physical (L2P) mapping table is maintained and updated by the memory controller to maintain the new location track of the modified backup data. L2P increases the load on the controller, including memory and programs.

In addition to the above, NAND FLASH generally does not have a high number of program / erase (P / E) cycles before degradation. Therefore, NAND devices often include an average erase combination to reduce P / E cycles for a given block of memory, or to distribute P / E cycles for most or all blocks in memory. The average erase algorithm attempts to equalize the multiple P / E cycles for each NAND device across each memory block. This can be achieved independently from the main operating instructions and file system operations. An effective averaging algorithm attempts to maintain a low P / E cycle difference between the highest and lowest cycle blocks of memory. Although the product life cycle is improved, the average erasure algorithm also increases the calculation and processing load.

In addition to the increased load through the average wipe algorithm and L2P mapping, garbage collection algorithms typically use NAND devices, especially for smaller technology nodes that have lower tolerances for average wipe and garbage collection algorithms. It is necessary to increase the perceived tolerance cycle. Rewriting a page or block of data to another location on the chip leaves the original location of the residual data. After multiple rewrites, whether by host command or average erase, significant number of pages or blocks of memory Remnants can be left behind. Because many NAND FLASH devices cannot overwrite the memory cells by erasing them in advance, the garbage collection algorithm is designed to release these pages or blocks by erasing them so that new data can be written to them.

For NAND FLASH, an overwrite procedure, as well as garbage collection and average erase, often involve multiple P / E cycles. These numbers of P / E cycles are related to the characteristics of memory called write amplification (WA). WA can be regarded as a performance measure of a memory controller, and is generally defined by characteristics of a memory device and a memory controller related to the memory device. More specifically, WA refers to the writing process of some memory controllers to execute a single host write instruction to the memory. The ideal WA is 1, which indicates a single memory controller write process for each host write command. NAND FLASH usually has a WA between 3 and 4, but it reflects the lack of the ability to directly overwrite. Because the reliability and life of the memory are affected by increasing the P / E cycle, the WA of the memory device will directly affect the reliability and performance of the memory device.

Yet another factor that affects storage system performance and load is reducing memory unit retention and correspondingly increasing BER. As mentioned above, as semiconductor transistor technology has a small size, there is a reduction in associated memory retention and an increase in BER. The increased BER places further require the need for error correction code (ECC) for NAND FLASH. For a given memory size (for example, 1 kB), the number of ECC corrections increases, the result of the ECC request increases, and the number of chip transistors related to ECC increases, program cycles, and power consumption. This further exacerbates the problem of combining more powerful digital signal processing algorithms (such as low density parity check codes (LPDC)) with traditional ECC algorithms. These codes can increase the effect of ECC correction, but significantly increase the load and power consumption to the memory storage system All components in. The inventor's opinion disclosed in this subject is that memory devices require more spare memory to accommodate increased ECC requirements, controllers require more transistors, and systems require larger capacity DRAM components.

In addition to memory retention, device life and system load challenge the above discussion. NAND FLASH storage systems have inherently slow page read speeds. The typical read speed of many NAND FLASH is about 25 μs. This potential factor may not be appropriate for newer applications, such as enterprise storage, real-time embedded memory applications, or the like. For example, in these and other memory applications, a 100ns read access time is better. The relatively low read current (for example, less than about 300 nA) of NAND FLASH constitutes a problem for improving the read time of this technology. In addition, the memory architecture of NAND FLASH utilizes inherent challenges to fast random read operations.

NAND FLASH has been the leading technology in portable memory storage devices in recent years. To effectively expand the capacity at the node size, combined with the ability to write and erase quickly, a fairly good life and manufacturing make NAND FLASH the most popular removable access device in the commercial and consumer markets. Although NAND has met the scalability requirements of up to 20X technology, the inventors of this application believe that other technologies will begin to replace traditional gate and operation transistor memory applications, especially in the cell technology below 20nm.

In light of this, the subject disclosure provides a memory array including a memory cell technology in the form of double-ended memory. Examples of double-ended memory technology include resistive memory (eg, resistive switching memory), ferromagnetic memory, phase change memory, magnetoresistive memory, organic memory, conductive bridge memory, and the like. Furthermore, the dual-end memory technology can facilitate writing to or rewriting to the memory location without first erasing the memory block where the memory location is located. In the Lord In some concepts revealed by the question, the disclosed memory device can be written to a memory location without having to erase his own memory location in advance. Accordingly, such a memory device can avoid garbage collection algorithms and related load costs. In addition, these memory devices provide WA values as low as 1, ideal for storage systems.

In other embodiments, the disclosed memory device includes a double-ended memory array with fast read (eg, page read) characteristics. In at least one embodiment, the memory cell reading speed for the disclosed memory device may be approximately 30 ns to 1 μs. Furthermore, the memory device can have a low BER, a high tolerance, and a robust cycle characteristic, alleviating the limitations of the ECC and average erase algorithms, and reducing the load and power consumption of the controller. In various embodiments, the two-terminal memory is provided to the memory array technology disclosed, may have about 10 or more years (e.g. at 85 ° C) to retain the memory, and the P / E cycle of approximately 1x10e ⁸ Unit tolerance. In other embodiments, the double-ended memory technology can be easily scaled down to a 5nm node, but the subject disclosure is not limited to having such a scalable double-ended memory technology.

In one or more other embodiments, the disclosed memory array may be implemented in a three-dimensional stacked arrangement. The three-dimensional stacked arrangement may be composed of, for example, a plurality of two-dimensional memory arrays (for example, two-dimensional NAND arrays, two-dimensional NOR arrays, etc.). In at least one disclosed concept, the three-dimensional stacked arrangement may include a pair of two-dimensional memory arrays stacked in three dimensions. In other concepts, a three-dimensional stacked arrangement may include four two-dimensional memory arrays stacked in three dimensions. In yet other concepts, other numbers of two-dimensional memory arrays (eg, 3, 5, 6, 7, etc.) can be stacked in three dimensions to provide a three-dimensional stacked arrangement.

According to other embodiments, the memory device is disclosed to have a high write or overwrite granularity. Write or overwrite granularity, as used herein, means that it can be programmed with a single memory operation Process, reprogram, or refresh the minimum number of units. High granularity refers to a lower minimum number of units, while low granularity refers to a higher minimum number of units. Continuing the above, the high write or overwrite granularity can be accomplished at least in part by adding a programming decoder like an input-output based (I / O-based) decoder. The I / O-based decoder can be used to implement I / O-based memory operations (such as programming, erasing, overwriting, etc.) of the memory device. I / O-based memory operations can cause the write or overwrite granularity to be equal to or smaller than the memory page. In some embodiments, the I / O-based decoder can cause the writing or overwriting granularity of multiple words (e.g., two words, four words, etc.), or even a single word (e.g., one word of data) Bytes, many bits of data, etc.). In at least one embodiment, the I / O-based decoder can cause a single bit of data to be written or overwritten (eg, a single memory unit).

In at least one embodiment, the subject matter provides a solid-state non-volatile memory storage drive that can be removably connected to a host computer device and is comprised of dual-end memory cell technology. Double-ended memory cell technology can include resistive switching memory in some concepts (eg, resistive random access memory, etc.). In one embodiment, the storage driver may have an 8-bit memory channel at a 200 MB conversion rate, and be between 1 and 8 devices per channel. Alternatively, or in addition, the storage driver may have one or more of the following characteristics: a data conversion rate of about 100 MHz, an 8-bit wide bus, a page of about 4 kB size, a time shift of about 20 μs, and a time shift of about 25 μs (Displacement time + 25% OH), a programming time of about 28 μs, a read delay of about 1 μs, a write amplification of 1, or a maximum transfer rate of about 160 MB.

Please refer to the drawings, FIG. 1 is a schematic diagram of an embodiment of a memory architecture 100 according to the present invention. The memory architecture 100 may be a subset of a memory array incorporated as part of a non-volatile, solid-state memory storage device in certain disclosed concepts. For example, the memory architecture 100 may be a memory Sub-blocks of the volume block, where the sub-block contains the global word line of the memory block, and a subset of the bit lines of the memory block that share a common set of regional word lines is an exclusive memory block Subblock.

The memory architecture 100 may include a set of bit lines 102. A set of bit lines 102 includes individual bit lines BL ₀ , BL ₁ , BL ₂ ... BL _X , where X is a positive integer greater than 1. The cross-group bit line 102 is a group of word lines 104. A set of word lines 104 includes individual word lines WL ₀ , WL ₁ ... WL _N , where N is a positive integer greater than one. In an embodiment, X may be an integer equal to 8 and N may be a positive integer equal to 512; however, X and N are not limited thereto, and may also be other suitable values.

As mentioned above, a set of bit lines 102 may be associated with sub-blocks of a memory block, so that a set of bit lines 102 share a set of regional word lines 108 of a sub-block of an exclusive memory block . Each of the sets of regional word lines 108 is connected to a memory cell group 106. The memory cell 106 has a first end connected to one of the set of bit lines 102 and a second end connected to one of the set of word lines 108. The regional word line 108 is connected to the source line 112 through each word line selection transistor 110. Each word line selection transistor 110 is positioned to be electrically connected (when activated or in a conducting state) or electrically disconnected (when not activated or in a resistive state) the respective region word line 108 and / or the source line 112. Each word line selection transistor 110 may be a gate transistor (eg, a single gate, a floating gate, etc.) in some embodiments. The gate of each word line selection transistor 110 is connected and controlled by each of a group of word lines 104, as described.

Appropriate electrical signals are applied to one of the selected bit lines 102 and one of the selected area word lines 108 to facilitate performing a memory operation on one of the targets in the memory cell 106. Applying an electrical signal to one of the selected regional word lines 108 may be achieved by one of the source lines 112 and an associated set of word lines 104 (eg, FIG. 2, below). Memory unit operations can be implemented using memory The circuit of the body architecture 100 may include startup, shutdown, programming, reprogramming, erasing, etc. The target memory unit 106 is connected to the target by applying a suitable electrical signal to one of the bit lines 102 and one of the area word lines 108 Memory unit 106 (see Fig. 6, below).

FIG. 2 is a schematic diagram of an embodiment of a memory architecture 200 according to the present invention. In at least one embodiment, the memory architecture 200 may be substantially the same as the memory architecture 100 in FIG. 1 described above. However, this is not a limitation; for example, in other embodiments, the memory architecture 100 may be programmed, overwritten, or erased according to a different memory operation process than the memory architecture 200.

The memory architecture 200 may include bit lines 202 of the memory device, including bit lines BL ₀ ... BL _X, and word lines 204 of the memory device, including WL ₀ ... WL _N , as shown in FIG. 2. The memory architecture shows that the bit lines 202 and the word lines 204 are arranged vertically (for example, the two are cross arrays), but it is not limited thereto. In some embodiments, the memory architecture 200 may be part of a three-dimensional memory array arrangement, where bit lines and word lines intersected by a plurality of two-dimensional arrays (eg, including the memory architecture 200) are stacked in three dimensions.

Generally speaking, the memory architecture 200 includes a memory cell 208 for each intersection of one of the bit lines 202 and one of the word lines 204. However, each memory cell 208 does not need a physical position where the word line 204 crosses the bit line 202. As mentioned, a group of regional word lines 210 may be interspersed between the word lines 204. Each group of memory cells 208 may include those memory cells 208 that share terminal contacts on one of the regional word lines 210. For example, the group of memory cells 208 connected to the selected column 206 may each have one end connected to one of the regional word lines 210 connected to the selected column 206. In addition, each memory cell 208 in the group of memory cells 208 may have a second end connected to one of the bit lines 202. In this way, by activating the selected column 206 and applying an operating voltage to one of the selected bit lines 202, a single memory cell 208 in the memory cell group (for example, For example, the memory cell 208 connected to the area word line 210 on the selected column 206 may be a target of a memory operation (eg, read, write, erase, overwrite, etc.).

A set of word line selection transistors 212 may be configured to electrically connect or disconnect each region word line 210 connected to the source line 214. One of the connected word lines 204 may be connected to a gate of each word line selection transistor 212. Accordingly, a suitable on / off signal is applied to the word line WL ₁ can enable or disable the selected local word line 206 is connected to the column 210. When the word line selection transistor 212 connected to the word line 204 WL ₁ is activated, the region word line 210 of the selected column 206 and the terminal of the memory cell group are connected to the region word line coupled to the source line 214 210. This process enables selection of the selected column 206. For example, applying a start signal to the word line 204 WL ₁ connects the regional word line of the selected column 206 to the source line 214. Then, by adding a suitable signal to the selected bit line 202 and the source line 214, the signal can be observed by the memory cell 208 of the selected row 206 having the first contact on the selected bit line 202 .

FIG. 3 illustrates a block diagram of a memory device 300 according to an embodiment of the present invention. In some embodiments, the memory device 300 may be a removable storage device, such as a FLASH device, and may be communicated from a host computer device (such as a computer, a notepad, etc.) through a communication interface (universal serial bus (USB) interface, etc.). Computer, terminal, smart phone, desktop computer, etc.). In other embodiments, the memory device 300 may be configured on a hardware card for connection with a servo device or other computer devices. In other embodiments, the memory device 300 may be through a suitable remote communication platform (such as a wireless interface, a radio communication interface, a satellite interface, a wired interface, an Ethernet interface, a broadband power line interface, etc.), or a suitable combination thereof. ) A stand-alone device that communicates with a remote host device.

In various embodiments, the memory device 300 may be operatively in electrical communication with the host computer device through a suitable communication interface. In at least one embodiment, the memory device 300 may To include a power line; however, in other embodiments, the memory device 300 may be powered via a communication interface. In at least one alternative embodiment, the memory device 300 may include a power source, and may also obtain power through a communication interface. In other embodiments, the memory device 300 may be integrated in a computer device, or may operate an exclusive host computer device. Those skilled in the art will appreciate that other suitable constructions of the memory device 300 are within the scope of the subject disclosure disclosed herein. For this reason, the memory device 300 may include additional components as appropriate (for example, a multi-purpose processing element, an application program for operating the multi-purpose processing element using data stored in the memory device 300, etc.) as appropriate in the description of FIG. 3.

The memory device 300 may include a memory controller 302. The memory controller 302 can be used to communicate with the host computer device through the host interface 310. The host interface 310 is operable to receive host commands from a host computer device regarding the memory module 304 on the memory device 300. Suitable host commands may include write commands, read commands, erase commands, overwrite commands, etc., or a suitable combination thereof. In addition, the host interface 310 can receive data from a host command related to the host computer device, or provide data stored in one or more memory modules 304 to the host device corresponding to the host command.

In various embodiments, the memory controller 302 may further include a memory interface 306 for communicating with a memory module 304 for performing memory operation communication, and through one or more channels / data buses 308 (herein referred to as For memory channel 308). In at least one concept, the memory channel 308 may be an 8-bit channel, but is not limited thereto in different embodiments, and one or more channels of other sizes may be used for the non-memory channel 308. In some embodiments, the memory controller 302 can perform low-level memory operations, including writing, erasing, reading, etc., on the memory module 304. In other embodiments, the memory controller 302 may execute high-level memory in the memory 302 block. Function, the memory controller (not shown) of each memory module 304 converts high-level memory functions (such as host read, write, erase commands, etc.) to low-level memory functions (such as memory card, memory, etc.) Write, memory erase, etc.) and perform low-level memory functions.

In various disclosed embodiments, the memory controller 302 may further include an error correction element 312 in combination with the ECC. In at least one embodiment, the ECC algorithm may be a relatively non-complex ECC (such as a Hamming code, a BCH code, an RS code, etc.), due to the overwriting ability of one or more memory modules 304 (for example, a reduction leads to a reduction (The P / E period of the error rate). In other embodiments, ECC may alternatively incorporate complex algorithms, such as LDPC codes and the like. In one embodiment, the memory controller 302 may also include a memory buffer 314 and a central processing unit 316 for performing memory operations on the memory module 304. In other embodiments, the memory device 300 may include a random access memory (RAM) 318 (such as a dynamic RAM or other suitable RAM) for temporary storage, high-speed operation of the memory or other obvious to those skilled in the art. Other purposes should be considered within the scope of the present invention.

The memory module 304 may include an array of memory units to store digital information, control hardware to access and write information, buffer memory (such as RAM, etc.) to facilitate control of hardware procedures and memory conversion operations, Cache, etc. or a suitable combination thereof. In some embodiments, the array of memory cells may include a staggered arrangement of double-ended memory cells (eg, resistive memory cells, resistive switching memory cells, etc.). In a staggered arrangement, word lines and bit lines crossing in the memory array can be used to facilitate the application of electrical signals to one or more of the double-ended memory cells. Furthermore, the memory module 304 may include a dual-end memory cell technology capable of directly overwriting and providing a WA value of 1 to the memory device 300. Examples of such double-ended memory cell technology can include, but are not limited to, resistive memory cells such as resistive switching memory, resistive random access memory Body, etc., or a suitable combination thereof. By using a staggered arrangement of double-ended memory cells having a WA value of 1, the inventors of the present application believe that the memory device 300 can provide good flexibility for performing memory operations. Specifically, the memory module 304 can directly overwrite the selected memory unit of each array in the memory unit. The inventors believe that the memory device 300 can alleviate or avoid the disadvantages of NAND FLASH in their point of view. NAND FLASH cannot directly overwrite the memory unit without first erasing the disadvantage of the memory block where the memory unit is located. The characteristics of NAND FLASH lead to high write amplification values (about 3 to 4), device load for garbage collection functions, complex ECC algorithms, and more. Accordingly, the memory device 300 and the memory module 304 can have significant advantages in operating efficiency, memory retention, memory life, read / write speed, and other characteristics due to the direct overwrite capability described herein.

In alternative or additional embodiments, the memory arrays of the one or more memory modules 304 may each include multiple memory blocks, where each block of at least one memory includes multiple memory sub-blocks. A schematic diagram of an embodiment of the sub-block is described by FIG. 1 and FIG. 2 above. The memory sub-block is connected to a sub-set of one of the bit lines connected to the memory sub-block. The number of bit line sub-sets can be changed according to different embodiments, just like the number of bit lines of a given bit line sub-set. Each sub-block and the connected bit line sub-set has an associated regional word line group that can monopolize the sub-block. Each sub-block also contains a group of double-ended memory cells with the same number of word lines as the memory module 304. A single group of memory cells in a sub-block includes two-terminal memory cells connected to their respective ends and a region word line of a memory sub-block. In addition, the memory cells of each group in the sub-block connect their respective ends to one of the bit-lines of the bit-line subset of the sub-block. Because each group of memory cells shares a common terminal and leakage current of a regional word line, which is also called a latent path current, it may occur in the memory sub-blocks along the word line of each area. For example, as shown in FIG. 2 above, if a voltage is applied to the bit line BL ₀ to operate the leftmost double-ended memory cell in the selected column 206, and other bit lines BL ₁ to BL _X observe the differential voltage ( For example, 0V or floating), the common path along the area word line 210 of the selected column 206 will allow a latent path current to occur between the bit line BL ₀ and each bit line BL ₁ -BL _X. These sub-path currents can reduce the sensing edges and other effects of the sensor 322.

In various embodiments, the memory module 304 may be configured according to the I / O configuration (for example, see FIG. 4, FIG. 5, and FIG. 6, below) to reduce the effect of the latent path current operating in the memory. For I / O-based connections, two or more memory cells (e.g., bytes, words, multiple words, pages, etc.) in such a memory cell group are from multiple sub-regions of the memory block Block selection. The memory arrangement in FIGS. 1 and 2 therefore, the memory cell groups will not share a common regional word line. Therefore, as an example, a single word of memory can be selected from a group of double-ended memory cells in which the 16 sub-blocks of the memory block are located. These double-ended memory cells will be connected to 16 different regional word lines, exclusive to each of the 16 sub-blocks of the memory. This method can be used to reduce or avoid the latent path current between the bit lines of each memory cell connected to the word of the memory. In the I / O-based connection, a plurality of bit lines can be selected from a plurality of memory sub-blocks for memory operation through a multiplexer arrangement configuration (for example, see FIG. 4, below). In one aspect, the number of multiple bit lines may be equal to the number of multiple sub-blocks, which means that the unique bit line of any given sub-block is selected for a given memory operation. However, other embodiments are allowed, wherein the number of the plurality of bit lines is greater than the number of the selected plurality of sub-blocks, which means that more than one bit line is from one of the selected sub-blocks or Multiple can be selected for a given memory operation. In the latter case, the latent path current between the selected bit lines will be higher than the previous case, but still less than the case discussed above, that is, the subblock's All bit lines are initiated in memory operation.

FIG. 4 shows a circuit diagram of an embodiment of a multiplexer 400 according to the present invention. In one embodiment, the multiple circuits are configured similar to a bit line of a multiplexer 400 that can be used to selectively connect or disconnect a subset of a memory block with a sense amplifier, a memory interface ( For example, an I / O contact associated with a memory interface), a power source (eg, a bias signal associated with a supply voltage), or the like, or a suitable combination thereof.

In other embodiments, the multiplexer 400 may be used to selectively interconnect one or more bit lines of the memory array, including bit lines BL ₀ 402, BL ₁ 404, having bias signal contacts 416, BL ₂ 406 ... BL _X 408 (collectively referred to as bit lines 402-408), or I / O contacts 414. In an embodiment, the I / O contact 414 may be connected to the sensing circuit 418 to facilitate reading one of the selected bit lines 402-408. In this embodiment, the multiplexer 400 can be used as a decoder that facilitates reading the memory unit. In other embodiments, I / O contacts 414 may be connected to a power source to facilitate programming, erasing, or overwriting selected bit lines 402-408. In this embodiment, the multiplexer 400 can be used as a decoder that facilitates writing and erasing memory cells. The bias signal contact 416 may be used to apply an appropriate bias signal to one or more bit lines 402-408. The bias signal can be supplied by an external power source-not shown (eg, voltage source, current source). Bias signals can be used to suppress unselected bit lines 402-408. For example, the first of the bit lines 402-408 is selected for programming and is connected to the I / O contact 414, and the other bit lines 402-408 may be connected instead of bias signal contacts 416, which can be driven to a disabled voltage, or floated, or other suitable signal to ease programming of other bit lines 402-408. As described in more detail below, multiplexer 400 may be configured to select a first subset of bit lines 402-408 to connect to (or disconnect from) I / O contacts 414 (eg, for programming , Read, erase, etc.) while selecting a second subset of bit lines 402-408 to connect to (or disconnect from) the bias signal contact 416 (for example, to inhibit programming, erasing Etc., or other suitable purpose).

In addition to the above, it should be recognized that the multiplexer 400 can be operated to dynamically select different subsets of the bit lines 402-408 for connecting or disconnecting from the I / O contacts 414 to / or dynamically select Different subsets of the bit lines 402-408 are used to connect or disconnect to / from the bias signal contacts 416 for various memory operations. Differently, the selected subset of bit lines can be dynamically changed by successive memory operations. For example, the multiplexer 400 may select a first subset of the bit lines 402-408 to connect to the first memory operation of the bias signal contact 416, and then select a second subset of the bit lines 402-408, unlike A first subset of bit lines 402-408 are connected to a bias signal contact 416 for operation in a second memory, and so on. Similarly, the multiplexer 400 may select a third subset of bit lines 402-408 (different from the first subset, the second subset) to connect to the I / O contact 414 for the first memory operation, and then A fourth subset (different from the first subset, the second subset, and the third subset) of the bit lines 402-408 is selected to connect to the second memory operation of the I / O contact 414, or the like.

Each bit line 402-408 has a related set of switches, including a respective input / output switch 410 and a respective bias signal switch 412. Therefore, BL _<0> 402 has an associated input / output switch 410 and an associated bias signal switch 412, as well, for the other bit lines 402-408. Each input / output switch 410 is turned on or off by its respective I / O selection signal (I / O _{SEL <0>} , I / O _{SEL <1>} , I / O _{SEL <2>} , ..., I / O _{SEL <X>} , where X is a suitable positive integer), including I / O _{SEL <0>} for input / output switch 410 related to BL _<0> 402, I / O _{SEL <1>} for BL related _<1> 404 related input / output switches 410, and so on. The activation of a particular I / O switch connects the corresponding bit lines 402-408 and I / O contacts 414 (for example, performing a memory operation on the corresponding bit lines 402-408). In addition to the above, each bias signal switch 412 is turned on or off by each bias selection signal (Bias _{SEL <0>} , Bias _{SEL <1>} , Bias _{SEL <2>} , ..., Bias _{SEL <X>} ), These include Bias _{SEL <0>} for bias signal switch 412 related to BL _<0> 402, Bias _{SEL <1>} for bias signal switch 412 related to BL _<1> , and so on. The specific bias signal switch 412 is activated to connect the corresponding bit lines 402-408 having bias signal contacts 416.

In operation, the multiplexer 400 may selectively connect a subset of the bit lines 402-408 to the I / O contact 414, and by activating the corresponding I / O selection signal of the subset of the bit lines 402-408, And the bias selection signals of the corresponding subset of the bit lines 402-408 are disabled. Other bit lines 402-408 can be isolated from I / O contacts 414 by disabling the I / O selection signals corresponding to these bit lines 402-408. Alternatively, other bit lines 402-408 can be suppressed or floated. By activating the bias selection signals of these other bit lines 402-408, the other bit lines 402-408 are connected to the bias signal contact 416. It can be connected to a disable signal or floating. In one example of operation, the multiplexer 400 may be operated so that a first subset of the bit lines 402-408 is connected to the I / O contacts 414 and a second subset of the bit lines 402-408 is connected To the bias signal 416, or operate to suppress a second subset of the bit lines 402-408.

FIG. 5 depicts a block diagram of an input / output memory configuration 500 according to an embodiment of the present invention. The input / output memory configuration 500 can promote 1-bit overwrite capability because it can access and perform writing, reading, and erasing a single bit of a memory sub-block.

The input / output memory configuration 500 may include an arrangement of 1 transistor-z resistors (1TzR), where Z is a positive integer greater than 1. In one embodiment, Z may have a value of 8, although the subject disclosure is not limited to this example. Those skilled in the art will understand alternative or additional transistor, resistor configurations, such as 1T4R, 1T16R, 1T128R, and other suitable configurations, and are within the scope of the considerations disclosed in this subject.

In a further embodiment, the input / output memory configuration 500 may include a dual-end memory unit with direct overwrite capability. The memory unit has an overwrite capability which can be an effective input / output memory configuration 500. Due to the efficient overwrite capability, a dual-end memory unit for the I / O memory configuration 500 can be used for the I / O memory configuration 500 to provide a WA that is smaller than many typical comparable memory configurations (e.g., NAND FLASH) value. In a specific embodiment, the WA value can be 2 or less. In at least one embodiment, the WA value may be one. Therefore, in some embodiments, the input / output memory configuration 500 may be used as part of a memory storage device and help improve data retention and device life due to the lower P / E cycle. In addition, the inventor of the present application believes that such a memory storage device can have a device with significantly lower load ratio incorporating a garbage collection algorithm, a complex ECC code, and a complex average erase algorithm.

The input / output memory configuration 500 may include multiple memory sub-blocks, including sub-block ₁ 502, sub-block ₂ 504 to sub-block _Y 506, where Y is a suitable integer greater than 1. Memory sub-blocks are collectively referred to as sub-blocks 502-506. Each memory sub-block 502-506 includes a corresponding N bit lines, where N is a suitable integer greater than 1. Specifically, sub-block ₁ 502 includes BL ₁ <0: N> 508 of the first group of bit lines, sub-block ₂ 504 includes a second group of bit lines BL ₂ <0: N> 512, and sub-block _Y 506 includes the Y-th bit line BL _Y <0: N> 514 (collectively referred to as bit line groups 508, 512, 514). Each set of bit lines 508, 512, and 514 includes a corresponding set of regional word lines that are dedicated to a respective one of the set of bit lines 508, 512, 514. Memory cell groups can be activated, by activating global word lines associated with specific groups of memory cells, and by applying signals to affect specific memory sub-blocks 502-506 (see, for example, memories in Figures 1 and 2 Global word line and selection line of the body sub-block). A particular memory cell activated by a memory cell group may be addressed by an individual bit line of one of the bit line groups 508, 512, 514 associated with the activated group.

Figure 5 shows a selected set of bit lines 510, including sub-block ₁ 502 of BL ₁ <0> 510A, sub-block ₂ 504 of BL ₂ <0> 510B, and BL _Y <0 to sub-block 506 > 510C, where each bit line 510A, 510B group selection bit line 510 is a member of a different sub-block 502-506 of memory. Because each sub-block of the memory 502-506 has a regional word line dedicated to the sub-blocks 502-506 of the memory, there is no direct path to configure the bits of 500 different sub-blocks along any existing input / output memory Local word line memory 502-506 between lines. Therefore, the memory operation bit line associated with the selected group may have the selected bit line 510. This minimum minimum latent path current helps to configure a higher number z in 1TzR memory, and improves the overall memory density of the input / output memory configuration 500.

In operation, the I / O memory configuration 500 may include a set of subsets multiplexed to a set of connection bit lines 508, 512, 514 and respective I / O contacts. The group of multiplexers includes a multiplexer 518A for subblock 1502, a multiplexer 518B for subblock 2504, and a multiplexer 518C for subblock 506. (Collectively referred to as multiplexers 518A-518C). The corresponding multiplexers 518A-518C can be configured to selectively connect or disconnect a subset of each of the bit lines 508, 512, 514 and the first I / O contact 516A through the YI / O Contact 516C The second I / O contact 516B (collectively referred to as I / O contacts 516A-516C). In Figure 5, the example depicted in the leftmost bit lines 510A, 510B, 510C (collectively referred to as the leftmost bit lines 510A-510 ° C) -506 includes the selected bit line 510, which is determined by the corresponding multi The converters are connected to the 518A-518C of the corresponding sub-blocks 502 to the respective I / O contacts 516A-516C. Through the I / O contacts 516A-516C, the memory cell-510C of the leftmost bit line 510A can be operated for the memory. In some embodiments, I / O contacts 516A-516C can be connected to a power source, making the power source available With the leftmost bit lines 510A-510C (one selection line 502-506 in each sub-block of the combined memory, for example, see FIG. 6, below) for writing, erasing, or covering the leftmost bit lines One or more memory cells 510A-510C. In alternative or additional embodiments, I / O contacts 516A-516C can be connected to sensors (see, for example, sensing figure 4, ibid. Circuit 418) so that the leftmost bit lines 510A-510C can be read as Part of a read operation.

It should be understood that although the I / O memory structure 500 shows a selected set of bit lines 510, one from each sub-block -506 of the memory 502, other numbers of the selected bit lines 510 may be used for memory operations, rather than activated . For example, more or fewer selected bit lines 510 may be activated. In at least one embodiment, a single bit line may be selected for a memory operation. Especially in the case of a refresh, or during an overwrite operation, the memory granularity of a single bit line / memory cell may result in great flexibility in overwriting or refreshing data. It should be understood, however, that other numbers of bit lines may be connected to the I / O contacts 516A-516C. In at least one embodiment, at most all groups of bit lines 508, 512, 514. According to the latter implementation (S) in combination with a large number of write or erase operations, for example, the IO memory configuration 500 can perform page erase, sub-block erase, block erase, etc., or page / sub-block / Block write.

FIG. 6 shows a schematic diagram of an example memory operation 600 according to a further embodiment disclosed by the subject matter. In one or more embodiments, the memory operation 600 may include an I / O-type memory operation. Therefore, in this embodiment, multiple memory cells for the memory operation 600 are selected from different subsets of the memory array, that is, not directly connected to a word line or a local word line. Therefore, the memory operation 600 has a certain degree of inherent latent pathways to mitigate the memory operation 600.

Memory operation 600 working memory, including a set of memory sub-blocks, which includes sub-blocks 1602, 2604, and sub-blocks 606 (collectively called sub-blocks of memory 602-606). A set of memory cells, from a single corresponding bit line of each sub-block selected from memory 602-606, can be targeted for memory operations (e.g., in a write operation, a rewrite operation, a read operation, a erase operation Division operation, refresh operation, and so on). Note that the size of the group of memory cells may vary. In various disclosed embodiments, from a single memory cell of a single bit line to a word line or multiple word lines intersecting memory cells of all bit lines on a page, all A unit of a memory block, or some other suitable combination of memory units.

Selected for use in memory operations, three memory cells that are always in this example are enclosed in shaded ovals in FIG. 6. In this case, one three-bit information 1-0-1 is programmed into three selected memory cells. Note that this 3-bit information can be programmed into three selected memory cells regardless of whether they are currently being erased or programmed, in at least one embodiment. To complete the programming of the three-bit information, the program signal 608 is applied to the subblock 1602 of BL1 <0>, and the <0> of the BLY subblock 606, as depicted, is applied to the source with ground or zero voltage 610 The line subblock1602 is divided into blocks 606. This applies a positive voltage signal to the sub-blocks 602, 606 in the selected memory cell, and the target cells are programmed to a logic state of one. In addition, zero volt 610 or ground is applied to the sub-block 2604 <0> of BL2, and an erase signal 612 is applied to the source line of the sub-block 2604 to erase the logic state of the target cell to zero. In one embodiment, the erasure signal 612 may have the same size as the program signal 608. In another embodiment, the erasure signal 612 and the program signal 608 may have different amplitudes.

The aforementioned figures have described relative to the interacting memory cells between several components of such a memory cell, or between memory architectures. It should be understood, however, that some suitable alternative aspects disclosed in this subject matter, such as diagrams, may include those components and structures specified therein, certain specified components / hardware architectures, or additional components / hardware architectures. . Subgroup Components can also be implemented to be electrically connected to other child components rather than included in the parent architecture. In addition, it should be noted that one or more of the disclosed methods can be combined into a single process to provide aggregation functions. For example, the deposition process may include a filling or etching process, an annealing process, or the like, or vice versa, to promote deposition, to fill or memorize the cell layer by an etching process in a polymerized manner. The components of the disclosed architecture may also interact with one or more other components not specifically described herein but known by those skilled in the art.

The description of the exemplary diagrams in the figure is the same as above, and the processing method may be better understood according to the disclosed subject matter implementation. Referring to FIG. 7, FIG. 8, and flowchart 9, although in the description for simplicity, the methods of FIG. 7, FIG. 8, and FIG. 9 are shown and described as a series of blocks, it is understandable and understandable, so The claimed subject matter is not limited by the order of the blocks, which may be depicted and described in certain blocks in different orders or concurrently with other blocks. In addition, not all illustrated blocks may be required. Implement the methods described herein. In addition, it should be further understood that the methods disclosed throughout the specification can be stored in the manufacture of articles to facilitate the transportation and delivery of electronic devices for these methods. The term article of manufacture, as used, is intended to include a computer program accessed from any suitable computer-readable device, the device being combined with a carrier, storage medium, or the like, or a suitable combination.

FIG. 7 shows a flowchart of an exemplary method 700 for manufacturing. A storage device according to other embodiments disclosed in this subject. At 702, method 700 may include creating a substrate array of memory cell word lines and bit lines arranged in an array relative to a plurality of two terminals. The double-ended memory cell may be a resistive memory cell in one embodiment (eg, resistive memory, resistive random access memory, etc.). In other embodiments, another dual-ended memory technology may be used as a plurality of dual-terminal memory cells. In various embodiments, the method 700 may further include arranging the plurality The double-ended memory unit is divided into a plurality of memory blocks, each of which has multiple sub-blocks of the double-ended memory unit.

At 704, method 700 may include connecting a respective set of local word lines to a single set of word lines on each set of double-ended memory cells. In one embodiment, the set of local word lines may be the one or more memory blocks exclusive. In an additional embodiment, the two double-ended memory units in the set may be dedicated to one or more memory blocks in the one associated sub-block of the plurality of bands.

At 706, method 700 may include providing a set of input-output interfaces configured to provide electrical power to multiple bit lines or multiple word lines simultaneously. In various embodiments, the set of input-output interfaces may be configured as a subset of the configuration of the I / O memory connected to the double-ended memory unit. In some embodiments, the set of input-output interfaces may be arranged as a sensing circuit of a plurality of bit lines or a plurality of word lines that are selectively connected or disconnected, for reading a subset of the double-ended memory cells. .

At 708, method 700 may include providing a memory controller configured to facilitate direct rewriting of several double-ended memory cells. In various embodiments, a memory controller may be provided so as to cover the double-ended memory unit without first resident blocks of the double-ended memory cells within the erased memory, or without erasing the double-ended memory cells themselves. In another embodiment, the memory may provide control means so as to cover several double-ended memory cells that are smaller than a single page of the two-ended memory cells. In at least one embodiment, a memory controller may be provided so as to cover one word of a double-ended memory cell among a plurality of word cells stored in two terminals, or as little as a single memory cell at both ends.

FIG. 8 illustrates a flowchart of an exemplary method 800 for manufacturing a memory. According to this Arrays in other embodiments of the invention. At 802, method 800 may include forming an array of resistive memory cells. Forming the array may further include a plurality of blocks arranged as a memory in the resistance storage unit. In some embodiments, the plurality of blocks arranged as a memory in the resistive memory unit may further include a corresponding one of the plurality of blocks of the memory unit arranged in the resistive memory unit to a plurality of sub-blocks of the memory unit.

At 804, method 800 may include creating an array of resistive memory cells for a set of bit line pairs. At 806, method 800 may include connecting respective subset lines to respective sub-blocks of the memory cell. At 808, method 800 may include creating memory for a set of word lines. At 810, method 800 may include various blocks of memory cells connecting subset word lines. At 812, method 800 may include forming an input-output interface for applying signals to the input-output interfaces of the corresponding bit lines of the plurality of subsets. At 816, method 800 may include providing a plurality of sub-blocks of a memory controller configured to cause the decoder / multiplexer to connect a corresponding input-output interface of a memory cell of a bit line from one or a corresponding one to facilitate An I / O-based memory configuration for a resistive memory cell array.

FIG. 9 illustrates a flowchart of an example method 900 for operating a memory. Arrays according to one or more other embodiments disclosed herein. At 902, method 900 may include receiving a set of data that is programmed as a subset of a logical memory block, NAND or NOR, logic based on non-volatile solid state memory. At 904, method 900 may include interconnecting the memory to a set of write interfaces to the programming paths of a subset of the respective blocks. At 906, method 900 may include a subset of the blocks in memory of the written data set. At 908, method 900 may include receiving a corresponding number of memory cells of a second subset of the memory unit of a subset of eight or fewer bits and blocks to cover the second set of data. In addition, method 900, in 910, may include covering eight or fewer bits to store The corresponding number of writes to the storage element is less than two. In addition to augmentation, rewriting may include data of other memory cells that maintain a subset of the blocks in the memory to which the subset settings are written. In at least one embodiment, the method 900 may include interconnected bit lines, the number of corresponding memory cells associated with each, and a separate sub-block memory located in the block, having a subset of the input-output interface. The corresponding one. In another embodiment, method 900 may include applying a forward polarity programming voltage to one of eight or fewer bits to each connected bit line to be programmed as a logic one through the second set of data. In other embodiments, method 900 may include applying a reverse polarity erase voltage to each bit line pair of one of eight or fewer bits connected by a second set of data programmed to logic zero.

In order to provide background, for each aspect of the disclosed subject matter, FIG. 10 and the following discussion, the present invention aims to provide a simple, general description of a suitable environment, in which the disclosed subject matter of each aspect can Implementation or processing. Although the subject matter has been described above in terms of the semiconductor architecture and process methods of manufacturing or generally operating such an architecture, those skilled in the art will recognize that the present disclosure may also be implemented in combination with other methods of structure or process. In addition, those skilled in the art will understand that the disclosed process may be a processing system or a processor of a computer, or may be implemented alone or within a host computer, which may include a single processor or a combination of multiple processors computer systems, small Computing devices, mainframe computers, as well as personal computers, handheld computing devices (eg, PDAs, smartphones, watches), microprocessor-based or programmable consumer or industrial electronic devices, and the like. The illustrated aspect can also be implemented in a distributed computing environment where tasks are performed by remote processing devices linked through a communication network. However, for some, if not all aspects of the claimed innovation can be implemented independently in electronic devices such as memory cards, flash memory modules, removable memory, or the like. In a distributed computing environment, program modules can be located in two local and remote memory stores Module or device.

FIG. 10 shows a block diagram of an example operation and control. The storage cell array 1002 of the environment 1000 is disclosed in accordance with various aspects of the subject matter. In at least one aspect of the subject disclosure, the memory cell array 1002 may include various memory cell technologies. In particular, the memory cell array 1002 may include a double-ended memory such as a resistive memory cell, as described.

The column controller 1006 may form an adjacent memory cell array 1002. Moreover, the column controller 1006 can electrically couple the memory cells of the bit line to the array 1002. The column controller 1006 can control the corresponding bit line, use appropriate programming, erase or read voltage, and select the bit line.

In addition, the operation and control environment 1000 may include row controllers 1004, row controllers 1004 may form adjacent column controllers 1006, and word lines electrically connected with row controllers 1004 tanks of the memory cell array 1002. Select a specific row of memory cells with the appropriate selection voltage. In addition, the bank controller 1004 can be easily programmed, erased or read out on a selected word line by applying a suitable voltage.

The clock source 1008 can provide corresponding clock pulses for timing read, write, row control 1004 and column control 1006 clock program operation source 1008 can further facilitate the selection of word line or bit line in response to the operation and control environment 1000 The receiving external or internal command input / output buffer 1012 may be connected to an external host device, such as a computer or other processing device (not shown) by an I / O buffer or other means of I / O communication interface. The input / output buffer 1012 may be configured to receive write data, receive an erase instruction, output read data, and receive address data and command data, and the address data are respective instructions. Address data can be transferred to the row controller 1004 and column controller 1006 by the address register 1010. In addition, input data is transferred to the memory cell array 1002 through signal input lines, and output data is transferred from the memory unit through signal output lines. The meta array 1002 receives. Input data can be received from the host device, and output data can be passed to the I / O buffer of the host device.

Command received from the host device. The command interface 1014 may be provided to a command interface 1014. The command interface 1014 may be configured to receive external control signals from the host device and determine whether data is input to the input / output buffer. Or address. Input commands can be transferred to a state machine 1016.

The state machine 1016 can be configured to manage the reprogramming of the state machine 1016 of the program and the memory cell array 1002, from the received command via the input / output interface 1012 and the command interface 1014, to manage reading, writing, and erasing with the host device , Data input, data output, and associated similar function memory cell array 1002. In some aspects, the state machine 1016 may send and receive various commands regarding successful reception or execution of confirmations and negative confirmations.

To perform read, write, erase, input, output, etc. functions, the state machine 1016 can control the clock source (S) 1008. Controlling the clock source (S) 1008 can cause the output pulses to be configured to facilitate row controller 1004 and column control. The controller 1006 performs a specific function. The output pulses can be delivered to selected bit lines through the column controller 1006, for example, or word lines by the row controller 1004, for example.

The illustrated aspects of the invention may also be linked over a communication network in a distributed implementation of a computing environment in which certain tasks are performed by a remote processing device. In a distributed computing environment, program modules or stored information, instructions, or similar, can be located in local or remote memory storage devices.

In addition, it can be understood that the various components described herein may include electrical circuits (secondary), which may include components and circuit elements of suitable values in order to implement the subject innovation (secondary) implementation. In addition, it is also understood that many different components can be implemented in one or more Integrated circuit chip to achieve. For example, in one embodiment, a group of components can be implemented on a single integrated circuit chip. In other embodiments, one or more corresponding components are manufactured or implemented on a separate IC chip.

In connection with FIG. 11, the systems and processes described below can be implemented in hardware, such as a single integrated circuit (IC) chip, multiple integrated circuits, an application specific integrated circuit (ASIC), or the like. Furthermore, each process that appears in some or all of its processing blocks should not be considered limiting. Instead, it should be understood that some process blocks can be executed in various commands and not all can be explicitly stated here.

11, a suitable environment 1100 implements various aspects of the claimed subject matter including a computer 1102, which includes a processing unit 1104, a system memory 1106, a codec 1135, and a system bus 1108. The system components of the system bus 1108 are coupled, including, but not limited to, a system memory 1106 to a processing unit 1104. The processing unit 1104 may be any different available processor. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 1104.

The system bus 1108 may be several types of bus structures, including a memory bus or a memory controller, a peripheral bus or an external bus, and / or any of the local buses used. Various available bus architectures include, but are not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association Bus (PCMCIA), FireWire (IEEE1394), and Small Computer System Interface (SCSI).

System memory 1106 includes volatile memory 1110 and non-volatile memory The basic input / output system (BIOS) of 1112 contains basic routines to transfer information between elements within the computer 1102, such as during startup, and is stored in the non-volatile memory 1112. Further, according to the present innovation, the codec 1135 may include at least one encoder or decoder, wherein at least one of the encoder or decoder may be made of hardware, software, or a combination of hardware and software. Although the codec 1135 is described as a separate component, the codec 1135 may be included in the non-volatile memory 1112 by way of illustration, and not limitation, the non-volatile memory 1112 may include read-only memory (ROM), Programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. The volatile memory 1110 includes a random access memory (RAM), which acts as an external cache memory. According to this aspect, the retry logic (not shown in FIG. 11) of the write operation that can be stored in the non-volatile memory is shown. By way of illustration and not limitation, RAM is provided in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM) .

The computer 1102 may also include removable / non-removable, volatile / nonvolatile computer storage media. Figure 11 shows, for example, disk storage 1114 disk storage 1114 includes, but is not limited to, such as disk drives, solid state disk (SSD) floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory adhere to. In addition, the disk storage 1114 may be used alone or in combination including storage media and other storage media including, but not limited to, optical disk drives, such as ROMs (CD-ROMs) of CD disk devices, recordable CD drives (CD-R drives), Erasing an optical disc drive (CD-RW drive) or digital versatile disc ROM drive (DVD-ROM). In order to facilitate the connection of the storage device 1114 to the system bus 1108, the removable or non-removable interface is commonly used, such as the interface 1116. It can be understood that the storage device 1114 can store Store information about users. Such information may be stored or provided to a server or an application running on a user device. In one embodiment, the user may be notified (eg, by the output device (S) 1136 of the type of information), which is stored in the disk storage 1114 method and / or sent to a server or application. The user may be provided the opportunity to opt in or opt out of having such information collected and / or shared with a server or application (eg, by entering from an input device (S) 1128).

It should be understood, however, that FIG. 11 depicts software, which includes an operating system 1118 as software such as an intermediary environment 1100 between suitable operating instructions users and basic computer resources. The operating system 1118 can be stored in the disk storage 1114, and its role is to control and allocate computer resources. The system 1102 uses 1120 to multiply resources into the resource. It operates through the operation management system 1118 through program modules 1124 and program data 1126, such as boot / shutdown transaction tables. Or it can be understood in the system memory 1106 or the disk storage 1114 that the claimed subject matter can be implemented in various operating systems or a combination of operating systems.

Commands or information entered by the user are input to the computer 1102 via input devices (times) 1128. Input devices 1128 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game Pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, etc. These and other input devices are connected to the processing unit 1104 via the system bus 1108. The interface port 1130 includes, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). The output device (time) 1136 uses some of the same types of ports as the input device (S) 1128. Therefore, for example, a USB port can be used to provide input to the computer 1102 and output information from the computer 1102 to the output device 1136. The output adapter 1134 is set to illustrate There are some output devices 1136 monitors, speakers, and printers as well as other output devices 1136, which require special adapters. The output adapter 1134 includes, by way of illustration and not limitation, a video card and a sound card that provide an output device 1136 and a system bus 1108. The connection between these should indicate that other devices and / or systems of the device provide input and output functions, such as a remote computer (S) 1138.

Computer 1102 can operate to one or more remote computers using logical connections in a network environment, such as remote computer (time) 1138. Remote computer (time) 1138 can be a personal computer, server, router, network PC, workstation, micro-based Processor devices, peer devices, smartphones, tablets or other network nodes, and often include many elements. Description relative to the purpose of computer 1102. Only the memory storage device 1140 is shown with a remote computer (second). 1138. The remote computer (S) 1138 is logically connected to the computer 1102 through a network interface, and the communication interface (S) 1144 is network interface 11421142, and then connected to include wired and / or wireless communication networks such as local area network (LAN) and wide area network (WAN) and cellular The internet. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, and Token Ring. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks, such as Integrated Services Digital Network (ISDN) and variants on which packet-switched networks, and digital subscriber lines (DSL).

Communication connection (secondary) 1144 refers to hardware / software to connect network interface 1142 to bus 1108. Although the communication connection 1144 is shown in the internal computer 1102 for clarity, it may also be an external computer 1102. Required for connecting to the network interface 1142 includes hardware / software for exemplary purposes only, internal and external technologies such as modems, including conventional telephone-grade modems, cable modems and DSL modems, ISDN adapters, and there are Wire and wireless Ethernet cards, hubs and routers.

As used herein, the terms "component", "system", "architecture", etc. are intended to refer to a computer or electronic related entity, or a combination of hardware, hardware and software, software (eg, in execution), Or firmware. For example, a component may be one or more transistors, memory cells, transistors or memory cells in an arrangement, a gate array, a programmable gate array, an application specific integrated circuit, a controller, a processor, the processor, an object, An executable program, program or process running on an application program accesses or uses a semiconductor memory, a computer or the like, or a combination of suitable interfaces. The component may include erasable programming (e.g., the process indicates, at least in part, stored in erasable memory) or hard programming (e.g., the process creates instructions that burn into non-erasable memory).

By way of illustration, the processing from memory and processor execution can be components. As another example, an architecture may include arranging electronic hardware (eg, parallel or serial transistors), processing instructions, and a processor. The processing instructions of this embodiment are suitable for arranging electronic hardware. In addition, the architecture may include individual components (e.g., a transistor, a gate array, ...) or components (arranged in a structure such as a series or parallel transistor, the gate array and program circuits, power leads, electrical connection ground, input signal lines And output signal lines, and so on). A system may include one or more components and one or more structures. An exemplary system may include a switch block structure that includes input / output lines and pass gate transistors, as well as a power source (S), signal generator (S), communication bus (SES), controller, I / O Interface, address register, etc. It should be understood, however, that in defining some overlapping expectations, and that an architecture or system can be a separate component, or a component, system, etc. of another architecture.

In addition to the above, the subject matter of the present disclosure may be implemented as a method, an apparatus, or a system. An electronic device manufactured using typical manufacturing, programming, or engineering techniques to produce hardware, firmware, software, or any suitable combination of items to implement the disclosed subject matter. The terms "apparatus" and "article of manufacture", as used herein, are intended to include an electronic device, semiconductor device, computer or computer program to access any computer-readable device, carrier or medium. Computer-readable media can include hardware media or software media. In addition, the media may include non-transitory media, or transmission media. In one example, non-transitory media may include computer-readable hardware media. Specific examples of hardware of the computer-readable medium may include, but are not limited to, magnetic storage devices (for example, hard disks, floppy disks, magnetic stripe ...), optical disks (for example, compact disks (CD), digital versatile disks (DVD). ..), smart cards, and flash devices (for example, cards, sticks, key drives ...). Computer-readable transmission media may include carrier waves, or the like. Of course, those skilled in the art will recognize that many variations can be made to the present configuration without departing from the scope or spirit of the subject matter of the present disclosure.

What has been described above includes embodiments of the invention. It is, of course, impossible to describe all possible combinations or methods of components in order to describe the subject innovation, but one of ordinary skill in the art can recognize that many further combinations of the subject innovation and permutation are possible. Accordingly, the disclosed subject matter is intended to include all such alterations, modifications, and variations which fall within the spirit and scope of the invention. Furthermore, the extent to which the term "includes", "includes", "has" or "has" and its variants is used in the detailed description or claims, this term is intended to be inclusive in a manner similar to the term When "including" is used as "including," the scope is interpreted as a transition.

Furthermore, the word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" should not necessarily be construed as superior to or superior to other aspects or designs. Rather, the words used are exemplary to present concepts in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless As otherwise specified, or clear from the context, "X uses A or B" means any natural inclusive arrangement. That is, if X uses A; X uses B; or X uses A and B, then "X uses A or B" is satisfied in any of the above examples. Furthermore, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.

In addition, some parts of the detailed description have been performed on algorithms or processes for electronically storing data bits within the scope of presentation authority. These process descriptions or representations are equally proficient for others who recognize that the mechanisms employed in the prior art effectively convey their work. Process is here, and is usually considered a self-consistent sequence of behaviors leading to the desired result. Those whose behavior is a physical quantity require physical manipulation. Typically, although not necessarily, these quantities are stored, transmitted, combined, compared, and / or otherwise manipulated in the form of the ability of electrical and / or magnetic signals to pass through.

He has been shown to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like, mainly for general reasons. It should but remember that all these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, or apparent from the foregoing discussion, it should be understood throughout the disclosed subject matter that discussion of the use of processes such as processing, computing, copying, mimicking, determining or sending, etc., refers to the processes of action and processing systems, and / Or similar consumer or industrial electronic equipment or machines, the manipulation or transformation of electronic equipment (S) represented as physical data or signals (electrical or electronic), the number of incoming circuits, registers or memories, and other data signals are similarly represented System memory or register or other such information storage, transmission and / or display device in a physical quantity machine or computer.

About the various functions, architectures, circuits, processes performed by the above components And similar terms (including the reference to "means") used to describe these components for a corresponding purpose, unless otherwise stated, any component that performs a specified function (e.g., a functional equivalent) of the described component, Even if the structure is not identical to the disclosed structure, the implementation aspect of the embodiments in the function described herein is a matter of exemplary aspects. In addition, while a particular feature may have been disclosed only with respect to one of several implementations, such a feature may be combined with one or more other features of other implementations for any given or particular application that may be desirable and advantageous. It will also be recognized that embodiments include a system and a computer-readable medium having a flow of computer-executable instructions for performing various actions and / or events.

Claims (19)

A solid-state non-volatile memory storage device for communication connection to a computer device includes: an array of a plurality of double-ended memory cells, which is configured to operate with a plurality of word lines and bit lines; and a memory A controller for receiving a set of data from the computer device and accessing at least a subset of the double-ended memory units, the subset containing the same or less than one page of the double-ended memory elements, and using Writing the set of data to the subset of the double-ended memory units and overwriting an existing data to the subset of the double-ended memory units, wherein the memory controller is used to overwrite the existing The data does not need to erase a physical location area to store the existing data, and the write amplification of the solid non-volatile memory storage device is equal to 1. The solid-state non-volatile memory storage device according to claim 1, wherein the computer device includes a memory storage device and a main controller for controlling the memory storage device. The solid-state non-volatile memory storage device according to claim 2, further comprising a first area word line connected to a first terminal of a dual-end memory unit connected to a subset of the dual-end memory units. And a second regional word line connected to a second dual-end memory cell of the subset of the dual-end memory cells, the first regional word line and the second regional word line being through the plurality of One of the word lines is activated. The solid-state non-volatile memory storage device according to claim 3, wherein activating the area word line causes the double-ended memory unit of the subset of the double-ended memory units to write a part of the set of data and Overwrite part of the information that exists. The solid-state non-volatile memory storage device according to claim 1, wherein the subset includes 8 or less double-ended memory units. The solid-state non-volatile memory storage device according to claim 1, wherein the subset comprises a single double-ended memory unit. The solid-state non-volatile memory storage device according to claim 1, further comprising: a set of input-output interfaces; a set of regional word lines controlled at least in part by one of the plurality of word lines; and a multiplexing element Is used to selectively connect each double-ended memory unit of the double-ended memory element group with each input-output interface of the set of input-output interfaces in cooperation with a memory operation. The solid-state non-volatile memory storage device according to claim 7, wherein the double-ended memory cell group includes at least two double-ended memory cells coupled to different regional word lines of the set of regional word lines. The solid-state non-volatile memory storage device according to claim 8, wherein the multiplexing element cooperates with the memory operation to be coupled to one of the first set of regional word lines and the first one of the groups in the group. The double-ended memory unit is connected to a first input-output interface of the set of input-output interfaces, and a second double-ended memory unit of the group that is to be coupled to one of the set of regional word lines and the second regional word line. Connected to one of the two I / O interfaces. The solid-state non-volatile memory storage device according to claim 7, wherein: the memory controller is configured to select the dual-end memory unit from a pair of memory cells on each of the regional word lines on a subset of the set of regional word lines. Each dual-end memory cell of the end-memory cell group; and the multiplexing element cooperates with the memory operation to cause each of the regional word lines of the subset of the set of area-word lines of the dual-end memory cell group to The double-ended memory unit is interconnected with each input-output interface of the set of input-output interfaces. The solid-state non-volatile memory storage device according to claim 7, wherein the multiplexing component causes one of the double-ended memory cell groups to be interconnected with one of the input-output interfaces and is not connected or Inhibits the remaining dual-end memory units in the group and the set of input-output interfaces. The solid-state non-volatile memory storage device according to claim 11, wherein the memory controller is further configured to write or overwrite one of the dual-end memory cell groups without writing or overwriting The remaining double-ended memory units of the group. A method for manufacturing a double-ended memory array includes: generating an array of a plurality of double-ended memory cells corresponding to a plurality of word lines and a plurality of bit lines on a substrate; and a single word on the plurality of word lines On the line, each regional word line of a group of regional word lines is connected to each pair of double-ended memory cell groups; a set of input and output interfaces are provided for supplying power to a plurality of the bit lines or a plurality of the word lines at the same time; and A memory controller is provided for receiving a set of data and directly overwriting the set of data to a single group of a plurality of double-ended memory units which are the same or smaller than the double-ended memory units. The method according to claim 13, further comprising arranging the plurality of double-ended memory cells, the plurality of word lines, and the plurality of bit lines in a NAND or NOR memory interface or architecture. The method according to claim 13, further comprising providing a multiplexing decoder for selectively connecting or disconnecting the plurality of bit lines or a subset of the plurality of word lines to a subset of the input / output interface. The method according to claim 15, further comprising configuring the multiplexing decoder to selectively selectively interconnect a single line in the bit line with a single line in the input-output interface set, so as to facilitate writing or overwriting. Higher than a single one of the multiple double-ended memory units. The method according to claim 15, further comprising: configuring the multiplexing decoder to selectively interconnect a plurality of the bit lines with a corresponding subset of the set of input / output interfaces, the plurality of bits The line includes a bit line selected from each of a plurality of bit line sub-sets in the array; and the memory controller is configured to simultaneously read, write, erase, or overwrite at least one double-end memory cell Each of the plurality of bit lines. A method for operating a solid non-volatile memory, comprising: receiving a group of data based on a non-volatile solid-state memory that is programmed into a logical NAND or NOR block of a block of memory; the memory The programming path of the sub-set of the block is interconnected to each set of writing interfaces; writing the set of data to the sub-set of the memory block; receiving a second set of data of 8 bits or less and the A plurality of memory cells corresponding to the subset of the memory block to overwrite the second set of data; and when the subset of the set of data is maintained is written to the subset of the memory block For other memory units, the 8-bit or less bits are overwritten to the corresponding plurality of memory units having a write amplification equal to 1. The method according to claim 18, wherein overwriting the 8-bit or lower bit further comprises: interconnecting a bit line with each input-output interface of a group of the input-output interface, the bit line is related to the Each of the corresponding plurality of memory cells is related to separate sub-blocks located in the memory block; a positive polarity programming voltage is applied to one of the 8-bit or less bits Each bit line of one is used to be programmed as a logic one by the second set of data; and a reverse polarity erase voltage is applied to each bit coupled to one of the eight bits or less A meta-line is used to program a logic 0 to the second set of data.