TWI629546B - Liquid crystal display device and pixel structure thereof - Google Patents

Abstract

A liquid crystal display device and its pixel structure. The pixel structure includes a first upper electrode, a first transistor, a second upper electrode, and a second transistor. The first upper electrode has a first pattern having opposing first and second ends and having at least one first slit. The first transistor is adjacent to the first end. The second upper electrode has a second pattern having opposite third and fourth ends and having at least one second slit. The third end is adjacent to the second end and the fourth end is remote from the second end. The second transistor is disposed between the second end and the third end. The second pattern of the second upper electrode is the same as the first pattern of the first upper electrode according to the Y-axis of the XY coordinate system, and the X-axis of the XY coordinate system corresponds to the extension of the scanning line of the liquid crystal display device. direction.

Description

Liquid crystal display device and its pixel structure

The present invention relates to a liquid crystal display device and a pixel structure thereof, and particularly to a liquid crystal display device and a pixel structure thereof which are applied to a multi-domain pixel structure.

In the current trend of multimedia diversification, the demand for viewing angles and color performance of tablet computers, notebook computers or smart phones is becoming stricter. In Phase Switching (IPS) liquid crystal display devices and Fringe Field Switching (FFS) liquid crystal display devices are currently the best viewing angle and color performance technology. Since the IPS liquid crystal display device and the FFS liquid crystal display device are driven by a horizontal electric field, their dependence on the viewing angle is not large. Compared with other types of liquid crystal display devices, such as a twisted nematic (TN) (TN) liquid crystal display device or a vertical alignment type (VA) liquid crystal display device, the IPS liquid crystal display device and the FFS liquid crystal display device have no large viewing angle gray. The disadvantage of order reversal or large viewing angle. However, the IPS liquid crystal display device and the FFS liquid crystal display device need to apply a multi-domain technical pixel structure to compensate for the color shift condition, and the current multi-domain technical pixel structure is liable to cause dark lines.

Therefore, there is a need for a liquid crystal display device and its pixel structure to avoid the generation of dark lines.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a pixel structure thereof, wherein the electrode included in the pixel structure forms a mirror structure, thereby preventing generation of dark lines.

One aspect of the present invention is to provide a pixel structure of a liquid crystal display device. The pixel structure includes a first upper electrode, a first transistor, a second upper electrode, and a second transistor. The first upper electrode has a first pattern having opposite first and second ends and having at least one first slit. The first transistor is adjacent to the first end. The second upper electrode has a second pattern having opposite third and fourth ends and having at least one second slit. The third end is adjacent to the second end and the fourth end is remote from the second end. The second transistor is disposed between the second end and the third end. The second pattern of the second upper electrode is the same as the first pattern of the first upper electrode according to the Y-axis of the XY coordinate system, and the X-axis of the XY coordinate system corresponds to the extension of the scanning line of the liquid crystal display device. direction.

According to an embodiment of the invention, the at least one first slit of the first pattern and the at least one second slit of the second pattern extend in different directions.

According to an embodiment of the invention, the at least one first slit and the at least one second slit respectively comprise a main slit structure and a pair of slit structures, and the angle between the main slit structure and the liquid crystal arrangement direction is between 5°- Between 12°.

According to an embodiment of the invention, the angle between the sub-slit structure and the liquid crystal arrangement direction is between 30° and 60°.

According to an embodiment of the invention, the pixel structure further includes a first lower electrode and a second lower electrode. The first lower electrode is disposed opposite to the first upper electrode. The second lower electrode is disposed opposite to the second upper electrode.

According to an embodiment of the invention, the first upper electrode and the second upper electrode are common electrodes, and the first lower electrode and the second lower electrode are pixel electrodes.

According to an embodiment of the invention, the first upper electrode and the second upper electrode are pixel electrodes, and the first lower electrode and the second lower electrode are common electrodes.

According to an embodiment of the invention, the first upper electrode and the second upper electrode form a V-shaped structure, and the folded portion of the V-shaped structure corresponds to the second end portion and the third end portion.

Another aspect of the present invention is to provide a liquid crystal display device. The liquid crystal display device includes a plurality of scan lines, a plurality of data lines, and a plurality of first pixels and second pixels. The scan line is used to provide a plurality of scan signals. The data line is used to provide a plurality of data signals, wherein the data lines are arranged across the scan lines to define a plurality of pixel regions. The first pixel and the second pixel are respectively disposed in the pixel region, and a first pixel and a second pixel are combined to form a pixel structure (pixel group). The first pixel includes a first upper electrode and a first transistor. The second pixel includes a second upper electrode and a second transistor. The first upper electrode has a first pattern having opposite first and second ends and having at least one first slit. The first transistor is adjacent to the first end. The second upper electrode has a second pattern having opposite third and fourth ends and having at least one second slit. The third end is adjacent to the second end and the fourth end is remote from the second end. The second transistor is disposed between the second end and the third end. The second pattern of the second upper electrode is the same as the first pattern of the first upper electrode according to the Y-axis of the XY coordinate system, and the X-axis of the XY coordinate system corresponds to the extension of the scanning line of the liquid crystal display device. direction.

According to an embodiment of the invention, the at least one first slit of the first pattern and the at least one second slit of the second pattern extend in different directions.

According to an embodiment of the invention, the at least one first slit and the at least one second slit respectively comprise a main slit structure and a pair of slit structures, and the angle between the main slit structure and the liquid crystal arrangement direction is between 5°- Between 12°.

According to an embodiment of the invention, the angle between the sub-slit structure and the liquid crystal arrangement direction is between 30° and 60°.

According to an embodiment of the invention, the pixel structure further includes a first lower electrode and a second lower electrode. The first lower electrode is disposed opposite to the first upper electrode. The second lower electrode is disposed opposite to the second upper electrode.

According to an embodiment of the invention, the first upper electrode and the second upper electrode are common electrodes, and the first lower electrode and the second lower electrode are pixel electrodes.

According to an embodiment of the invention, the first upper electrode and the second upper electrode are pixel electrodes, and the first lower electrode and the second lower electrode are common electrodes.

According to an embodiment of the invention, the first upper electrode and the second upper electrode form a V-shaped structure, and the folded portion of the V-shaped structure corresponds to the second end portion and the third end portion.

According to an embodiment of the invention, the first transistor and the second transistor are arranged in a zigzag manner.

According to an embodiment of the present invention, one of the first pixels and one of the second pixels are located in the same pixel row, the column of the pixel extends along the extending direction of the data line, and the first pixel One of the first transistors is electrically connected to one of the data lines, and the second transistor of one of the second pixels is electrically connected to the other of the data lines.

According to an embodiment of the invention, the second transistor is disposed on a portion of the first pixel and a portion of the second pixel.

According to an embodiment of the invention, the second transistor is disposed within a range of one of the plurality of scan lines.

According to all embodiments of the present invention, a liquid crystal display device employs a Fringe Field Switching (FFS) architecture and technology.

As can be seen from the above description, the liquid crystal display device of the embodiment of the present invention and its pixel structure include a mirrored electrode structure, so that the generation of dark lines can be avoided.

100‧‧‧Liquid crystal display device

110‧‧‧Sequence Controller

120‧‧‧gate driver

130‧‧‧Source Driver

140, 440‧‧‧ data line

150, 150A, 150B, 150C, 450‧‧‧ scan lines

UEL21, UEL22, UEL41, UEL42‧‧‧ upper electrode

UEL22M‧‧‧ upper electrode mirror pattern

LC1, LC2‧‧‧ liquid crystal molecules

MSL1, MSL2‧‧‧ main slit structure

BEL21a, BEL21b, BEL22a, BEL22b‧‧‧ end

BEL41a, BEL41b, BEL42a, BEL42b‧‧‧ end

UEL21a, UEL21b, UEL22a, UEL22b‧‧‧ end

UEL41a, UEL41b, UEL42a, UEL42b‧‧‧ end

BEL21, BEL22, BEL41, BEL42‧‧‧ lower electrode

PS‧‧‧ pixel group

PX1‧‧‧ first pixel

PX2‧‧‧Second Picture

SL21, SL22, SL41, SL42‧‧‧ slit structure

SSL1, SSL2‧‧‧Second slit structure

T21, T41‧‧‧ first transistor

T22, T42‧‧‧second transistor

T23, T43‧‧‧ third transistor

TH21, TH41‧‧‧ first perforation

TH22, TH42‧‧‧ second perforation

DR21, DR22, DR23, DR41, DR42, DR43‧‧‧ bungee

SO21, SO22, SO23, SO41, SO42, SO43‧‧‧ source

SE21, SE22, SE23, SE41, SE42, SE43‧‧‧ semiconductor layer

For a more complete understanding of the embodiments and the advantages thereof, the following description is made with reference to the accompanying drawings, wherein: FIG. 1 is a schematic view showing the structure of a liquid crystal display device according to an embodiment of the present invention; [FIG. 2A] A schematic top view of a pixel structure (pixel group) according to an embodiment of the present invention; FIG. 2B is a schematic diagram showing a mirror pattern according to an embodiment of the present invention; FIG. 3 is a diagram showing an arrangement direction of liquid crystal molecules corresponding to pixels according to an embodiment of the present invention; FIG. 4 is a schematic top plan view showing a pixel structure (pixel group) according to another embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a liquid crystal display device 100 according to an embodiment of the invention. The liquid crystal display device 100 includes a timing controller 110, a gate driver 120, a source driver 130, a data line 140, a scan line 150, and a pixel group PS. The timing controller 110 is configured to control the gate driver 120 and the source driver 130 to provide a data signal and a scan signal to the data line 140 and the scan line 150, wherein the data signal includes a pixel signal corresponding to each pixel, and the scan The signal contains a transistor switching signal corresponding to each pixel. The data line 140 and the scan line 150 are arranged to cross each other to define a plurality of pixel regions to set pixels.

Each pixel group PS (one pixel structure) contains a first pixel PX1 (half pixel structure) and a second pixel PX2 (half pixel structure), and each pixel group PS The pixel PX1 and the second pixel PX2 are respectively located in the pixel region defined by the data line 140 and the scan line 150, and are electrically connected to the corresponding data line 140 and the scan line 150, and are based on the pixel signal and the scan. The signal operates to cause the liquid crystal display device 100 to display an image. In addition, the arrangement direction of the pixel groups PS can define an X-Y plane on the liquid crystal display device 100. The coordinate system, wherein the vertical arrangement direction of the pixel group PS can be defined as the Y axis, and the horizontal arrangement direction of the pixel group PS can be defined as the X axis.

2A and 2B, FIG. 2A is a schematic top view of a pixel structure (pixel group PS) according to an embodiment of the present invention, wherein the area covered by the first pixel PX1 is represented by FIG. 2A. The lower edge of the scan line 150A is defined by the lower edge of the scan line 150B (ignoring the gate is not seen), and the area covered by the second pixel PX2 is the lower edge of the scan line 150B in FIG. 2A and the scan line 150C. The lower edge is defined (ignoring the gate is not seen), and the first pixel PX1 (half pixel structure) includes a first lower electrode BEL21, a first transistor T21, and a first upper electrode UEL21 (shown by a dotted line) The second pixel PX2 (half pixel structure) includes a second lower electrode BEL22, a second transistor T22, and a second upper electrode UEL22 (shown in broken lines). In this embodiment, the first lower electrode BEL21 and the second lower electrode BEL22 are pixel electrodes, and the first upper electrode UEL21 and the second upper electrode UEL22 are common electrodes, but embodiments of the present invention are not limited thereto. . In other embodiments of the present invention, the first lower electrode BEL21 and the second lower electrode BEL22 are common electrodes, and the first upper electrode UEL21 and the second upper electrode UEL22 are pixel electrodes.

In addition, the first transistor T21 includes a drain DR21, a source SO21, and a semiconductor layer SE21, and is electrically connected to the lower electrode BEL21 through a first via TH21; the second transistor T22 includes a drain DR22 and a source. The electrode SO22 and a semiconductor layer SE22 are electrically connected to the lower electrode BEL22 through a second via TH22; the third transistor T23 (the other pixel group) includes a drain DR23, a source SO23 and a semiconductor layer SE23. And electrically connected to another lower electrode (not shown) through a through hole. In another embodiment The first transistor T21 may also be connected to the first lower electrode BEL21 without the first via TH21. Similarly, the second transistor T22 can be directly connected to the second lower electrode BEL22, and the third transistor T23 can be directly connected to the lower electrode (not shown). In addition, for the sake of clarity of the drawing, the gate of the first transistor T21, the gate of the second transistor T22, and the gate of the third transistor T23 are omitted and are not shown in the drawing.

In the first pixel PX1, the first lower electrode BEL21 has opposite end portions BEL21a and BEL21b, and the first transistor T21 is adjacent to the end portion BEL21b to provide a pixel signal from the corresponding data line 140 to the first pixel. Electrode BEL21. The first upper electrode UEL21 is disposed above the first lower electrode BEL21, and has a first pattern. The first pattern has a first end portion UEL21a and a second end portion UEL21b, respectively corresponding to the first lower electrode BEL21. End BEL21b and BEL21a. In this embodiment, the first pattern includes three first slits SL21, and both ends of the first slit SL21 extend from a position adjacent to the first transistor T21 to a position adjacent to the second transistor T22, respectively. That is, the first slit SL21 extends in the direction of the first transistor T21 to the second transistor T22. However, embodiments of the invention are not limited thereto. In other embodiments of the invention, the first pattern may also include other numbers of first slits, such as two first slits.

Each of the first slits SL21 includes at least one turning portion, and the turning portion may divide the first slit SL21 into a main slit structure MSL1 and at least one slit structure SSL1 bent relative to the main slit structure MSL1, wherein the main slit The length of the slit structure MSL1 is greater than the length of the sub-slit structure SSL1. A liquid crystal layer (not shown) is disposed on the first lower electrode BEL21 and the first upper electrode UEL21. Wherein, in the case where no voltage is applied, the liquid crystal alignment direction is parallel to the Y axis of the XY plane coordinate system, and the angle between the liquid crystal alignment direction and the long axis extension direction of the main slit structure MSL1 is between 5° and 12°. The angle between the liquid crystal alignment direction and the extending direction of the bent sub-slit structure SSL1 is between 30° and 60°. In this embodiment, the liquid crystal alignment can be aligned by illuminating or mechanically aligning the liquid crystal after forming a rubbing direction of the polyimide layer.

In the second pixel PX2, the second lower electrode BEL22 has opposite end portions BEL22a and BEL22b, wherein the end portion BEL22a is close to the end portion BEL21a of the first lower electrode BEL21, and the end portion BEL22b is away from the end of the first lower electrode BEL21. Department BEL21a. The second upper electrode UEL22 is correspondingly disposed above the second lower electrode BEL22, and has a second pattern different from the first pattern of the first upper electrode UEL21, the second pattern having a third end UEL22a And the fourth end portion UEL22b corresponds to the end portions BEL22a and BEL22b of the second lower electrode BEL22, respectively. As such, the second transistor T22 is located between the second end portion UEL21b of the first pattern and the third end portion UEL22a of the second pattern, and also corresponds to the end portion BEL22a of the second lower electrode BEL22 and the first lower electrode BEL21. Between the ends BEL21a. In this embodiment, the second upper electrode UEL22 and the first upper electrode UEL21 are formed by a part of the patterned common electrode, but the embodiment of the present invention is not limited thereto, and in other embodiments. It can also be part of a patterned pixel electrode. In the manufacturing process of the common electrode of the present embodiment, a common electrode having a large area is first formed, and then patterned, and defined as a plurality of patterned common electrode portions having a small area, wherein these are small The patterned common electrode portions of the area are still electrically connected to each other. In addition, in this embodiment, the second pattern includes three second slits SL22, and two ends of the second slit SL22 extend from a position adjacent to the second transistor T22 to adjacent to the third transistor T23, respectively. The position, that is, the second slit SL22 extends in the direction of the second to third transistors T22 to T23. However, embodiments of the invention are not limited thereto. In other embodiments of the invention, the second pattern may also include other numbers of second slits, such as two second slits.

Each of the second slits SL22 includes at least one turning portion, and the turning portion divides the slit second SL22 into a main slit structure MSL2 and at least one sub-slit structure SSL2, wherein the length of the main slit structure MSL2 is larger than the sub-narrow The seam structure is SSL2. Wherein, the angle between the liquid crystal arrangement direction (Y direction) and the main slit structure MSL2 is between 5° and 12° (the angle between the Y direction and the long axis direction of the main slit), and the liquid crystal arrangement direction and the sub slit The angle of the structure SSL2 is between 30° and 60° (the angle between the Y direction and the direction in which the sub slit extends).

It is worth mentioning that after the pattern (second pattern) of the second upper electrode UEL22 is mirrored on the Y axis, the pattern shape thereof is the same as the pattern (first pattern) of the first upper electrode UEL21. As shown in FIG. 2B, the second pattern of the second upper electrode UEL22 is the same as the first pattern of the first upper electrode UEL21 generated by the Y-axis of the XY coordinate system (Cartesian coordinate system), wherein the XY The X-axis of the coordinate system corresponds to the direction in which the scan line 150 extends. In other words, the first pattern of the first upper electrode UEL21 is also generated in the same mirror pattern as the second pattern of the second upper electrode UEL22 according to the Y-axis of the X-Y coordinate system. In addition, the second transistor T22 of this embodiment The included drain electrode DR22, the source SO22, and the semiconductor layer SE22 are simultaneously disposed in a region covered by part of the first pixel PX1 and a portion covered by the second pixel PX2, but the present invention Not limited to this. In other words, a portion of the second transistor T22 is located in the region where the first pixel PX1 is located, and another portion is located in the region where the second pixel PX2 is located.

Please refer to FIG. 3. FIG. 3 is a diagram showing the arrangement direction of the liquid crystal molecules corresponding to the pixels according to the embodiment of the present invention subjected to an electric field (in the case of applying a voltage to the upper and lower electrodes), wherein the pixel PX1 corresponds to the liquid crystal molecule LC1. And the pixel PX2 corresponds to the liquid crystal molecule LC2. As shown in FIG. 3, when an electric field is applied to the liquid crystal molecules of the pixels, the alignment direction of the liquid crystal molecules is affected by the electric field to exhibit a complementary state. For example, the arrangement direction of the liquid crystal molecules LC1 of the pixel PX1 is from the lower left to the upper right, and the alignment direction of the liquid crystal molecules LC2 of the pixel PX2 is from the upper left to the lower right, so that after the application of the electric field, the liquid crystal alignment direction of the pixel PX1 is drawn. The alignment of the liquid crystals of the PX2 is complementary.

Referring back to FIG. 2A, in the embodiment, the first upper electrode UEL21 of the first pixel PX1 and the second upper electrode UEL22 of the second pixel PX2 form a V-shaped structure, and the turning portion of the V-shaped structure is Located at the first upper electrode end UEL21b and the second upper electrode end UEL22a.

As apparent from the above description, the pixel group PS of the liquid crystal display device 100 of the embodiment of the present invention includes two pixels PX1 and PX2 having complementary domains. By using such a pixel corresponding to a pixel structure of a domain, the complementarity of visual effects can be achieved.

In addition, in the embodiment of the present invention, the electro-crystal system of each pixel is arranged in a zigzag manner, so that it is easier to use space. Design the electrode pattern. For example, for the pixel PX1, the first transistor T21 and the second transistor T22 are arranged diagonally, and the first slit SL21 of the first pattern may be in the first transistor T21 to the second transistor T22. Extend in the direction. For another example, for the pixel PX2, the second transistor T22 and the third transistor T23 are arranged diagonally, and the second slit SL22 of the second pattern is available in the second transistor T22 to the third transistor. Extends in the direction of T23. The third transistor T23 is a transistor of a pixel of another pixel group (for example, a third pixel).

In the same pixel row, each pixel is arranged in the vertical direction (ie, the direction in which the data line extends), in other words, the pixel line extends along the direction in which the data line extends. Since the crystals of each pixel are arranged in a zigzag manner, the transistors of two upper and lower adjacent pixels in the same pixel row are respectively connected to different data lines, and the driving mode is also Z word. The way to drive. For example, the data line to which the first transistor T21 of the first pixel PX1 is connected is different from the data line to which the second transistor T22 of the second pixel PX2 is connected. Referring to FIG. 2A, the first transistor T21 is connected to the data line 140 adjacent to the first transistor T21, and the second transistor T22 is connected to another data line 140 adjacent to the second transistor T22. The first transistor T21 and the second transistor T22 in the same pixel row are respectively connected to different data lines 140. The third transistor T23 is connected to the data line 140 adjacent to the first transistor T21, and is connected to the same data line 140 as the first transistor T21.

Please refer to FIG. 4. FIG. 4 is a schematic top plan view of a pixel structure (pixel group PS) according to another embodiment of the present invention, as shown in FIG. 2A. For example, the area covered by each pixel is defined by the distance between the lower edges of two adjacent scan lines 450. The first pixel PX1 includes a first lower electrode BEL41, a first transistor T41, and A first upper electrode UEL41 (shown in phantom), the second pixel PX2 includes a second lower electrode BEL42, a second transistor T42, and a second upper electrode UEL42 (shown in dashed lines). In this embodiment, the first lower electrode BEL41 and the second lower electrode BEL42 are pixel electrodes, and the first upper electrode UEL41 and the second upper electrode UEL42 are common electrodes, but the embodiment of the present invention is not limited thereto. . In other embodiments of the present invention, the first lower electrode BEL41 and the second lower electrode BEL42 are common electrodes, and the first upper electrode UEL41 and the second upper electrode UEL42 are pixel electrodes.

In addition, the first transistor T41 includes a drain DR41, a source SO41, and a semiconductor layer SE41, and is electrically connected to the lower electrode BEL41 through a first through hole TH41. The second transistor T42 includes a drain DR42 and a source. a pole SO42 and a semiconductor layer SE42 are electrically connected to the lower electrode BEL42 through a second through hole TH42. The third transistor T43 (the other pixel group) includes a drain electrode DR43, a source SO43, and a semiconductor layer SE43. And electrically connected to another lower electrode (not shown) through a through hole. In another embodiment, the first transistor T41 may also be connected to the lower electrode BEL41 without the first through hole TH41. Similarly, the second transistor T42 can be directly connected to the lower electrode BEL42, and the third transistor T43 can be directly connected to the other lower electrode.

It is worth mentioning that the second transistor T42 can be disposed at least one of a region covered by the first pixel PX1 or a region covered by the second pixel PX2. For example, in the embodiment of FIG. 2A, the second transistor T22 is the same The time is in the area covered by the pixels PX1 and PX2. Compared with the embodiment of FIG. 2A, the electro-crystal system of the present embodiment is disposed in a region covered by one pixel. For example, the drain electrode DR42, the source electrode SO42, and the semiconductor layer SE42 included in the second transistor T42 are disposed only in a region covered by the second pixel PX2, and the first transistor T41 is disposed only in the first pixel PX1. Within the covered area. In other words, the second transistor T42 may be disposed at least one of a region covered by the first pixel PX1 or a region covered by the second pixel PX2. As with the previous embodiment, the area covered by the first pixel PX1 is defined by the lower edge of any of the scan lines 450 of FIG. 4 to the lower edge of another adjacent scan line 450 (ignoring the gate not to be seen).

In the first pixel PX1, the first lower electrode BEL41 has opposite end portions BEL41a and BEL41b, and the first transistor T41 is adjacent to the end portion BEL41b to provide a pixel signal from the corresponding data line 440 to the first pixel. Electrode BEL41. The first upper electrode UEL41 is disposed above the first lower electrode BEL41, and has a first pattern. The first pattern has a first end portion UEL41a and a second end portion UEL41b corresponding to the first lower electrode BEL41. End BEL41b and BEL41a. In this embodiment, the first pattern includes three first slits SL41, and both ends of the first slit SL41 extend from a position adjacent to the first transistor T41 to a position adjacent to the second transistor T42, respectively. That is, the first slit SL41 extends in the direction of the first transistor T41 to the second transistor T42. However, embodiments of the invention are not limited thereto. In other embodiments of the invention, the first pattern may also include other numbers of first slits, such as two first slits.

In the second pixel PX2, the second lower electrode BEL42 has opposite end portions BEL42a and BEL42b, wherein the end portion BEL42a is close to the end portion BEL41a of the first pixel electrode BEL41, and the end portion BEL42b is away from the first lower electrode BEL41. End BEL41a. As such, the second transistor T42 provides the pixel signal from the corresponding data line 440 to the second lower electrode BEL42. The second upper electrode UEL42 is disposed above the second lower electrode BEL42 and has a second pattern. The second pattern has a third end portion UEL42a and a fourth end portion UEL42b corresponding to the first lower electrode BEL42. The ends BEL41a and BEL41b, wherein the second pattern of the second upper electrode UEL42 is different from the first pattern of the first upper electrode UEL41. The second transistor T42 is located between the second end portion UEL41b of the first upper electrode UEL41 and the third end portion UEL42a of the second upper electrode UEL42. In this embodiment, the second upper electrode UEL42 and the first upper electrode UEL41 are formed by a part of the patterned common electrode, but the embodiment of the present invention is not limited thereto, and in other embodiments. It can also be part of a patterned pixel electrode. In the manufacturing process of the common electrode of the present embodiment, a common electrode having a large area is first formed, and then patterned, and defined as a plurality of patterned common electrode portions having a small area, wherein these are small The patterned common electrode portions of the area are still electrically connected to each other. In addition, in the embodiment, the second pattern includes three second slits SL42, and two ends of the second slit SL42 extend from a position adjacent to the second transistor T42 to adjacent to the third transistor T43, respectively. The position, that is, the second slit SL42 extends in the direction of the second transistor T42 to the third transistor T43. However, embodiments of the invention are not limited thereto. In the present invention In other embodiments, the second pattern may also include other numbers of second slits, such as two second slits.

As in the previous embodiment, each of the first slits SL41 includes at least one turning portion, and the turning portion may divide the first slit SL41 into a main slit structure and at least one pair of slits bent relative to the main slit structure. The structure wherein the length of the main slit structure is greater than the length of the sub-slit structure. A liquid crystal layer (not shown) is disposed on the first lower electrode BEL41 and the first upper electrode UEL41. Wherein, in the case where no voltage is applied, the liquid crystal alignment direction is parallel to the Y axis of the XY plane coordinate system, and the angle between the liquid crystal alignment direction and the long axis extension direction of the main slit structure is between 5° and 12°. The angle between the alignment direction of the liquid crystal and the extending direction of the bent sub-slit structure is between 30° and 60°. Also in the present embodiment, in the present embodiment, the liquid crystal alignment can be aligned by illuminating or mechanically aligning the liquid crystal after forming a rubbing direction of the polyimide layer.

Similar to the previous embodiment, after the second pattern of the second upper electrode UEL42 of the present embodiment is mirrored on the Y-axis, the pattern shape thereof is the same as the first pattern of the first upper electrode UEL41. In other words, the shape of the mirror pattern generated by the first pattern of the first upper electrode UEL41 according to the Y-axis of the X-Y coordinate system is also the same as the second pattern of the second upper electrode UEL42.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

Claims (20)

A pixel structure of a liquid crystal display device, comprising: a first upper electrode having a first pattern, the first pattern having a first end and a second end, wherein the first pattern has at least one a first slit; a first transistor adjacent to the first end; a second upper electrode having a second pattern, the second pattern having a third end and a fourth end The second pattern has at least one second slit, the third end being adjacent to the second end of the first upper electrode, the fourth end being away from the second end of the first upper electrode; And a second transistor is disposed between the second end portion and the third end portion; wherein the second pattern of the second upper electrode generates a mirror pattern according to a Y-axis of an XY coordinate system The first pattern of the first upper electrode is the same, and the X-axis of the XY coordinate system corresponds to an extending direction of one of the scanning lines of the liquid crystal display device. The pixel structure of the liquid crystal display device of claim 1, wherein the at least one first slit of the first pattern and the at least one second slit of the second pattern extend in different directions. The pixel structure of the liquid crystal display device of claim 2, wherein the at least one first slit and the at least one second slit respectively comprise a main slit structure and at least one bent relative to the main slit structure The sub-slit structure has an angle between a long axis extending direction of the main slit structure and a liquid crystal alignment direction of between 5° and 12°. The pixel structure of the liquid crystal display device of claim 3, wherein an angle between the extending direction of the bent at least one pair of slit structures and the liquid crystal alignment direction is between 30° and 60°. The pixel structure of the liquid crystal display device of claim 1, further comprising: a first lower electrode disposed opposite to the first upper electrode; and a second lower electrode disposed opposite the second upper electrode. The pixel structure of the liquid crystal display device of claim 5, wherein the first upper electrode and the second upper electrode are common electrodes, and the first lower electrode and the second lower electrode are pixel electrodes. The pixel structure of the liquid crystal display device of claim 5, wherein the first upper electrode and the second upper electrode are pixel electrodes, and the first lower electrode and the second lower electrode are common electrodes. The pixel structure of the liquid crystal display device of claim 6 or 7, wherein the first upper electrode and the second upper electrode form a V-shaped structure, and the folded portion of the V-shaped structure corresponds to the second end portion and The third end. A liquid crystal display device comprising: a plurality of scan lines for providing a plurality of scan signals; a plurality of data lines for providing a plurality of data signals, wherein the data lines are disposed to intersect with the scan lines to define a plurality of pixel regions; and a plurality of first pixels and a plurality of second pixels, Separatingly disposed in the pixel regions, wherein each of the first pixels comprises: a first upper electrode having a first pattern, the first pattern having a first end and a second end The first pattern has at least one first slit; and a first transistor adjacent to the first end; each of the second pixels comprises: a second upper electrode having a first a second pattern having a third end portion and a fourth end portion, wherein the second pattern has at least one second slit adjacent to the second portion of the first upper electrode An end portion, the fourth end portion is away from the second end portion of the first upper electrode; and a second transistor disposed between the second end portion and the third end portion; wherein the second upper portion a second pattern of the electrode is generated according to a Y-axis of an XY coordinate system The first pattern of the first upper electrode is the same, and the X-axis of the X-Y coordinate system corresponds to the extending direction of the scan lines. The liquid crystal display device of claim 9, wherein the at least one first slit of the first pattern and the at least one second slit of the second pattern extend in different directions. The liquid crystal display device of claim 10, wherein the at least one first slit and the at least one second slit respectively comprise a main slit structure and at least one slit structure bent relative to the main slit structure The longitudinal direction of the main slit structure extends at an angle of between 5° and 12° with respect to a liquid crystal alignment direction. The liquid crystal display device of claim 11, wherein an angle between the extending direction of the bent at least one pair of slit structures and the liquid crystal alignment direction is between 30° and 60°. The liquid crystal display device of claim 9, further comprising: a first lower electrode disposed opposite to the first upper electrode; and a second lower electrode disposed opposite the second upper electrode. The liquid crystal display device of claim 13, wherein the first upper electrode and the second upper electrode are common electrodes, and the first lower electrode and the second lower electrode are pixel electrodes. The liquid crystal display device of claim 13, wherein the first upper electrode and the second upper electrode are pixel electrodes, and the first lower electrode and the second lower electrode are common electrodes. The liquid crystal display device of claim 14 or 15, wherein the first upper electrode and the second upper electrode form a V-shaped structure, The turning portion of the V-shaped structure corresponds to the second end portion and the third end portion. The liquid crystal display device of claim 9, wherein the first transistors and the second transistors are arranged in a zigzag manner. The liquid crystal display device of claim 9, wherein one of the first pixels is located in the same pixel row as one of the second pixels, and the pixel is along the data lines. Extending the direction to extend, and the first transistor of the one of the first pixels is electrically connected to one of the data lines, and the second transistor of the second pixel and the data line The other one is electrically connected. The liquid crystal display device of claim 9, wherein the second transistor is located in at least one of an area covered by the first pixel or an area covered by the second pixel. The liquid crystal display device of claim 9, wherein the second transistor is located in a region covered by the first pixel and a portion covered by the second pixel.