TWI628663B - Current sensing circuit for memory and sensing method thereof - Google Patents

Abstract

Current sensing circuit and sensing method of memory. The current sensing circuit includes a precharge circuit, a sense current to voltage generator, an auxiliary current to voltage generator, a reference current to voltage generator, and a detection circuit. The precharge circuit provides a precharge signal to the selected bit line during the precharge time interval. The sense current to voltage generator generates a sense voltage by transmitting a memory cell current of the selected bit line through the first load. The auxiliary current-to-voltage generator provides a detection voltage to a portion of the memory cell current of the selected bit line through the second load during the pre-charge time interval. The reference current to voltage generator provides a reference voltage during the data sensing time interval. The detecting circuit determines the stop time point of the pre-charging time interval according to the detected voltage generated by the second load and the reference voltage.

Description

Memory current sensing circuit and sensing method

The present invention relates to a sensing circuit and a sensing method for a memory, and more particularly to a sensing circuit and a sensing method for a memory that can dynamically adjust a precharge time length.

In flash memory, the data stored in the flash memory cell is set by stylized and erased actions. Among them, the stylization and erasing actions can change the threshold voltage of the flash memory cells. In the data reading operation, the conventional technique often obtains the data stored by the flash memory cells by detecting the magnitude of the current flowing through the flash memory cells.

It is worth mentioning that in order to speed up the reading of data, especially in the design of high-density and low-voltage flash memory cells, conventional techniques often reduce the length of time required for sensing time intervals through a pre-charging mechanism. However, the pre-charging mechanism applied in the prior art is often performed by a fixed-length pre-charging time interval or a fixed-intensity pre-charging signal. When overcharging occurs, the sensing time interval is required. The inverse effect of increasing the length of time reduces the overall performance of the memory.

The invention provides a sensing circuit and a sensing method for a memory, which effectively speed up the sensing speed of the read data.

The sensing circuit of the memory of the present invention includes a precharge circuit, a sense current to voltage generator and its switch, an auxiliary current to voltage generator and its switch, a reference current to voltage generator and its switch, and a detection circuit. The precharge circuit can be coupled to the selected bit line of the read memory cell via the same type of current to voltage generator to provide a precharge signal to the selected bit line in the precharge time interval. The sensing current-to-voltage generator switch is turned on in the data sensing time interval, and the sensing current-to-voltage generator output is coupled to the memory cell current of the selected bit line, and generates a sensing voltage through the first load. The auxiliary current to voltage generator switch is turned on in the precharge time interval, the auxiliary current to voltage generator output is coupled to a portion of the memory current of the selected bit line, and the auxiliary sense voltage is supplied through the second load. The reference current-to-voltage generator switch is turned on in the data sensing time interval, and the reference current-to-voltage generator output is coupled to the reference memory cell current of the reference bit line, and generates a reference voltage through the reference load. The detecting circuit is coupled to the second load, and the detected time of the pre-charge time interval is determined according to the detected voltage generated by the second load and the reference voltage generated by the reference load.

The sensing method of the memory of the present invention comprises: starting a pre-charging time interval in a data sensing time interval; providing a pre-charging current to a coupled memory cell via a current-turning voltage generator in a pre-charging time interval a bit line; in the precharge time interval, the auxiliary current to voltage generator is simultaneously coupled to the selected bit line, and the detected voltage is supplied through the second load by reading a part of the current of the memory cell; and, according to the comparison The detected voltage generated by the second load is compared with the reference voltage to determine the stop time point of the precharge time interval; in the data sensing time interval, the sense current turn voltage generator switch is activated, and the sense current turn voltage generator is activated. The output is coupled to the memory cell current of the selected bit line, and the sensing voltage is supplied through the first load by reading the memory cell current.

Based on the above, the sensing circuit and the sensing method of the memory provided by the present invention are simultaneously coupled to the selected bit line by using the same type of auxiliary current-to-voltage generator, and a part of the current of the memory cell is read and transmitted through the same. The second load provides a detected voltage, and compares the detected voltage on the second load with the reference voltage to determine a stop time point of the precharge time interval. Therefore, the sensing circuit and the sensing method of the memory provided by the present invention can effectively speed up the sensing speed of the read data and improve the working efficiency of the memory by providing a dynamically adjusted pre-charging mechanism.

The above described features and advantages of the invention will be apparent from the following description.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a sensing circuit of a memory according to an embodiment of the invention. The sensing circuit 100 includes a pre-charging circuit 110, a sensing current-to-voltage generator and switch 120, an auxiliary current-to-voltage generator and switch 130, a reference current-to-voltage generator and switch 135, a detection circuit 140, and a current-to-voltage generation The set 150 includes a sense current to voltage generator 150A, an auxiliary current to voltage switch generator 150B, and a current to voltage generator 150C of a precharge path, a reference current to voltage generator 150R, and a main sense amplifier 160. The pre-charging circuit 110 is coupled to the selected bit line SBL of the read memory cell MC1 via the same type of current-to-voltage generator 150C, and provides a pre-charging current to the selected bit line in the pre-charging time interval according to the signal EN1. SBL, here the signal EN1 is generated in accordance with the precharge enable signal PCEN. The sensing current generator and the switch 120 are activated according to the sensing enable signal SEN, and are coupled to the selected bit line SBL through the sensing current converting voltage generator 150A in the data sensing time interval to provide the sensing current IS1 to the first The load L1 is generated to generate the sensing voltage VC1. The auxiliary current generator and the switch 130 are coupled to the selected bit line SBL through the auxiliary current turning voltage generator 150B according to the signal EN1 in the pre-charging time interval, and provide the auxiliary sensing current IS2 to the second load L2 to generate the detected Measure the voltage VC2. The detecting circuit 140 is coupled to the detecting load L2, and determines the pre-charging according to the detected voltage VC2 and the reference voltage Vr generated by comparing the detected load L2 and the partial current of the read memory cell of the selected bit line SBL. The time point of the time interval. The detecting circuit 140 generates the pre-charge disable signal PCEN according to the compared detected voltage VC2 and the reference voltage Vr. Wherein, when the detected voltage VC2 is less than the reference voltage Vr, the detecting circuit 140 can enable the pre-charge enable signal PCEN to be enabled (at a first logic level) and cause the pre-charge circuit 110 to provide a pre-charge signal. The pre-charge operation is performed on the selected bit line SBL. Moreover, when the detected voltage VC2 rises to be equal to or slightly smaller than the reference voltage Vr, the detecting circuit 140 disables the pre-charge enable signal PCEN (which is a second logic level complementary to the first logic level), The precharge circuit 110 is then stopped from providing a precharge signal to precharge the selected bit line SBL. The main sense amplifier 160 is coupled to the sensing load L1, receives the voltage VC1 on the sensing load L1 and the reference voltage Vr, and generates the read data DOUT according to the comparison voltage VC1 and the reference voltage Vr, and the sensing is provided in the final stage. The current IS1 to the sense voltage L1 generated by the sense load L1.

The reference current-to-voltage generator switch 135 provides the reference current ISR of the reference memory cell RMC1 on the reference bit line RBL in the data sensing time interval by the transmissive current-turning voltage generator group 150R, and thereby generates the reference voltage LR and the current-to-voltage voltage. A reference voltage Vr is generated at an end coupled to the set 150R. The current to voltage generator 150R provides a reference memory cell RMC1 current to the reference load LR to generate a reference voltage Vr.

The sense current turn voltage generator 150A, the auxiliary current turn voltage generator 150B, and the reference current turn voltage generator 150C in the current turn voltage generator group 150 are respectively coupled to the sense load L1, the detection load L2, and the precharge circuit. The path between the 110 and the selected bit line SBL is used to convert the current signal on the path into a voltage signal. In addition, using the same type of current-to-voltage generator will ensure that the sensing current IS1 is equal to the pre-charge time interval. The auxiliary sense current IS2 is connected to the charge precharge current, and the sum of the three currents comes from reading the memory cell MC1 current.

In the overall action details, at the beginning of the data sensing time interval, the sensing circuit 100 enters the pre-charging time interval and causes the pre-charging circuit 110 to provide a pre-charging signal to the selected bit line SBL in accordance with the signal EN1. At the same time, the auxiliary current to voltage generator 150B and the sensing current to voltage generator 150A respectively provide the auxiliary sensing current IS2 and the sensing current IS1, and respectively enable the auxiliary sensing current IS2 and the sensing current IS1 and respectively pass the detection. The load L2 and the sensing load L1, wherein the sensing current IS1, the auxiliary sensing current IS2, and the pre-charging current are the currents ISBL of the read memory cell MC1 flowing to the selected bit line.

Through the current-to-voltage generator 150B, the detecting circuit 140 receives the reference voltage Vr and detects the detected voltage VC2 on the load L2. The detecting circuit 140 generates a pre-charge enable signal PCEN by comparing the voltage difference between the detected voltage VC2 and the reference voltage Vr, wherein the detecting circuit 140 can generate the enabled pre-charging at the beginning of the data sensing time interval. The signal PCEN is activated, and when the voltage value of the detected voltage VC2 rises to a voltage value equal to or slightly smaller than the reference voltage Vr, the detecting circuit 140 can generate the disabled pre-charge enable signal PCEN. Wherein, when the precharge enable signal PCEN is enabled, the precharge circuit 110 starts and continues to provide the precharge current, and when the precharge enable signal PCEN is disabled, the precharge circuit 110 stops providing the precharge current and enables the precharge The time interval is aborted.

Please note that in this embodiment, the impedance value of the detection load L2 is equal to the reference load LR multiplied by a ratio, which is determined by the ratio of the auxiliary sense current IS2 to the read memory cell MC1 current. That is to say, when passing through the current-to-voltage generator of the same hardware structure, the auxiliary sensing current IS2 is equivalent to the sensing current IS1 and the pre-charging current, and in the pre-charging time interval, all are reading the memory cell MC1 current ISBL. In one step, the impedance value of the detected load L2 is thus three times or slightly less than three times the impedance value of the reference load LR. Based on this, the sensing circuit 100 can control the pre-charging operation performed by the pre-charging circuit 110 to stop when the voltage value on the selected bit line SBL is precharged to a voltage value approximately equal to the reference voltage Vr, thereby effectively preventing pre-charging. Overcharge occurs.

It is worth mentioning that, according to the preset ratio between the impedance value of the detected load L2 and the preset reference load LR, the voltage value of the detected voltage VC2 is equal to or slightly smaller than the voltage value of the reference voltage Vr at the same time point. . In this way, the precharge operation can be terminated early, and the precharge overcharge phenomenon is ensured.

Please refer to FIG. 2A. FIG. 2A is a schematic diagram of a sensing circuit according to another embodiment of the present invention. The sensing circuit 200 includes a precharge circuit 210, a sense current to voltage generator switch 220, an auxiliary current to voltage generator switch 230, a detection circuit 240, a current to voltage generator group 250, a main sense amplifier 260, and a reference current. Turn voltage generator switch 270.

In this embodiment, the precharge circuit 210 is coupled to the power supply terminal VP through a switch formed by the transistor M1. Wherein, the transistor M1 is controlled by the signal EN1 to be turned on or off, and controls the activation of the precharge circuit 210. The precharge circuit 210 can be a current source and, when the transistor M1 is turned on, provides a precharge current of the current signal to the selected bit line SBL through the current to voltage generator group 250. In addition, the sense current to voltage generator and switch 220, the auxiliary current to voltage generator and switch 230, and the reference current to voltage generator and switch 270 are respectively formed by transistors M3, M2, and M4. Wherein, the transistor M2 is controlled by the signal EN1 to provide the auxiliary sensing current IS2 through the current to voltage generator group 250. The transistors M3 and M4 are controlled by the reverse signal of the sensing enable signal SEN to provide the sensing current IS1 and the reference current ISR to the sensing load L1 and the detecting load L2 through the current converting voltage generator group 250, respectively. A sensing voltage VC1 and a detected voltage VC2 are generated. Wherein, the inverter IV1 receives the sensing enable signal SEN and generates an inverted signal of the sensing enable signal SEN.

On the other hand, the reference current-to-voltage generator and the switch 270 of the embodiment are activated in the data sensing time interval, and the reference current-to-voltage generator and the switch 270 are provided through the current-to-voltage converter group 250 to provide the reference memory cell RMC1. The current ISR is applied to the reference load LR to generate a reference voltage Vr. The main sense amplifier 260 receives the reference voltage Vr and the sensing voltage VC1, and transmits the detection result by the voltage difference between the reference voltage Vr and the sensing voltage VC1 after the pre-charging time interval ends.

In the present embodiment, the detection circuit 240 includes an auxiliary sense amplifier SA2 and a latch LA1. The auxiliary sense amplifier SA2 receives the reference voltage Vr and the detected voltage VC2, and generates a detection result by sensing the voltage difference between the reference voltage Vr and the detected voltage VC2. The latch LA1 is coupled to the output of the auxiliary sense amplifier SA2, and generates a precharge enable signal PCEN according to the detection result of the auxiliary sense amplifier SA2.

In terms of motion details, the latch LA1 receives the detection result of the auxiliary sense amplifier SA2 and receives the sensing enable signal SEN. At an initial time point when the sensing time interval is activated, the latch LA1 can enable the pre-charge enable signal PCEN according to the sense enable signal SEN at which the transition occurs, and thereby initiate the pre-charge time interval. Moreover, when the detection result of the auxiliary sense amplifier SA2 indicates that the voltage value of the detected voltage VC2 is not less than the voltage value of the reference voltage Vr, the latch LA1 can be disabled according to the detection result of the auxiliary sense amplifier SA2. The start signal PCEN is charged and the precharge time interval is aborted. In the embodiment of the present invention, the latch LA1 may be an SR type latch, and the hardware structure of the auxiliary sense amplifier SA2 may be the same as the hardware structure of the main sense amplifier 260.

In the present embodiment, the current to voltage generator group 250 includes a plurality of transistors M5 to M7. The transistor M5 is connected in series between the detection load L2 and the selected bit line SBL; the transistor M6 is connected in series between the sensing load L1 and the selected bit line SBL; and the transistor M7 is connected in series with the reference load LR and reference bit line RBL. The transistors M5 to M7 are both controlled by the bias voltage VB for the current to voltage conversion operation. Each group of current-to-voltage generators has the same hardware structure, that is, transistors M5 to M7 are transistors of the same size and the same size. Among them, the current-to-voltage generator controlled by a bias voltage transistor is only an illustrative example, and the current-to-voltage generator of other circuit architectures can also achieve the operation of the pre-charging circuit sensing circuit. It should be noted that the pre-charge circuit 210 in this embodiment can connect two equal parts (precharge circuit group pairs formed by the pre-charge circuits 210A and 210B) to the connection points of the sensing load L1 and the transistor M6, respectively. The connection point of the load L2 and the transistor M5 is detected, and the precharge current is averaged through the transistors M6 and M5, and is supplied to the selected bit line SBL, so that the sensing current IS1 and the auxiliary sense are maintained in the precharge time interval. The measured current IS2 is consistent, and the ratio of the auxiliary sense current IS2 to the read memory cell MC1 current has been determined.

In addition, the selected memory cell MC1 and the reference memory cell RMC1 in this embodiment may have the same hardware architecture, wherein the selected memory cell MC1 is controlled by the column address control signal ColC and the character address signal WLC, The memory cell RMC1 is controlled by the reference column control signal ColR and the reference word signal WLref. The selected memory cell MC1 and the reference memory cell RMC1 may all be flash memory cells.

Please refer to FIG. 2B. FIG. 2B is a schematic diagram of another embodiment of the sensing circuit of the embodiment of FIG. 2A of the present invention. Different from the embodiment shown in FIG. 2A, in FIG. 2B, the precharge circuit 210 is coupled to the selected bit line SBL through the independent transistor M8, and transmits the precharge current through the transistor M8 to the selected state. Bit line SBL. The transistor M8 is also controlled by the bias voltage VB and is used to perform a current-to-voltage conversion operation such that the charging current is substantially the same as the current flowing through the other current-to-voltage converters.

Please refer to FIG. 3. FIG. 3 is a schematic diagram showing a manner of generating the signal EN1 according to an embodiment of the present invention. The signal EN1 can be generated by the logic operation circuit ND1 and the pulse wave generator 310. The pulse generator 310 receives the sensing enable signal SEN and generates a fixed interval pulse signal according to the sensing enable signal SEN in the data sensing time interval. The logic operation circuit ND1 receives the pulse wave signal generated by the pulse wave generator 310, the sensing enable signal SEN, and the precharge enable signal PCEN, and generates a pulse wave signal and a sensing enable signal generated by the pulse wave generator 310. The SEN and the precharge enable signal PCEN perform a logical operation opposite to (NAND) to generate the signal EN1. The signal EN1 is used to initiate the pre-charging action of the sensing circuit of the embodiment of the present invention.

It should be noted here that the logical operation of the NAND circuit through the logic operation circuit ND1 is merely an illustrative example and is not intended to limit the scope of the present invention. In fact, other operational forms of logic operations can also be applied in embodiments of the invention to generate signal EN1 without fixed limits. For example, when the pre-charging action of the sensing circuit can be enabled when the signal EN1 is at a logic high level, a logic operation circuit that performs an AND logic operation can be applied to generate the signal EN1. Or, when the enabled logic level of the pulse wave signal, the sensing enable signal SEN, and the precharge enable signal PCEN generated by the pulse wave generator 310 is changed, logic for performing other kinds of logic operations may be applied. The arithmetic circuit generates a signal EN1.

Referring to FIG. 4, FIG. 4 is a flow chart showing a sensing manner of a memory according to an embodiment of the present invention. Step S410 starts a pre-charge time interval in the data sensing time interval, wherein the start pre-charge time interval is initiated at an initial time point of the data sensing time interval. Next, in step S420, a precharge current is supplied to the selected bit line coupled to the read memory cell in the precharge time interval, and the current transduction voltage is transmitted in the data sensing time interval in steps S430 and S440, respectively. The converter is coupled to the selected bit line to provide a sense current to the first load, and is coupled to the reference bit line through the same type of current to voltage converter, providing a reference current to the reference load, and in the precharge time interval The same type of current to voltage converter is simultaneously coupled to the selected bit line to provide auxiliary sense current to the second load. In step S450, the stop time point of the precharge time interval is determined according to comparing the detected voltage and the reference voltage on the second load and the selected bit line coupling point. Finally, in step S460, after the pre-charge time interval is suspended, the auxiliary sensing current is simultaneously turned off. The readout data is generated based on the relationship between the current of the read memory cell, the sense voltage generated to the first load, and the reference voltage. At this time, the memory cell current is read, and the read voltage is generated by the voltage difference between the sensing voltage and the reference voltage provided by the first load.

Regarding the implementation details of the above steps, the foregoing embodiments and implementations have been described in detail, and will not be further described herein.

In summary, in the precharge time interval, the present invention provides an auxiliary sense voltage by simultaneously coupling the auxiliary current and the detected load of the selected bit line through the current voltage generator, that is, the detected voltage, and It is determined whether to stop the pre-charging action by detecting the difference between the detected voltage on the load and the reference voltage. As such, the precharge action can be stopped when the selected bit line is precharged to a voltage level equal to (or slightly below) the reference voltage. Precharge overcharge can be avoided and the memory read rate can be increased.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ sensing circuit
110, 210, 210A, 210B‧‧‧ Precharge circuits
120, 220‧‧‧Sense current to voltage generator and switch
130, 230‧‧‧Auxiliary current to voltage generator and switch
135‧‧‧Reference current to voltage generator and switch
140, 240‧‧‧Detection circuit
150, 250‧‧‧current to voltage generator group
150A‧‧‧Sensing current to voltage generator
150B‧‧‧Auxiliary current to voltage generator
150C‧‧‧Reference current to voltage generator
160, 260‧‧‧ main sense amplifier
270‧‧‧Reference current to voltage generator and switch
MC1‧‧‧Read memory cells
SBL‧‧‧Selected bit line
IS1‧‧‧Sense current
L1, L2, LR‧‧‧ first load (sensing), second load (detection), reference load
IS2‧‧‧Auxiliary sensing current
VC1‧‧‧ voltage
Vr‧‧‧reference voltage
VC2‧‧‧ detected voltage
PCEN‧‧‧Precharge start signal
DOUT‧‧‧Reading information
SEN‧‧‧Sense enable signal
M1~M8‧‧‧O crystal
IV1‧‧‧ reverser
RMC1‧‧‧ reference memory cell
ISR‧‧‧reference current
SA2‧‧‧Auxiliary sense amplifier
LA1‧‧‧Latch
RBL‧‧‧ reference bit line
VB‧‧‧ bias voltage
ColC, ColR‧‧‧ column address control signal, reference column control signal
WLC, WLref‧‧‧ character address signal, reference character signal
ND1‧‧‧Logical Operation Circuit
EN1‧‧‧ signal
ISBL‧‧‧ Current
150R‧‧‧Reference current to voltage generator
310‧‧‧ Pulse Generator
S410~S460‧‧‧Steps for sensing the memory

FIG. 1 is a schematic diagram of a sensing circuit of a memory according to an embodiment of the invention. 2A is a schematic diagram of a sensing circuit according to another embodiment of the present invention. 2B is a schematic diagram of another embodiment of the sensing circuit of the embodiment of FIG. 2A of the present invention. FIG. 3 is a schematic diagram showing a manner of generating a signal EN1 according to an embodiment of the present invention. 4 is a flow chart showing a sensing manner of a memory according to an embodiment of the present invention.

Claims (12)

A sensing circuit for a memory, comprising: a precharge circuit coupled to a selected bit line of a read memory cell via a current-to-voltage generator to provide a precharge current in a precharge time interval Up to the selected bit line; a sensing current to voltage generator and switch, coupled to the selected bit line in a data sensing time interval, providing a sensing current through a first load, generating a Sense voltage; a reference current-to-voltage generator and switch, coupled to a reference memory cell in a data sensing time interval, providing a reference current through a reference load to generate a reference voltage; and an auxiliary current-to-voltage generation And a switch, coupled to the selected bit line in the pre-charging time interval, providing an auxiliary sensing current through a second load to generate a detected voltage; and a detecting circuit coupled to the The second load determines a pause time point of the pre-charge time interval according to comparing the detected voltage on the second load to the selected bit line coupling point and the reference voltage. The sensing circuit of claim 1, wherein the impedance of the second load is a ratio of the impedance value of the reference load, the ratio being the pre-charge time interval, the auxiliary sensing current and the read memory. The ratio of the cell current is determined. The sensing circuit of claim 1, wherein the detecting circuit enables a pre-charge enable signal when the data sensing time interval is activated, and The pre-charge enable signal is disabled when the detected voltage is not less than the reference voltage, wherein the pre-charge enable signal is used to indicate whether the pre-charge time interval is enabled or not. The sensing circuit of claim 1, wherein the sensing current to voltage generator and the switch comprise: a first transistor, according to a sensing enable signal to turn on the sensing current to voltage generator Up to the selected bit line, providing the sensing current to the first load; the reference current to voltage generator and the switch comprising: a second transistor, according to the sensing enable signal to turn on the reference current to voltage Generating the reference current to the reference memory to provide the reference current to the reference load; the auxiliary current to voltage generator and the switch comprise: a third transistor, according to a precharge enable signal to turn on the auxiliary current to voltage generator to The selected bit line provides the auxiliary sense current to the second load. The sensing circuit of claim 1, further comprising: a main sense amplifier coupled to the first load and receiving the sensing voltage and the reference load and receiving the reference voltage, wherein the main The sense amplifier is coupled to the sensing current coupled to the selected bit line and the voltage generated by the first load via the sensing current-turning voltage generator during the sensing time interval and after the pre-charging time is over. And a voltage difference of the reference voltage to generate a readout data. The sensing circuit of claim 1, wherein the detecting circuit comprises: An auxiliary sense amplifier coupled to the second load, receiving the detected voltage and the reference load, receiving the reference voltage, generating a detection result according to comparing the detected voltage and the reference voltage; and a latch The auxiliary sense amplifier is coupled to receive and latch the detection result to generate a precharge enable signal, wherein the precharge enable signal is used to indicate whether the precharge time interval is enabled or not. The sensing circuit of claim 4, further comprising: a current-to-voltage generator group having a plurality of current-to-voltage generators coupled to the read memory cell and the first load, respectively The second load is coupled between the reference memory cell and the reference load, and performs a current-to-voltage conversion operation according to a bias voltage. The sensing circuit of claim 7, wherein each of the current-to-voltage generators comprises: a transistor connected in series between the corresponding memory cell and the corresponding load and controlled by the bias voltage. The sensing circuit of claim 1, wherein the pre-charging circuit comprises: a pre-charging circuit pair pair coupled between the read memory cell and the sensing current-to-voltage generator, and The pre-charge current is supplied between the read memory cell and the auxiliary current-to-voltage generator to provide a precharge current to the selected bit line. A method for sensing a memory, comprising: starting a precharge time interval in a data sensing time interval; providing a precharge signal to a selected bit of a read memory cell in the precharge time interval a sensing line is provided with a sensing current-to-voltage generator and a switch to be coupled to the selected bit line to provide a sensing current through a first load to provide a sensing voltage; In the pre-charging time interval, an auxiliary current-to-voltage generator and a switch are provided, and the auxiliary current-to-voltage generator is coupled to the selected bit line, and an auxiliary sensing current is provided to pass through a first The second load provides a detected voltage; and the suspension time point of the pre-charge time interval is determined according to comparing the detected voltage and a reference voltage on the second load. The sensing method of claim 10, wherein a ratio of the impedance value of the first load to the impedance value of the reference load is determined by a ratio of the auxiliary sensing current to the read memory cell current. The sensing method of claim 10, wherein the pre-charging time interval is determined according to comparing the detected voltage between the second load and the auxiliary current-to-voltage generator coupling point and the reference voltage. The step of stopping the time point includes: enabling a pre-charge enable signal when the data sensing time interval is activated; and disabling the pre-charge enable signal when the detected voltage is not less than the reference voltage, The pre-charge enable signal is used to indicate whether the pre-charge time interval is enabled or not.