TWI627630B - Resistive memory apparatus and setting method for resistive memory cell thereof - Google Patents

Abstract

A method of setting a resistive memory device and its resistive memory cell. The method for setting the resistive memory cell comprises: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is completed; determining whether or not according to the verification result of the first verifying operation Performing a first reset operation on the resistive memory cell, and performing a second verify operation on the resistive memory cell after deciding to perform the first reset operation and performing the completion; and, according to the verification result of the second verify operation, To determine whether to perform a second reset operation on the resistive memory cell, and perform a third verify operation on the resistive memory cell after deciding to perform the second reset operation and performing the completion.

Description

Resistive memory device and method for setting resistive memory cell

The present invention relates to a resistive memory device and a method for setting the resistive memory cell thereof, and more particularly to a resistive memory device capable of preventing high temperature data from being lost, and a method of setting the resistive memory cell.

In the resistive memory, in order to restore the oxygen vacancy area of the resistive memory cell generated in the setting operation and improve the switching stability, the conventional technique proposes a resistive memory cell which is unconditionally reset after the setting is performed. Setting mechanism. However, this conventional setting mechanism is to perform setting and reset operations unconditionally for all resistive memory cells that perform setting operations. As a result, problems of the two setting operations that may occur in the conventional art as shown in FIGS. 1A and 1B may occur.

In FIG. 1A, for a normal resistive memory cell, an excessively strong reset operation may cause the oxygen ions OX in the titanium layer 110 to be pushed into the oxygen vacant region 120 in a large amount, through the oxygen vacant region 120 and the oxygen ions. The composite action of OX, the area where the oxygen vacancy zone 120 is in contact with the titanium layer 110 is narrowed, and the problem of high temperature data remaining lost is generated.

In FIG. 1B, the excessively weak reset operation cannot cause the possible oxygen ions OX to be pushed away from the oxygen vacancy zone 110, and the oxygen vacancy zone 110 may be weakened by the combination of the oxygen vacancy zone 110 and the oxygen ion OX. Causes the problem of high temperature data to be lost.

The invention provides a plurality of resistive memory devices and a method for setting the resistive memory cells thereof, thereby effectively improving the problem of failure of high temperature data storage.

The method for setting a resistive memory cell of the present invention comprises: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is completed; and verifying the result according to the first verifying operation Determining whether to perform a first reset operation on the resistive memory cell, and performing a second verify operation on the resistive memory cell after deciding to perform the first reset operation and performing the completion; and, according to the second verify operation The result is verified to determine whether to perform a second reset operation on the resistive memory cell, and perform a third verify operation on the resistive memory cell after deciding to perform the second reset operation and performing the completion.

Another method for setting a resistive memory cell of the present invention comprises: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is completed; Verifying the result to determine whether to perform the second setting operation on the resistive memory cell, and performing a second verifying operation on the resistive memory cell after deciding to perform the second setting operation and performing the completion; according to the verification result of the second verifying operation, Determining whether to perform a first reset operation on the resistive memory cell, and performing a third verify operation on the resistive memory cell after deciding to perform the first reset operation and performing the completion; determining whether or not according to the verification result of the third verify operation Performing a second reset operation on the resistive memory cell, and performing a fourth verify operation on the resistive memory cell after deciding to perform the second reset operation and performing the completion; and determining whether or not according to the verification result of the fourth verify operation A third reset operation is performed on the resistive memory cell.

The resistive memory device of the present invention includes a plurality of resistive memory cells, a controller, and a current validator. The resistive memory cell is coupled to the source line and the bit line, the controller is coupled to the source line and the bit line, and the current validator is coupled to the bit line. The controller is configured to perform the plurality of steps of the above-described method of setting the resistive memory cell.

Based on the above, the method of setting the resistive memory cell of the present invention performs a verify operation after performing a setting operation on the resistive memory cell, and determines whether to perform a subsequent reset operation based on the verification result of the verify operation. In this way, when the method for setting a resistive memory cell with different characteristics is used, the adaptive setting action can be adjusted for the characteristics of the selected resistive memory cell, which can effectively reduce the generation of data when the resistive memory cell is at a high temperature. The probability of loss, maintaining the yield of the resistive memory device.

The above described features and advantages of the invention will be apparent from the following description.

Please refer to FIG. 2. FIG. 2 is a flow chart showing a method for setting a resistive memory cell according to an embodiment of the present invention. When the set operation is performed on the resistive memory cell, the first setting operation is performed on the resistive memory cell by performing step S210, and the first verification is performed on the resistive memory cell after the first setting operation is completed. Operation; then, after the first verification operation is completed, by performing step S220 to determine whether to perform the first reset operation on the resistive memory cell according to the verification result of the first verification operation, and deciding to perform the first reset operation After the execution is completed, the second verification operation is performed on the resistive memory cell. Next, in step S130, according to the verification result of the second verification operation, to determine whether to perform the second reset operation on the resistive memory cell, and after performing the second reset operation and performing the completion of the execution, the resistive memory cell is executed. The third verification operation.

According to the above description, in the method for setting a resistive memory cell according to the embodiment of the present invention, after the first setting operation is completed, the resistive memory cell does not unconditionally perform the first reset for the resistive memory cell. operating. In contrast, in the embodiment of the present invention, the first verification operation is performed on the resistive memory cell after the first setting operation, and the resistance result is determined according to the verification result generated by the first verification operation. Perform the first reset operation. Specifically, the first verification operation can verify the resistance value of the resistive memory cell after the first setting operation is completed, and when the first verification operation verifies that the resistance value of the resistive memory cell is set to be less than one pre- When the threshold is set, it indicates that the setting operation of the resistive memory cell has been completed, and the subsequent first reset operation is not required. In contrast, if the first verification operation verifies that the resistance value of the resistive memory cell is set to be not less than the preset threshold value, it indicates that the setting operation of the resistive memory cell has not been completed, and a subsequent first reset is required. operating. Moreover, in the embodiment of the present invention, after performing the second verification operation after the first reset operation is completed, it is determined that a further second reset operation needs to be performed.

Regarding the operation details, when the first setting operation is performed on the resistive memory cell, the first set voltage may be provided across the two ends of the resistive memory cell, thereby lowering the resistance value of the resistive memory cell, and then, Verification operation for resistive memory cells. When the first verification operation of the resistive memory cell is performed, a verification voltage is provided across the two ends of the resistive memory cell, and the verification current generated by the resistive memory cell according to the verification voltage is measured, and the current of the verification current is made The value is compared to a preset value. When the current value of the verification current is greater than the preset value, it indicates that the action of the resistive memory cell has been completed. In contrast, when the current value of the verification current is not greater than the preset value, it indicates that the action of the resistive memory cell is not completed.

When the verification result of the first verification operation indicates that the setting operation of the resistive memory cell is not completed, the first reset voltage may be supplied to both ends of the resistive memory cell, and the first reset operation is performed for the resistive memory cell. When the verification result of the second verification operation indicates that the setting operation of the resistive memory cell is not completed, the second reset operation of the resistive memory cell may be performed to perform the setting operation on the resistive memory cell.

Referring to FIG. 3, FIG. 3 is a schematic diagram showing the wave form of the setting operation of the resistive memory cell according to the embodiment of the present invention. In the phase S1, the set voltage VS1 is supplied to bridge across the resistive memory cells and the setting operation is performed. Then, after the setting operation is completed (after the step S1), the verify operation VFY1 is performed for the resistive memory cell. Then, if the verification result of the verification operation VFY1 indicates that the setting operation of the resistive memory cell is not completed, the reset voltage VR1 may be supplied across the two ends of the resistive memory cell and the reset operation may be performed at the stage R1. It should be noted that the reset voltage VR1 is opposite to the polarity of the set voltage VS1, and in the present embodiment, the absolute value of the voltage of the reset voltage VR1 is smaller than the absolute value of the voltage of the set voltage VS1.

On the other hand, in the embodiment of the present invention, after the reset operation is completed (after the phase R1), the verification operation VFY2 is performed again for the resistive memory cell, and it is verified whether the setting operation of the resistive memory cell has been carry out. If it is verified that the setting operation of the resistive memory cell is completed, the setting operation of the resistive memory cell can be suspended. In contrast, if the setting operation of the resistive memory cell is verified to be incomplete, the resistive memory cell can be performed in the phase R2. The reset operation is performed again, and the verification operation VFY3 is performed after the phase R2. The absolute value of the voltage of the reset voltage VR2 applied in the phase R2 may be greater than the absolute value of the voltage of the reset voltage VR1 applied in the phase R1.

If the verification result of the verification operation VFY3 still indicates that the setting operation of the resistive memory cell is not completed, in the embodiment of the present invention, the set voltage VS2 may be provided in the phase S2 to be connected across the two ends of the resistive memory cell, and This performs a set operation again. The voltage value of the set voltage VS2 is greater than the voltage value of the set voltage VS1. And, after the setting operation is completed (after step S2), the verification operation VFY4 is performed for the resistive memory cell.

In addition, after the verify operation VFY4, one or more reset operations and a loop operation of the verify operation may be performed for the resistive memory cell, and thereby the setting operation of the resistive memory cell is completed. In FIG. 3, the phases R3 and R4 respectively perform different levels of reset operations, wherein the reset voltage of the reset voltage VR2 provided by the reset operation of the phase R3 is smaller than the reset voltage provided by the reset operation of the phase R4. The absolute value of the voltage of VR3, and the verification operations VFY4 and VFY5 occur immediately after the phases R3, R4. The absolute value of the voltage of the reset voltage VR2 applied in the phase R2 may be smaller than the absolute value of the voltage of the reset voltage VR3 applied in the phase R4.

It can be noted that the verifying operation VFY1-VFY5 in the embodiment of the present invention can be performed by providing a positive or negative verifying voltage to the resistive memory cell by reading the read current generated by the resistive memory cell.

Referring to FIG. 4, FIG. 4 is a flowchart of a method for setting a resistive memory cell according to another embodiment of the present invention. In step S410, a set voltage VS1 having a voltage absolute value of, for example, 4.5V to 1.5V is supplied to the resistive memory cell, thereby performing a setting operation. Next, step S420 performs a verification operation, and determines whether the verification current generated by the resistive memory cell according to the verification voltage is greater than a preset value (for example, 17 uA). If the verification current is greater than 17 uA, the setting operation is completed (step S421), and if the verification current is not greater than 17 uA, the process proceeds to step S422.

Step S422 provides a reset voltage VR1 of a voltage absolute value (for example, between 3.6V and 0.6V) to the resistive memory cell, thereby performing a reset operation. Next, a verification operation is performed on the resistive memory cell in step S423, and it is determined whether the verification current is greater than a preset value (for example, 17 uA). If the verification current is greater than 17 uA, the setting operation is completed (step S424), and if the verification current is not greater than 17 uA, step S425 is performed.

Step S425 provides a reset voltage VR2 (greater than the reset voltage VR1) with a higher voltage absolute value (for example, between 3.8V and 0.8V) for another reset operation. And, in the subsequent step S426, the verification operation is performed on the resistive memory cell, and it is judged whether or not the verification current is greater than a preset value (for example, 17 uA). If the verification current is greater than 17 uA, the setting operation is completed (step S427), and if the verification current is not greater than 17 uA, the process proceeds to step S430.

Step S430 performs a further setting operation of the resistive memory cell. In step S430, the setting operation is performed on the resistive memory cell by providing the set voltage VS2 whose voltage absolute value is, for example, 5.0V-2.0V. It is worth mentioning that the absolute value of the voltage of the set voltage VS2 in step S430 is greater than the absolute value of the voltage of the set voltage VS1 in step S410.

In step S440 following the step S430, a verification operation is performed on the resistive memory cell, and it is judged whether or not the verification current is greater than a preset value (for example, 17 uA). If the verification current is greater than 17 uA, the setting operation is completed (step S441), and if the verification current is not greater than 17 uA, step S450 is performed.

Step S450 performs a reset operation on the resistive memory cell by providing a reset voltage VR3 of an absolute value of the voltage, for example, between 3.8V and 0.8V, and performs a verify operation on the resistive memory cell in step S460, and determines whether the verify current is Greater than the preset value (for example, 17uA). If the verification current is greater than 17 uA, the setting operation is completed (step S461), and if the verification current is not greater than 17 uA, step S470 is performed.

Step S470 performs a reset operation on the resistive memory cell by providing a voltage absolute value, for example, a reset voltage VR4 of 4.0V-1.0V, and performs data output after the reset operation is completed. Here, the absolute value of the voltage of the reset voltage VR4 provided in step S470 may be greater than the absolute value of the voltage of the reset voltage VR3 provided in step S450. And, after the completion of step S470, the action of data output can be performed.

The above-mentioned values about the set voltage VS1-VS2, the reset voltages VR1-VR4, and the verify current can be appropriately adjusted according to the actual electrical characteristics of the resistive memory cell, and the values proposed in the embodiment of the present invention are only a demonstration. Sexual examples are not intended to limit the scope of the invention.

Referring to FIG. 5A to FIG. 5C , FIG. 5A to FIG. 5C are schematic diagrams showing various embodiments of a method for setting a resistive memory cell according to an embodiment of the present invention. In FIG. 5A, after the operation S511 is set, a plurality of reset operations R511 and R512 can be connected, and after a plurality of reset operations R511 and R512, a further setting operation S512 can be performed for the resistive memory cell, and the setting operation is performed. After S512, a plurality of reset operations R513 and R514 are performed. Of course, after each setting operation S511, S512 and the reset operation R511-R514, the verification operations V51-V55 are separately performed, and it is determined according to the verification result of the verification operations V51-V55 whether or not subsequent operations are required.

It is worth mentioning that in FIG. 5A, the absolute values of the set voltages of the sequentially set operation operations S511 and S512 can be sequentially increased. Similarly, the absolute reset voltage of the reset operation R511-R514 occurs in sequence. Values can also be promoted in order.

In addition, in FIG. 5B, a plurality of setting operations S521 and S522 may be performed for the resistive memory cell, and a plurality of reset operations R521-R523 may be performed for the resistive memory cell. The absolute values of the set voltages of the sequentially occurring setting operations S521 and S522 may be sequentially increased. Similarly, the absolute values of the reset voltages of the sequentially occurring reset operations R521-R523 may be sequentially increased. Of course, after each setting operation S521, S522 and the reset operation R521-R523, the verification operations V51-V54 are separately performed, and it is determined whether the subsequent operations are required according to the verification results of the verification operations V51-V54.

In FIG. 5C, a one-time setting operation S531 can be performed first for the resistive memory cell, and a plurality of reset operations R531-R534 can be performed for the resistive memory cell. The absolute value of the reset voltage of the reset operation R521-R523 may be sequentially increased, and after the setting operation S531 and the reset operation R531-R534, the verification operations V51-V54 are separately performed, and Verify the verification result of operation V51-V54 to determine whether subsequent operations are required.

Please refer to FIG. 6. FIG. 6 is a schematic diagram of a resistive memory device according to an embodiment of the invention. The resistive memory device 600 includes a resistive memory cell RC1-RC3, a controller 620, and a current validator 630. The resistive memory cells RC1-RC3 can form a memory cell block 610 and are coupled to the source line SL1 and the bit line BL1. The controller 620 is coupled to the source line SL1 and the bit line BL1. The current validator 630 is coupled to the bit line BL1. The controller 620 can select one or more selected resistive memory cells of the resistive memory cells RC1-RC3 through an address decoding operation, and provide a set voltage, a reset voltage, or a verify voltage to the selected resistive type. The memory cell performs a set operation, a reset operation, or a verification operation. The controller 620 can provide a set voltage to bridge between the source line SL1 and the bit line BL1 to set the selected resistive memory cell when the setting operation is performed. The controller 620 may provide a reset voltage to bridge between the source line SL1 and the bit line BL1 to set the selected resistive memory cell when the setting operation is performed. Wherein, the polarity of the reset voltage and the polarity of the set voltage may be opposite. When performing the verifying operation, the controller 620 can provide a verify voltage to the source line, and the current validator 630 can obtain the verify current generated by the selected resistive memory cell according to the verify voltage through the bit line BL1. The current validator 630 compares the current value of the verification current with a preset value, and determines whether the setting action of the selected resistive memory cell is completed when the current value of the verification current is greater than a preset value.

Details of the implementation of the controller 620 and the current validator 630 have been described in detail in the foregoing embodiments, and will not be further described herein.

In summary, the setting operation of the resistive memory cell provided by the present invention increases the verify operation after the setting operation, and determines whether to perform the reset operation for the resistive memory cell according to the verifying operation. In this way, the setting action of different processes can be performed for the resistive memory cells with different characteristics, and the probability that the resistive memory cells generate high temperature data is lost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

110‧‧‧Titanium layer

OX‧‧‧Oxygen ion

120‧‧‧Oxygen Vacancy

S210-S220, S410-S470‧‧‧Resistive memory cell setting steps

VFY1-VFY5‧‧‧ verification operation

R1-R4, S1-S2‧‧‧ stage

VS1, VS2‧‧‧ set voltage

VR1-VR4‧‧‧Reset voltage

R511, R512, R521-R523, R531-R534‧‧‧ Reset operation

S511, S512, S521, S522, S531‧‧‧ setting operation

V51-V55‧‧‧ verification operation

600‧‧‧Resistive memory device

RC1-RC3‧‧‧Resistive memory cell

620‧‧‧ Controller

630‧‧‧current validator

SL1‧‧‧ source line

BL1‧‧‧ bit line

The problem of the two setting operations that may occur in the prior art illustrated in Figures 1A and 1B. 2 is a flow chart showing a method of setting a resistive memory cell according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing the wave form of the setting operation of the resistive memory cell according to the embodiment of the present invention. 4 is a flow chart showing a method of setting a resistive memory cell according to another embodiment of the present invention. 5A-5C are schematic diagrams showing various embodiments of a method for setting a resistive memory cell according to an embodiment of the present invention. 6 is a schematic diagram of a resistive memory device in accordance with an embodiment of the present invention.

Claims (16)

A method for setting a resistive memory cell includes: providing a first set voltage to the resistive memory cell to perform a first setting operation, and performing a first direct setting operation on the resistive memory cell after the first setting operation is completed a first verification operation; determining, according to the verification result of the first verification operation, whether to perform a first reset operation on the resistive memory cell, and after determining to perform the first reset operation and performing the completion of the resistive The memory cell performs a second verification operation; and according to the verification result of the second verification operation, to determine whether to perform a second reset operation on the resistive memory cell, and decides to perform the second reset operation and performs the completion A third verify operation is performed on the resistive memory cell. The method for setting a resistive memory cell according to the first aspect of the invention, further comprising: determining whether to perform a second setting operation on the resistive memory cell according to the verification result of the third verifying operation, and determining Performing a fourth verification operation on the resistive memory cell after the execution of the second setting operation is completed. The method for setting a resistive memory cell according to claim 2, wherein the step of performing the second setting operation on the resistive memory cell comprises: providing a second set voltage to bridge across the resistive memory cell And performing, by the two ends, the second setting operation on the resistive memory cell, wherein the voltage value of the second set voltage is greater than the voltage value of the first set voltage. The method for setting a resistive memory cell according to claim 1, wherein the step of performing the first verifying operation on the resistive memory cell comprises: providing a verify voltage across the two ends of the resistive memory cell And measuring a verification current generated by the resistive memory cell according to the verification voltage; and determining whether the verification current is greater than a predetermined value to generate a verification result of the first verification operation, wherein the first verification operation is performed according to the first verification operation The step of verifying the result to determine whether to perform the first reset operation on the resistive memory cell includes: providing a first reset voltage across the resistive memory cell when the verify current is not greater than the preset value Both ends of the operation perform the first reset operation on the resistive memory cell. The method for setting a resistive memory cell according to the first aspect of the invention, further comprising: determining whether to perform a third reset operation on the resistive memory cell according to the verification result of the third verifying operation, and Determining to perform the third reset operation and performing a fourth verify operation on the resistive memory cell after the completion of the execution; and determining whether to perform a fourth reset on the resistive memory cell according to the verification result of the fourth verify operation operating. The method for setting a resistive memory cell according to claim 4, wherein the step of performing the second reset operation comprises: providing a second reset voltage across the two ends of the resistive memory cell to The resistive memory cell performs the second reset operation, The voltage value of the second reset voltage is greater than the voltage value of the first reset voltage. The method for setting a resistive memory cell according to claim 2, further comprising: determining whether to perform a third reset operation according to the verification result of the fourth verification operation, and deciding to execute the third weight And performing a fifth verifying operation on the resistive memory cell after the operation is completed; and determining whether to perform a fourth reset operation on the resistive memory cell according to the verification result of the fifth verifying operation. A method for setting a resistive memory cell, comprising: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is completed; Verifying the verification result of the operation to determine whether to perform a second setting operation on the resistive memory cell, and performing a second verifying operation on the resistive memory cell after deciding to perform the second setting operation and performing the completion; and a verification result of the second verification operation to determine whether to perform a first reset operation on the resistive memory cell, and perform a third operation on the resistive memory cell after deciding to perform the first reset operation and performing the completion a verification operation; determining, according to the verification result of the third verification operation, whether to perform a second reset operation on the resistive memory cell, and determining the execution of the second reset operation and performing the completion of the resistive memory cell Performing a fourth verification operation; and determining a verification result according to the verification result of the fourth verification operation The memory cell performs a third reset operation. A resistive memory device includes: a plurality of resistive memory cells coupled to a source line and a bit line; a controller coupled to the source line and the bit line; and a current validator The controller is configured to: provide a first set voltage to a selected resistive memory cell to perform a first setting operation, and after the first setting operation is completed, directly enable the The current validator performs a first verifying operation on the selected resistive memory cell; determining whether to perform a first reset operation on the selected resistive memory cell according to the verification result of the first verifying operation, and determining to execute Performing a second verification operation on the selected resistive memory cell after the first reset operation is performed; and determining whether to perform the first resistive memory cell according to the verification result of the second verify operation And a second reset operation, and performing a third verify operation on the selected resistive memory cell after deciding to perform the second reset operation and performing the completion. The resistive memory device of claim 9, wherein the controller determines whether to perform a second setting operation on the selected resistive memory cell according to the verification result of the third verifying operation, and determines Performing a fourth verification operation on the selected resistive memory cell after the execution of the second setting operation is completed. The resistive memory device of claim 10, wherein the controller provides a second set voltage to bridge across the selected resistive memory cell and select the resistive memory cell The second setting operation is performed, wherein the voltage value of the second set voltage is greater than the voltage value of the first set voltage. The resistive memory device of claim 9, wherein the controller provides a verification voltage across the two ends of the selected resistive memory cell, and the current validator measures the selected resistive And determining, by the memory cell, a verification current generated by the verification voltage, and determining whether the verification current is greater than a predetermined value to generate a verification result of the first verification operation, wherein when the current verification device determines that the verification current is not greater than the pre-determination When set, the controller provides a first reset voltage across the selected resistive memory cells to perform the first reset operation on the selected resistive memory cell. The resistive memory device of claim 9, wherein the controller is further configured to: determine whether to perform a third reset on the selected resistive memory cell according to the verification result of the third verifying operation Operating, and performing a fourth verify operation on the selected resistive memory cell after deciding to perform the third reset operation and performing the completion; and determining whether to select the resistive type according to the verification result of the fourth verify operation The memory cell performs a fourth reset operation. The resistive memory device of claim 12, wherein the controller provides a second reset voltage across the two ends of the selected resistive memory cell to perform the selected resistive memory cell. The second reset operation, wherein the voltage value of the second reset voltage is greater than the voltage value of the first reset voltage. The resistive memory device of claim 10, wherein the controller is further configured to determine whether to perform a third reset operation according to the verification result of the fourth verification operation, and decide to execute the third Performing a fifth verify operation on the selected resistive memory cell after the reset operation is completed; and determining whether to perform a fourth reset operation on the selected resistive memory cell according to the verification result of the fifth verify operation . A resistive memory device includes: a plurality of resistive memory cells coupled to a source line and a bit line; a controller coupled to the source line and the bit line; and a current validator And the controller is configured to: perform a first setting operation on a selected resistive memory cell, and perform a first performing on the selected resistive memory cell after the first setting operation is completed a verification operation; determining, according to the verification result of the first verification operation, whether to perform a second setting operation on the selected resistive memory cell, and determining the selected resistance after performing the second setting operation and performing the completion Memory cell performs a second verification operation; And determining, according to the verification result of the second verification operation, whether to perform a first reset operation on the selected resistive memory cell, and selecting the resistive type after deciding to perform the first reset operation and performing the completion The memory cell performs a third verification operation; according to the verification result of the third verification operation, to determine whether to perform a second reset operation on the selected resistive memory cell, and decides to perform the second reset operation and execute After completion, performing a fourth verifying operation on the selected resistive memory cell; and determining whether to perform a third reset operation on the selected resistive memory cell according to the verification result of the fourth verifying operation.