TWI627520B - System to configure thermal design power in a microprocessor or processing means - Google Patents

Abstract

A technique for changing the thermal design power (TDP) value. In one embodiment, one or more environment or user driven changes may cause a processor's TDP value to be changed. Moreover, in some embodiments, a change in the TDP can change the acceleration mode target frequency.

Description

System for configuring thermal design power in a processor or processing device [related application]

This is a partial continuation of the US application No. 12/974100 filed on December 21, 2010.

Several embodiments of the present invention are generally in the field of information processing, and more particularly in the field of power management in computing systems and microprocessors.

Background of the invention

The importance of controlling the power consumption in a microprocessor is increasing. Some prior art techniques for controlling processor power consumption do not adequately allow for an elastic configuration of the processor's thermal design power (TDP) specifications.

Summary of invention

In accordance with an embodiment of the present invention, a processor is specifically provided that includes logic for changing a processor thermal design power (TDP) value in response to user control.

In accordance with another embodiment of the present invention, a system is specifically provided comprising: a processor including logic for changing a processor thermal design power (TDP) value in response to user control; memory, To store instructions to be executed by the processor.

In accordance with yet another embodiment of the present invention, a method is specifically provided that includes the steps of changing a processor thermal design power (TDP) value in response to user control.

92, 94‧‧‧ memory

105‧‧‧ Thermal Design Power (TDP)

110‧‧‧Normal Thermal Design Power (TDP)

115‧‧‧ Thermal Design Power (TDP)

120~130‧‧‧P state

205‧‧‧Operating system P state control

210, 310, 410, 510, 610, 811, 910‧‧‧ Basic Input/Output Software (BIOS)

215‧‧‧OSPM Power Configuration Small Application

220‧‧‧DPTF drive

225, 801, 805, 810, 815, 970, 980‧‧ ‧ processors

230‧‧‧ACPI Notice

240‧‧‧Users

245‧‧‧trigger

255‧‧‧Configurable Thermal Design Power (TDP)

260‧‧‧User mode

265‧‧‧ nuclear mode

270‧‧‧ Thermal Design Power (TDP) Configuration

305, 405‧‧‧ end users

315, 415, 525, 615‧‧‧ Processor/Power Control Unit (PCU)

320, 420, 515, 620‧‧‧ OSPM

325~355, 425~445, 530~555, 625~645‧‧‧ processing procedures

405‧‧‧End users

505‧‧‧ events

520‧‧‧DPTF driver

605‧‧‧ Platform EC

700‧‧‧Microprocessor

701‧‧‧Instruction decoding/scheduling

705, 710, 823, 827, 833, 837, 843, 847, 853, 857, 930‧‧‧ core

707, 713, 803, 807, 813, 817‧‧‧ cache

709‧‧‧Integer register/bypass

710‧‧‧Floating point register/bypass

712‧‧‧ST

714‧‧‧LD

715‧‧‧Shared cache memory

716‧‧‧FALU

719, 819, 919‧‧ ‧ Logic

720‧‧‧CALU

722‧‧‧MMX SSE FPU

724‧‧‧BR FPU

812‧‧‧I/O

820, 825, 830, 835, 840, 845, 850, 855‧‧‧ Cache memory

829‧‧‧PCI bus

839‧‧‧ front side bus

860‧‧‧System Memory

865, 990‧‧‧ chipset

870‧‧‧Network adapter

873‧‧‧PCI CTL

874‧‧‧Disk CTL

875‧‧ ‧Bridge

914‧‧‧I/O equipment

918‧‧ ‧ bus bar bridge

922‧‧‧Keyboard/mouse

924‧‧‧Audio I/O

926‧‧‧Communication equipment

928‧‧‧Data storage

938‧‧‧High-performance graphics circuit

939‧‧‧High-performance graphical interface

950, 952, 954‧ ‧ peer-to-peer (PtP) interface

972, 982‧‧‧ Memory Controller Hub (MCH)

974, 984‧‧‧ processor core

976, 978, 986, 988, 994, 998‧ ‧ point-to-point (PtP) interface circuits

992, 996‧‧‧I/F

The embodiments of the present invention are illustrated by way of example, and not limitation, in the drawings For example, a technique for configuring thermal design power (TDP) is exemplified

Figure 2 illustrates at least one level of techniques for configuring a TDP, in accordance with one embodiment.

Figure 3 illustrates an aspect of an initialization technique corresponding to a configurable TDP, in accordance with one embodiment.

Figure 4 illustrates at least one level of techniques for configuring a TDP, in accordance with one embodiment.

Figure 5 illustrates at least one level of techniques for configuring a TDP, in accordance with one embodiment.

Figure 6 illustrates at least one level of techniques for configuring a TDP, in accordance with one embodiment.

Figure 7 illustrates a block diagram of a microprocessor in which at least one embodiment of the present invention may be utilized.

Figure 8 illustrates a block diagram of a shared bus computer system in which at least one embodiment of the present invention may be utilized.

Figure 9 illustrates a block diagram of a point-to-point interconnect computer system in which at least one embodiment of the present invention may be utilized.

Detailed description of the preferred embodiment

Several embodiments of the present invention are directed to a configurable thermal design power (TDP) consumption for a processor. Although a plurality of embodiments of the present invention are present in a plurality of embodiments, at least one or more layers are illustrated by way of example to teach a few embodiments of the present invention. Interpreted as a set of exhaustive or exclusive embodiments.

The processor can be rated or specified to include both performance and power related characteristics. Several individual products or several product families may have an associated specification, including specified base and turbo frequency capabilities, as well as other performance related features. The range of power consumption in a processor can be specified for a family of products. For example, a standard voltage (SV) mobile processor might have 35 watts. Thermal Design Power (TDP) rating. This rating may be an indication to the original equipment manufacturers (OEMs) that a processor purchased by an OEM will dissipate less than or equal to the specified TDP value of the product when running a specified TDP workload. Power, this specified TDP workload represents a worst-case real-world workload scenario when operating at worst-case temperatures. Although the specified performance characteristics may vary in a family of products, TDP can be assigned the same value across multiple product families. This allows an OEM to design a single platform that can dissipate the specified TDP while providing a range of different retail price performance. Acceleration capabilities, on the other hand, are a potential performance benefit because TDP workloads can cause TDP power to dissipate at the fundamental frequency.

In some embodiments, there are several types of acceleration modes. The above is a version of the acceleration mode for workload or package power sharing. In this case, if there is no acceleration, the workload with lower natural power than the TDP application can benefit from the same frequency. These workloads can benefit by allowing the power to rise to the package TDP power by giving power above the base frequency. Another version of the acceleration mode is the dynamic acceleration mode, in which the power is allowed to exceed the TDP power for a finite period of time, so that on average, the power is still TDP power over time, which allows for lower than previously The power of the TDP may have a short deviation from the TDP regardless of, for example, whether it is an idle workload or just a workload that does not cite power equal to the TDP power threshold. TDP power can also impact power delivery design requirements.

Platform thermal capability is a design choice for OEMs because of its impact, size, weight, audible noise, and bill of materials (BOM) costs. The specified TDP for the processor may thus have a significant impact on the thermal design of the platform. Some processors are only sold with a few TDPs. For example, the SV of a 35W mobile processor, the SV of a 25W low voltage processor, and the SV of an 18W ultra low voltage processor.

In the mobile platform, there is a possibility that the cooling capacity and the audible noise tolerance may vary depending on the usage environment. For example, a platform that is docked and operating on alternating current (AC) power may have greater cooling capacity than when battery power is used for undocked operation.

Operating a higher power processor in an environment with less than the ability to cool the specified TDP may result in reduced thermal control performance to a very unknown level of capability that varies from product to product. In addition, acceleration capabilities may be deactivated as part of thermal control.

A configurable TDP in accordance with one embodiment may allow an OEM to configure a TDP of a processor to one of several values. This configuration can be done statically in initialization, or dynamically, "on-the-fly." This is done efficiently by changing the base frequency of the processor to one of several supported base frequencies. This change can be guaranteed by the base frequency to guarantee a certain performance, and this TDP is assigned to each of these support base frequencies. In addition, as the base frequency/TDP changes, the point of accelerated engagement also changes. This provides OEMs with the ability to It is known that the presented workload allows for accelerated boost performance while still ensuring maximum power dissipation while still delivering accelerated boost performance.

FIG. 1 illustrates a technique for providing three TDP levels respectively corresponding to a plurality of power states, such as P states P0 130, P5 125, and P9 120, such as "on a TDP," according to an embodiment. 105, "Normal TDP" 110 and "TDP Down" 115, while providing a configurable TDP in one processor. In one embodiment, as the TDP value changes dynamically, the magnitude of the acceleration capability also changes, allowing for more favorable aspects of the acceleration boost technique while still providing specific performance to the end user.

In one embodiment, a configurable TDP technique includes a verified and configured frequency and TDP set provided to a processor. In one embodiment, the verified values may be fused, planned, or otherwise configured into hardware that allows the platform firmware or software to detect and utilize this capability.

In one embodiment, the configurable TDP provides a mechanism for designing the processor as a new segment of the platform. For example, a processor that supports configurable TDP can offer benefits over other non-configurable TDP processors. The OEM can then choose to purchase a processor and configure the processor for its needs or provide this processor in a platform that supports in-provisioning of performance and power. One such example is a "mobile extreme edition" platform that is not docked and uses batteries. Configurable TDP also has the potential to reduce the number of product families offered.

In one embodiment, the configurable TDP architecture does not do anything in the standard Or assumptions about interdependencies with other technologies, and so on. Table 1 below describes various aspects and portions of a platform that can be affected by configurable TDP, in accordance with one embodiment.

In one embodiment, a model specific registers (MSR) can be changed for a processor, and a new MSR can be used to support the configurable TDP of the processor. These registers may provide the ability to change the point at which the junction is accelerated, for example, and the ability to set a runtime average power limiting (RAPL) power limit value for the new base frequency. In one embodiment, a series of registers that can be accessed, changed, or added using a configurable TDP include: PLATFORM_INFO: This register can be used to detect configurable TDP capabilities, CONFIG_TDP_LIMIT_1; CONFIG_TDP_LIMIT_2: This register is available To detect the configurable TDP ratio and the corresponding TDP power and power range, CONFIG_TDP_CONTROL: This register can be used to allow the software to select different TDP points and read the current selection. PSTATE_NOTIFY Hook: This register can be used to allow software to be energized from a new one. Acceleration of the P1 ratio point. Separating this register from CONFIG_TDP_CONTROL allows for a number of usage models in which the OS may choose a specified ceiling that can tolerate the acceleration range.

In other embodiments, other registers or banks (eg, memory, cache, etc.) may be used to provide a configurable TDP. Moreover, in some embodiments, the functions provided in the above registers are It is integrated into a smaller amount of registers or storage.

In some embodiments, there may not be a unique platform entity requirement for a configurable TDP. However, in some embodiments, specifications for power delivery and cooling may be developed to cope with the requirements for individual TDP points. In some embodiments, the specifications may reflect the ability to select TDP levels for the design, and may or may not accommodate other points.

In some embodiments, a new interface or technique may not be particularly needed to support a configurable TDP. However, in some embodiments, the affected design features that can be addressed in specification and energization include thermal design current (ITDC) and the maximum possible current that can be supported (eg, "Iccmax"). In some embodiments, parameters may be defined for each TDP point.

TDP can be implicit, presenting an infinitely long-lasting cooling level to support the corresponding TDP power level. However, in one embodiment, no particular technique is required to represent changes in cooling capacity, whether it is external design, parked cooling, changes in fan speed, changes in the surrounding environment, and the like. However, in the case of enabling documentation, several cooling design requirements can be established for each TDP level.

In one embodiment, a configurable TDP can be used for other logic, such as graphics, memory control, or peripheral device control. For example, if a configurable TDP is used for graphics, it may be necessary to inform a graphics driver about the new TDP level and the corresponding RP1 frequency. In one embodiment, this can be done in at least two ways:

(1) via the change at the TDP level and the corresponding RP1 frequency An interrupt from the processor to the graphics device driver. In one embodiment, this may require several interrupt configurations and status registers in addition to the scratchpads that are required to support the configurable TDP.

(2) Notifying the graphics driver TDP level and the corresponding TP1 frequency when to change via the software stack. This may require updating the software that is already in place as part of the software stack to the graphics driver communication interface.

In one embodiment, changing the TDP configuration may require the platform to restrict the OS from utilizing certain P-states (eg, ACPI notifications), and expose the OS to the OS during initialization and by enabling acceleration at various operating points. All available P states. In some embodiments, an ACPI P-state table (PSS) can be suitably implanted. In one embodiment, there may be no ecosystem requirements for supporting a configurable TDP.

In one embodiment, the configurable TDP is statically configured by the BIOS, for example, during initialization, or dynamically configured by the BIOS or a software driver during runtime to not be melted ( A value of fused default). In one embodiment, a corresponding power limit is written to by writing a new acceleration rate limit to the MSR to set the point at which the junction is accelerated, and based on the value specified for the portion/base frequency. The RAPL power limits the MSR to complete the configuration of the TDP. Moreover, in some embodiments, depending on the new base frequency, the operating system can be notified to limit its use of the P state. In one embodiment, this can be achieved by causing the OS to evaluate the ACPI_PCC object under each of the complex logical processors (ACPI: Advanced Configuration and Power Interface; PCC: Performance Presentation) Performance Present Capabilities).

Figure 2 illustrates logic for configuring a TDP, in accordance with one embodiment. The logic illustrated in Figure 2 may be included in one processor hardware or some other hardware. Alternatively, the logic in FIG. 2 can be incorporated into a tangible, machine-readable medium having stored instructions that, if executed, cause the functionality of the logic illustrated in FIG. 2 to be carried out. In FIG. 2, the OSPM power configuration mini-app 215 can be selective and its use of DPPE services is a trigger 245 to motivate a TDP configuration change. Based on a trigger 245, such as a power source or power plan change, the mini-app will communicate this change to the DPTF driver 220.

The DPTF driver 220 receives the TDP configuration changes from the OSPM power configuration applet and thus performs two functions. The first is to evaluate an ACPI object within its device. This ACPI object causes an ACPI notification to be sent by the BIOS 210 on the logical processor 225 to the OS to inform it to re-evaluate the PPC objects under each logical processor. . The return value from this object is a value derived from the DPTF driver 220 and limits the use of certain P states by the operating system to the new base frequency and below. After this is done, DPTF driver 220 writes a new TDP configuration 270 to processor 225 (MSR write) to set a new acceleration ratio for this processor (indicating where the acceleration is being steered) and for a new basis The corresponding RAPL power limit value for the frequency.

In one embodiment, this processor contains the MSR described above. Write MSR to carry information to acceleration and RAPL power limits The power control unit (PCU) on the P state where the value is ignited (acceleration ratio).

In one embodiment, BIOS 210 contains ACPI firmware and locally executable code. In one embodiment, BIOS 210 may be responsible for detecting configurable TDP 255 feature availability and appropriately establishing an ACPI firmware structure (_PSS). The BIOS 210 can statically configure one TDP that is less than the maximum of one product or family during the initialization period. Alternatively, in one embodiment, the BIOS 210 itself may dynamically set the TDP configuration by performing a combination with the ACPI notification via the SMM. The DPTF can also be utilized to dynamically set the TDP configuration, but in another case, the BIOS 210 contains ACPI firmware that is evaluated to signal the OS to re-evaluate the _PPC object under each logical processor. In one embodiment, this _PPC object evaluation will determine which P states are currently available to the OS - corresponding to the TDP configuration (including the P state at which the acceleration is steered).

In one embodiment, the OS receives an ACPI notification 230 that causes it to re-evaluate the _PPC object under each logical processor. Depending on the TDP configuration type, the value returned from the _PPC object evaluation can limit the operating system P state control 205 software from being able to use certain P states. When the TDP configuration changes, the highest performance P state allowed by the _PPC object is configured to ignite a P state of the accelerated job.

In accordance with an embodiment, to initialize the configurable TDP 255, the platform BIOS 210 may first detect feature availability. It can then build the OSPM_PSS table with the configurable TDP 255 information it collects from the processor. According to one embodiment, the third figure illustrates an initialization technique. For example, BIOS 310 may first detect that features are available in handler 330. Sex. The BIOS 310 can then construct the OSPM_PSS table in the handler 325 using the configurable TDP information, such as the TDP level and ratio, collected by the handler 335 from the processor/PCU 315.

The BIOS 310 can plan a maximum TDP ratio or a desired TDP ratio, such as the current TDP ratio in the processor/PCU 315 illustrated in the process 340. BIOS 310 may also set _PPC to "0" or a P state corresponding to a desired TDP ratio in process 345 to indicate the allowed P state and report the _PPC table to OSPM 320. In process 355, OSPM 320 can change the P state of processor/PCU 315 to a new maximum P state (depending on the workload). In the process 350, the processor/PCU 315 can be enabled to accelerate if the target ratio is greater than the current P1 ratio. The initialization technique of FIG. 3 and other processing procedures or mechanisms disclosed herein are performed by processing logic, which may include dedicated hardware or be executed by a general purpose machine or by a special purpose machine or a combination of the two. Software or firmware job code.

In one embodiment, there are three possible mechanisms with which the TDP can be changed during runtime. In other embodiments, other techniques or mechanisms may be used to change the TDP during runtime. In one embodiment, the platform may provide the end user 405 with an option to select a designated job mode for the system, and this option may be provided 425 with a hotkey input. In this example, the hotkey action by the user triggers a change in the TDP value during runtime. Figure 4 illustrates a flow of a user initiating a TDP change, in accordance with one embodiment. In the processing program 425, a hotkey input is used to select one for the system. After a new TDP mode of operation, BIOS 410 can plan a new P1 ratio and plan the RAPL power limit to a new TDP point in processor/PCU 415, as illustrated in process 430. BIOS 410 may also set _PPC to a new maximum available P state (new accelerated P state in _PPC) in processing 440 and report the _PSS table to OSPM 420. OSPM 420 may then change the P state of processor/PCU 415 to a new maximum P state (depending on the workload) in process 445. If the target rate is greater than the current P1 ratio, the processor/PCU 415 can be accelerated in the handler 435.

According to one embodiment, a usage model uses platform software to interpret user input and convert it into a BIOS 510 call to motivate TDP changes. Figure 5 illustrates this usage model in accordance with one embodiment. In process 530, event 505 can include a user selection for a new TDP mode via a power-pan setting or a software GUI or a dock, and is triggered by event 505. A change is communicated to the DPTF driver 520. The DPTF driver 520 initiates an ACPI method with a P1 selection that causes an ACPI notification to be issued by the BIOS 510 to the OSPM 515 in the handler 540 to inform it that the _PPC object is to be set to a new maximum available P state (_PPC). The new acceleration P state). The OSPM 515 can then change the P state of the processor/PCU 515 to a new maximum P state (depending on the workload) in the handler 555. The return value from the ACPI object is derived from a value passed by the DPTF driver 520.

In one embodiment, the processor/PCU 525 contains as above Said MSR. Writing to an MSR can carry P-state information about the acceleration and the RAPL power limit value being throttled (acceleration rate) to the processor/PCU 525. Therefore, in process 545, DPTF driver 520 (written via MMIO/MSR) plans a new P1 ratio in processor/PCU 525 to set a new acceleration ratio for processor/PCU 525 (acceleration is motivated) Point) and plan the corresponding RAPL power limit value for the new TDP base frequency point. If the target rate is greater than the current P1 ratio, the processor/PCU 525 can be enabled to accelerate in the process 550.

In some embodiments, the platform may choose not to provide user control to modify the TDP, but instead base this decision on system events (eg, AC to DC switching, or parked versus unparked events, etc.). This model of use is depicted in the sequence shown in Figure 6 in accordance with one embodiment. For example, in handler 625, platform EC 605 notifies BIOS 610 of a new TDP request in accordance with a system event as described above. BIOS 610 can plan a new P1 ratio and plan the RAPL power limit to a new TDP point in processor/PCU 615, as illustrated in process 630. BIOS 610 may also set _PPC to a new maximum available P state (new accelerated P state in _PSS) in handler 635 and report the _PSS table to OSPM 620. The OSPM 620 can then change the P state of the processor/PCU 615 to the new maximum P state (depending on the workload) in the handler 645. If the target rate is greater than the current P1 ratio, the processor/PCU 615 can be accelerated in the handler 640.

In one embodiment, the TDP configuration can be dynamically changed as described above.

In one embodiment, the configurable TDP can interoperate with the platform firmware and the thermal control capabilities of manipulating the ACPI object to ensure that no conflicts occur. In one embodiment, the Run Time Average Power Limit (RAPL) allows one platform to limit the power consumption of the processor. Because the platform can use TDP details as the basis for RAPL restrictions, the fact that TDP dynamically changes can cause the RAPL restrictions to become invalid. For example, consider a situation where the current TDP is 15W and the RAPL limit has been set to 14W by the platform. When the current TDP changes to 23W, the 14W RAPL limit is too restrictive and the processor will not be able to maintain this RAPL limit. In accordance with an embodiment, to address this issue, the RAPL restrictions can be updated to be part of a configurable TDP change during runtime to match the new TDP level.

In one embodiment, the TDP can be configured to map to two platform features (aggregation of interface specifications)). They are the TDP configurability interface (Configuration) and Trigger.

Feature Name: ConfigTDP

Platform Features (PFAS) ConfigTDP

ConfigTDP.Trigger

ConfigTDP.Trigger.app

ConfigTDP.Trigger.driver (DPTF)

ConfigTDP.Trigger.bios

ConfigTDP.Configuration(Interface)

ConfigTDP.Configuration.bios

ConfigTDP.Configuration.driver(DPTF)

ConfigTDP.Configuration.cpu

ConfigTDP.Configuration.GFXDriver

According to one embodiment, some additional features include new and new-purpose processor MSR and graphics driver changes.

Figure 7 illustrates a microprocessor in which at least one embodiment of the present invention can be utilized. In particular, FIG. 7 illustrates a microprocessor 700 having one or more processor cores 705 and 710, each having a local cache 707 and 713 associated therewith, respectively. Also shown in FIG. 7 is a shared cache memory 715 that stores a version of at least some of the information stored in each of the local caches 707 and 713. In some embodiments, the microprocessor 700 can also include other logic not shown in FIG. 7, such as an integrated memory controller, an integrated graphics controller, and others for performing other functions in a computer system. The logic of functions such as I/O control. In one embodiment, various microprocessors in a multiprocessor system or cores in a multi-core processor may include logic 719 or otherwise be associated with logic 719, in accordance with at least one embodiment. Linked to enable flexible configuration of TDP specification technology. This logic may include circuitry, software (embodied in tangible media), or both, to enable more efficient resource allocation among multiple cores or processors than some prior art implementations.

Figure 8, for example, illustrates an embodiment in which the present invention can be used A front-side-bus (FSB) computer system. Any processor 801, 805, 810 or 815 may be from one or more processor cores 823, 827, 833, 837, 843, 847, 853, 857 or otherwise with one or more of the processes Information about any local level one (L1) cache memory 820, 825, 830, 835, 840, 845, 850, 855 associated with the core. Moreover, any processor 801, 805, 810 or 815 may be derived from any of the shared level two (L2) caches 803, 807, 813, 817 or from the system via chipset 865. Information about memory 860. In accordance with at least one embodiment, one or more processors in FIG. 8 may include logic 819 or otherwise be associated with logic 819 to enable resilient configuration of TDP specification techniques.

In addition to the FSB computer system illustrated in Figure 8, other system configurations can be utilized in conjunction with various embodiments of the present invention, including point-to-point (P2P) interconnect systems and loop interconnect systems. For example, the P2P system in FIG. 9 may include a number of processors, of which only two processors, 970, 980, are exemplarily shown. The processors 970, 980 can each include a local memory controller hub (MCH) 972, 982 for connection to the memory 92, 94. Processors 970, 980 can exchange data using PtP interface circuits 978, 988 via a point-to-point (PtP) interface 950. Processors 970, 980 can exchange data with a chipset 990 via point-to-point interface circuits 976, 994, 986, 998 via respective PtP interfaces 952, 954. Chipset 990 can also pass through a high performance graphics interface In 939, data is exchanged with a high performance graphics circuit 938. Several embodiments of the invention may be tied to any processor having any number of processing cores or within each of the PtP bus agents of Figure 9. In one embodiment, any processor core may include or be associated with a cache memory (not shown) or otherwise. In addition, a shared cache (not shown) that is still connected to the processor via the p2p interconnect may be included in any of the two processors so that when one processor is When placed in a new power mode, local cache information for either or both of these processors can be stored in this shared cache. In accordance with at least one embodiment, one or more processors or cores in FIG. 9 may include logic 919 or otherwise be associated with logic 919 to enable resilient configuration of TDP specification techniques.

One or more layers of at least one embodiment may be implemented by means of presentation data stored on a machine readable medium, the presentation data representing or coupling various functional description substances and/or logic within the processor, Reading by a machine causes the machine to fabricate logic for performing the techniques described herein. Such representations, known as "IP cores", can be stored on a tangible machine-readable medium ("tape") and supplied to many customers or manufacturing facilities for loading into actual logic or The processor is manufactured in the machine.

Several embodiments of the invention may be included or applied to any hardware device or portion thereof, including a central processing unit, a graphics processing unit, or other processing logic within a processor or a computer system. Nuclear heart. Several embodiments may be embodied as a tangible machine-readable medium having stored a set of instructions that, when executed by a machine, cause the machine to perform the operations described herein.

To this end, a method and apparatus for directing access to a micro-architectural memory region has been described. The above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent upon reading and understanding the above description. Accordingly, the scope of the invention is to be determined by the scope of the appended claims and the full scope of the equivalents

Claims (15)

A system for configuring thermal design power in a processor, comprising: the processor including a plurality of cores; and a storage controller for communicatively coupling the processor to the storage device; wherein the processor comprises: an integrated type a memory controller for communicatively coupling the processor to the system memory; and logic for setting the processing in a basic input/output system (BIOS) based on a user selection in the user interface a thermal design power (TDP) setting of the device for changing a configurable power limit value for the processor based on the TDP setting, wherein the configurable power limit value is used to limit power consumption of the processor, the logic Used to read the configurable power limit value, and the logic is used to write power state information associated with the configurable power limit value in a first core register, the power state information including for the first core a maximum power state and one of a plurality of power states indicating that the first core is currently operating, wherein the complex power state includes at least one low power state and at least Acceleration (Turbo) mode state. A system as claimed in claim 1, wherein the processor comprises a shared cache. A system as claimed in claim 1, wherein the processor comprises a plurality of core level caches, the core level caches comprising first level (L1) cache memory. For example, the system of claim 1 includes an input/output unit. A system as claimed in claim 1, wherein the processor and the one or more processors comprise a common processor architecture. A system for configuring thermal design power in a processing device, comprising: the processing device comprising a plurality of cores; a system memory operatively coupled to the processing device; and a storage control device operatively coupled to the processing device; An integrated memory control device for communicatively coupling the processing device to system memory; and a logic device for selecting a user based on a user interface in a basic input/output system (BIOS) Setting a thermal design power (TDP) setting for the processing device, the logic device for changing a configurable power limit value for the processing device based on the TDP setting, wherein the configurable power limit value is used to limit the processing device Power consumption, the logic device is configured to read the configurable power limit value, and the logic device is configured to write power state information associated with the configurable power limit value in a register of the first core, the power state The information includes one of a maximum power state for the first core and one of a plurality of power states indicating that the first core is currently operating. In the complex power state comprises at least one low power state and at least one acceleration (Turbo) mode state. For example, the system of claim 6 of the patent scope also includes a shared cache. For example, the system of claim 6 includes a plurality of core level caches, and the core level cache includes first level (L1) cache memory. For example, the system of claim 6 includes an input/output device. A system as claimed in claim 6, wherein the processing device and the one or more other processing devices comprise a common processor architecture. A system for configuring thermal design power in a processor, comprising: a storage controller for communicatively coupling the processor to a storage device; and the processor, the processor comprising: an integrated memory controller Communicating the processor to the system memory communicatively; and logic for setting a thermal design power for the processor based on a user selection in a user interface in a basic input/output system (BIOS) ( a TDP) setting, the logic for changing a configurable power limit value for the processor based on the TDP setting, wherein the configurable power limit value is used to limit power consumption of the processor, the logic is configured to read the Configuring a power limit value, and the logic is to write power state information associated with the configurable power limit value in a register of a core of the processor, the power state information including a maximum power state and indication for the core One of a plurality of power states at which the core is currently operating, wherein the complex power state includes at least one low power state and at least one turbo mode state. A system as claimed in claim 11, wherein the processor comprises a complex core comprising the core, the complex core being coupled to a shared cache. The system of claim 11, wherein the processor comprises a plurality of core level caches, the core level caches comprising first level (L1) cache memory. For example, the system of claim 11 includes an input/output device. For example, the system of claim 11 includes a multiprocessor system.