TWI625946B - Transceiver circuit and control method of receiver circuit - Google Patents

Abstract

This case provides a transmission circuit. The transmission circuit includes a transmission circuit, a reception circuit, a frequency domain analysis circuit, and a DC bias generation circuit, and the reception circuit includes a mixer. The transmitting circuit transmits the test signal, and the mixer of the receiving circuit receives a plurality of predetermined DC bias groups. When the mixer operates in the predetermined DC bias group, the receiving circuit is configured to form a plurality of output signals according to the test signals. The frequency domain analysis circuit converts the output signal into a plurality of frequency domain signals. The DC bias generating circuit generates a function according to the frequency domain signals and the predetermined DC bias group, and generates a first DC bias group according to the function to the mixer.

Description

Transmission circuit and reception circuit control method

The present invention relates to a transmission circuit and a reception circuit control method, and particularly relates to a transmission circuit capable of reducing noise and a reception circuit control method.

In conventional transmission circuits, the signal transmitted by the transmission circuit may cause noise to the receiving circuit. Some of the noise is originally in the out band, but because of the second-order nonlinear effect of the receiving circuit, the extra-frequency noise is coupled to the in-band, causing intra-frequency noise.

Therefore, the related art proposes some methods to solve this problem. For example, the aforementioned problem can be improved by adjusting the DC bias of the mixer in the transmitting circuit. However, the conventional method is usually a binary search method to gradually calculate the DC bias of a suitable mixer, none of which is provided. The mechanism for quickly calculating the DC bias of the mixer requires a large amount of computation time and cost to calculate a suitable DC bias.

One object of the present invention is to provide a transmission circuit and a reception circuit control method, which can calculate the DC bias of an ideal mixer in a simple step.

An embodiment of the present disclosure discloses a transmission circuit including a transmission circuit, a reception circuit, a frequency domain analysis circuit, and a DC bias generation circuit, and the reception circuit includes a mixer. The transmitting circuit transmits a test signal, and the mixer receives a plurality of predetermined DC bias groups. Wherein, when the mixer operates in the predetermined DC bias group, the receiving circuit forms a plurality of output signals according to the test signal. The frequency domain analysis circuit converts the output signal into a plurality of frequency domain signals. The DC bias generating circuit generates a function according to the frequency domain signal and the predetermined DC bias group, and generates a first DC bias group according to the function to the mixer.

Another embodiment of the present disclosure discloses a receiving circuit control method, which is applied to a transmitting circuit, where the transmitting circuit includes a transmitting circuit and a receiving circuit. The receiving circuit contains a mixer. The receiving circuit control method comprises the steps of: transmitting a test signal by the transmitting circuit; receiving a plurality of predetermined DC bias groups by the mixer, wherein the receiving circuit forms a plurality of the test signals according to the test signal when the mixer operates in the predetermined DC bias group Output signals; converting the output signals into a plurality of frequency domain signals; and generating a function according to the frequency domain signal and the predetermined DC bias group, and generating a first DC bias group according to the function to the mixer.

According to the foregoing embodiment, the ideal mixer DC bias can be calculated by a simple calculation step, and the problem that a large amount of calculation is required in the prior art to obtain an ideal mixer DC bias can be improved.

FIG. 1 is a block diagram of a transmission circuit 100 according to an embodiment of the present invention. The transmission circuit 100 includes a transmission circuit 101, a reception circuit 103, a frequency domain analysis circuit 107, a DC bias generation circuit 109, a duplexer 203, and an antenna 204. The reception circuit 103 includes a mixer 105. The transmitting circuit 101 is coupled to the duplexer 203. The receiving circuit 103 is coupled to the duplexer 203, the frequency domain analyzing circuit 107, and the DC bias generating circuit 109. The frequency domain analyzing circuit 107 is coupled to the DC bias circuit 109, and the duplexer 203 is coupled to the antenna 204. The transmitting circuit 101 transmits the test signal TS to the duplexer 203.

The receiving circuit 103 receives the transfer signal output from the duplexer 203. In this embodiment, the transfer signal is a tx leakage signal caused by the transmission circuit 101 transmitting the test signal TS. Since the receiving circuit 103 has a second-order nonlinear effect, even if the transmission leakage signal is frequency (out The band signal, the receiving circuit 103 still generates an output signal OS based on the transmission leakage signal.

The mixer 105 down-converts the signal or the amplified transfer signal based on the DC bias group V_DBG1. For example, the receiving circuit 103 further includes an amplifier (not shown), the amplifier is used to amplify the transfer signal, and the mixer 105 is based on the DC. The output of the biasing group V_DBG1 is down-converted, and then the receiving circuit 103 will generate an output signal OS based on the output of the mixer 105. In some embodiments, the DC bias group V_DBG1 can include at least a DC bias.

The frequency domain analysis circuit 107 converts the output signal OS into a frequency domain signal FS. The frequency domain analysis circuit 107 can be implemented by any circuit capable of converting the time domain signal into a frequency domain signal. For example, the frequency domain analysis circuit 107 can be a fast Fourier transform circuit. It should be noted that the energy of the frequency domain signal FS output by the frequency domain analysis circuit 107 and the DC bias voltage group V_DBG1 received by the mixer 105 are quadratic functions. Therefore, when the mixer 105 operates in a plurality of predetermined DC bias groups, the frequency domain analysis circuit 107 can generate a plurality of frequency domain signals FS corresponding to the test signals TS.

The DC bias generating circuit 109 generates an ideal DC bias group according to the frequency domain signal FS, so that the mixer 105 can be based on the forwarded signal or the amplified transfer signal output by the ideal DC bias group down-converter 203. The duplexer 203 switches the path between the antenna 204 and the transmission circuit 101 and the path between the antenna 204 and the receiving circuit 103.

Furthermore, referring to FIG. 2, FIG. 2 illustrates an embodiment of the transmission circuit 100 in FIG. 1, that is, the transmission circuit 100a. The transmission circuit 101 includes an amplifier 201. Please note that other components of the transmission circuit 101 are not shown here. The receiving circuit 103 includes an amplifier 205, a mixer 105, amplifiers 207, 213, filters 209, 215, gain controllers 211, 217, and analog-to-digital converters 219, 211. The mixer 105 includes mixers Mix_i and Mix_q. In some embodiments, amplifier 205 is a low noise amplifier.

The mixer Mix_i, the amplifier 207, the filter 209, the gain controller 211, and the analog-to-digital converter 219 form an I path. Similarly, mixer Mix_q, amplifier 213, filter 215, gain controller 217, and analog digital converter 221 form a Q path. The frequency domain analysis circuit 107 includes a Fourier transformer 227. The output signals OS of the I path and the Q path are converted by the Fourier converter 227. It should be noted that the circuit shown in FIG. 2 is for example only and is not intended to limit the present invention. In some embodiments, the transmit circuit 100a may not include the amplifier 205, the amplifiers 207, 213, the filters 209, 215, and/or the gain controllers 211, 217.

In one embodiment, the test signal TS is a dual frequency signal having a frequency f_TXLO-f_sig, f_TXLO+f_sig, the frequency f_TXLO is the carrier frequency of the transmission circuit 201, and the frequency f_sig is a predetermined frequency. As described above, since the receiving circuit 103 has a second-order non-ideal effect, the frequency 2*f_sig of the frequency signal FS caused by the test signal TS will fall within the frequency. In some embodiments, the frequency domain analysis circuit 107 can be a single frequency fourier transform circuit, that is, the frequency domain analysis circuit 107 only generates the output signal OS at the frequency 2*f_sig (here, 2*f_sig is called The signal size on the test frequency). In some embodiments, the predetermined frequency f_sig may be determined according to the frequency band used by the receiving circuit 103.

As described above, the DC bias group V_DBG1 may include more than one DC bias. In the embodiment of FIG. 2, the DC bias group V_DBG1 includes an I path DC bias Vi and a Q path DC bias Vq, and another Fourier. The energy of the frequency signal FS output by the converter 227 has a quadratic function relationship with the DC bias group received by the mixer 105. Therefore, in an embodiment, the frequency signal FS output by the Fourier converter 227 is at the test frequency 2 *f_sig signal size P (the energy of frequency signal FS is |P| ² ) can be expressed as a function, that is, P(Vi, Vq)=miVi+mqVq+P(Vi=0, Vq=0), where P(Vi =0, Vq=0) is the signal size of the frequency signal FS output by the Fourier transformer 227, and mi and mq are coefficients when Vi and Vq are 0 when the transmission circuit 101 transmits the test signal TS. Therefore, if mi and mq in the function are obtained, the relationship P(Vi, Vq) between the output of the Fourier transformer 227 and the I-path DC bias Vi and the Q-path DC bias Vq can be known. In the present embodiment, the DC bias generating circuit 109 sets a predetermined DC bias group, so that the DC bias generating circuit 109 can calculate mi and mq according to the frequency domain signal FS to generate an ideal I-path DC bias and Q path. DC bias, the ideal DC bias group.

In one embodiment, the DC bias generating circuit 109 sets five sets of predetermined DC bias groups such that the DC bias generating circuit 109 can calculate mi and mq according to the corresponding frequency domain signal FS. It should be noted, however, that the aforementioned quadratic function may be different due to the structural difference of the mixer 105. Therefore, different sets of predetermined DC bias groups may be required to find the DC bias group and the frequency domain analysis circuit 107. The relationship of the output frequency signal FS. In this embodiment, the five sets of predetermined DC bias groups are the following combinations:

First DC bias group (Vi_0, Vq_0) = (-Vo, 0)

Second DC bias group (Vi_1, Vq_1) = (Vo, 0)

The third DC bias group (Vi_2, Vq_2) = (0, -Vo)

The fourth DC bias group (Vi_3, Vq_3) = (0, Vo)

Fifth DC bias group (Vi_4, Vq_4) = (0, 0)

Where Vo is a predetermined voltage, which can be selected according to the structure of the transmission circuits 100, 100a.

The following describes how to calculate mi, mq in P(Vi, Vq)=miVi+mqVq+P(Vi=0, Vq=0) according to the above five groups of DC bias groups and corresponding frequency domain signals FS. P (Vi = 0, Vq = 0).

According to the first DC bias group and the second DC bias group, mi can be estimated:

P_0 and P_1 are signal sizes corresponding to the frequency domain signal FS of the first DC bias group and the second DC bias group at the test frequency 2*f_sig.

According to the third DC bias group and the fourth DC bias group, mq can be estimated:

Wherein P_2 and P_3 are signal sizes corresponding to the frequency domain signal FS of the third DC bias group and the fourth DC bias group at the test frequency 2*f_sig.

According to the fifth DC bias group, P (Vi = 0, Vq = 0) can be estimated:

............... (Formula 3)

Wherein P_4 corresponds to the signal size of the frequency domain signal FS of the fifth DC bias group at the test frequency 2*f_sig

Next, the estimation results of mi, mq, and P(Vi=0, Vq=0) are substituted into P(Vi, Vq)=miVi+mqVq+P(Vi=0, Vq=0), and the ideal DC bias is assumed. The group is the first ideal DC bias group (Vi_opt1, Vq_opt1), so that P(Vi_opt1, Vq_opt1)=0+0j, that is, the frequency signal FS caused by the test signal TS is equal to zero, and then (Formula 4) is obtained.

......... (Formula 4)

The first ideal DC bias group (Vi_opt1, Vq_opt1) can be obtained by processing the real part and the imaginary part of (Formula 4) in a simultaneous equation.

In addition, the first ideal DC bias group (Vi_opt1, Vq_opt1) can replace the aforementioned fifth DC bias group as another predetermined DC bias group, and P(Vi, Vq)=miVi+mqVq+P( Vi=0, Vq=0) is changed to P(Vi, Vq)=miVi+mqVq+P(Vi=Vi_opt1, Vq=Vq_opt1), and the second ideal DC bias group is obtained. In more detail, the Fourier converter 227 can generate a corresponding frequency domain signal FS according to another predetermined DC bias group, and the DC bias generating circuit 109 can according to the signal size P_0 of the frequency domain signal FS at the test frequency 2*f_sig. , P_1, P_2, P_3, P (Vi=Vi_opt1, Vq=Vq_opt1) and (Formula 4) to obtain a second ideal DC bias group. Another predetermined DC bias group is as follows:

First DC bias group (Vi_0, Vq_0) = (-Vo, 0)

Second DC bias group (Vi_1, Vq_1) = (Vo, 0)

The third DC bias group (Vi_2, Vq_2) = (0, -Vo)

Fourth DC bias group (Vi_3, Vq_3) = (0, Vo)

The first ideal DC bias group (Vi_4, Vq_4) = (Vi_opt1, Vq_opt1)

Please also note that the aforementioned iterative process can be repeated continuously so that the DC bias generating circuit 109 can generate an updated ideal DC bias group.

FIG. 3 is a flow chart of a method for calculating a DC bias group according to an embodiment of the present invention, which can be applied to the transmission circuits 100 and 100a of the first and second figures, respectively, and includes the following steps.

Step 301: Start.

Step 303: Set the iteration number itr_num and set the iteration index i to 1.

Step 305: Set the test signal TS, and set the predetermined DC bias group to five groups of DC bias groups (-Vo, 0), (Vo, 0), (0, -Vo), (0, Vo), ( 0, 0), and get the signal size P_0, P_1, P_2, P_3, P_4 of the corresponding frequency domain signal FS on the test frequency 2*f_sig.

Step 307: Calculate a DC bias group (Vi_tmp, Vq_tmp) according to P_0, P_1, P_2, P_3, and P_4. Note that the DC bias group (Vi_tmp, Vq_tmp) here is the first ideal DC bias group (Vi_opt1, Vq_opt1) described above.

Step 309: Determine whether the iteration index i is equal to the iteration number itr_num, and if yes, go to step 311; if no, go to step 313.

Step 311: Supply the DC bias group (Vi_tmp, Vq_tmp) to the mixer 105.

Step 313: The DC bias group (Vi_tmp, Vq_tmp) is supplied to the mixer 105, and the frequency domain signal FS corresponding to the DC bias group (Vi_tmp, Vq_tmp) is obtained on the test frequency 2*f_sig in the frequency domain analysis circuit 107. Signal size P_tmp

Step 315: Calculate a DC bias group (Vi_itr, Vq_itr) according to P_0, P_1, P_2, P_3, P_tmp, and set a DC bias group (Vi_tmp, Vq_tmp) to a DC bias group (Vi_itr, Vq_itr), and i The value of the plus one. In some embodiments, the DC bias group (Vi_tmp, Vq_tmp) can also be set to a DC bias group (Vi_itr+Vi_tmp, Vq_itr+Vq_tmp).

Step 317: End

Fig. 4 is a view showing an embodiment of the DC bias generating circuit 109 in Fig. 1. The DC bias generating circuit 109 includes subtractors S_1-S_6, an adder A_1, multipliers M_1-M_6, arithmetic circuits PW_1 and PW_2, and long dividing circuits LD_1 and LD_2. The arithmetic circuits PW_1 and PW_2 are used to multiply the input signal Here, Vo is Vo in the aforementioned predetermined DC bias group. The long dividing circuits LD_1 and LD_2 perform long division on the signals input to the long dividing circuits LD_1 and LD_2.

The input end of the subtracter S_1 receives the real signal P_1r corresponding to the frequency domain signal P_1 of the second DC bias group, and the subtraction terminal receives the real signal P_0r corresponding to the frequency domain signal P_0 of the first DC bias group. The input end of the subtracter S_2 receives the imaginary part signal P_1i of the frequency domain signal P_1, and the subtraction end receives the imaginary part signal P_0i of the frequency domain signal P_0. The input end of the subtracter S_3 receives the real signal P_3r corresponding to the frequency domain signal P_3 of the fourth predetermined DC bias group, and the subtraction end receives the real signal P_2r corresponding to the frequency domain signal P_2 of the third predetermined DC bias group. . The input end of the subtracter S_4 receives the imaginary part signal P_3i of the frequency domain signal P_3, and the subtraction end receives the imaginary part signal P_2i of the frequency domain signal P_2.

The first input end of the multiplier M_1 is coupled to the output end of the first subtractor S_1, and the second input end receives the imaginary part signal P_4i corresponding to the frequency domain signal P_4 of the fifth predetermined DC bias group, or the second input end The imaginary part signal P_tmp1i corresponding to the frequency domain signal P_tmp1 of the first ideal DC bias group may also be received. The first input end of the multiplier M_2 is coupled to the output end of the subtractor S_2, the second input end receives the real signal P_4r of the frequency domain signal P_4, or the second input end thereof can also receive the real part of the ideal frequency domain signal P_tmp1 Signal P_tmp1r. The first input end of the multiplier M_3 is coupled to the output end of the first subtractor S_1, and the second input end is coupled to the output end of the subtracter S_4. The first input end of the multiplier M_4 is coupled to the output end of the subtractor S_2, and the second input end is coupled to the output end of the subtractor S_3. The first input end of the multiplier M_5 is coupled to the output end of the subtracter S_4, the second input end receives the real signal P_4r of the frequency domain signal P_4, or the second input end thereof receives the real signal of the ideal frequency domain signal P_tmp1 P_tmp1r. The first input end of the multiplier M_6 is coupled to the output end of the subtracter S_3, the second input end receives the imaginary part signal P_4i of the frequency domain signal P_4, or the second input end thereof receives the imaginary part signal of the ideal frequency domain signal P_tmp1 P_tmp1i.

The first input end of the adder A_1 is coupled to the output end of the multiplier M_1, the second input end is coupled to the output end of the multiplier M_2, and the output end of the adder A_1 is coupled to the arithmetic circuit PW_1. The input end of the subtracter S_5 is coupled to the output end of the multiplier M_6, the subtraction end is coupled to the output end of the multiplier M_5, and the output end of the subtracter S_5 is coupled to the arithmetic circuit PW_2. The input end of the subtracter S_6 is coupled to the output end of the multiplier M_3, the subtraction end is coupled to the output end of the multiplier M_4, and the output end of the subtracter S_6 is coupled to the long dividing circuit LD_2.

The calculation effect of the above (Formula 4) can be achieved by the circuit configuration of FIG. However, the circuit configuration shown in FIG. 4 is for illustrative purposes only and is not intended to limit the invention.

According to the foregoing embodiment, a receiving circuit control method as shown in FIG. 5 can be obtained, which is used in a transmitting circuit, the transmitting circuit includes a transmitting circuit and a receiving circuit, and the receiving circuit includes a mixer, and the signal output by the receiving circuit is The energy at the test frequency has a quadratic functional relationship with the DC bias group received by the mixer. The receiving circuit control method includes the following steps:

Step 501: Generate a test signal to the output of the transmission circuit.

Step 503: respectively generate a frequency domain signal of the output signal formed by the test signal to the receiving circuit when the mixer operates on a plurality of different predetermined DC bias groups.

Step 505: Generate a first ideal DC bias group to the mixer according to the frequency domain signal and the predetermined DC bias group.

The detailed steps of the receiving circuit control method can be derived from the foregoing embodiments, and thus will not be described again.

In summary, the present case can calculate the ideal mixer DC bias in a simple calculation step, which can improve the problem that a large amount of calculation is required in the prior art to obtain an ideal DC bias of the mixer.

100, 100a transmission circuit 101 transmission circuit 103 reception circuit 105 mixer 107 frequency domain analysis circuit 109 DC bias generation circuit 201, 205, 207, 213 amplifier 203 duplexer 204 antenna 209, 215 filter 211, 217 gain Controller 219, 221 Analog-to-digital converter 227 Fourier converter Mix_i and Mix_q Mixer S_1~S_6 Adder A_1 Adder M_1~M_6 Multiplier PW_1, PW_2 Operation circuit LD_1, LD_2 Long division circuit

FIG. 1 is a block diagram of a transmission circuit according to an embodiment of the present invention. Fig. 2 is a view showing an embodiment of the transmission circuit in Fig. 1. FIG. 3 is a flow chart of a method for calculating a DC bias group according to an embodiment of the present invention. Fig. 4 is a view showing an embodiment of the DC bias generating circuit of Fig. 1. FIG. 5 is a flow chart of a receiving circuit control method according to an embodiment of the present disclosure.

Claims (10)

A transmission circuit comprising: a transmission circuit for transmitting a test signal; a receiving circuit comprising a mixer for receiving a plurality of predetermined DC bias groups, wherein the mixer operates In the predetermined DC bias group, the receiving circuit is configured to form a plurality of output signals according to the test signal; a frequency domain analysis circuit for converting the output signals into a plurality of frequency domain signals; and a DC bias voltage And generating a circuit for generating a function according to the frequency domain signals and the predetermined DC bias groups, and generating a first DC bias group according to the function to the mixer. The transmission circuit of claim 1, wherein the mixer has a first mixer corresponding to an I path and a second mixer corresponding to a Q path, each of the predetermined DC bias groups Each includes a predetermined I path DC bias and a predetermined Q path DC bias; and the function is P(Vi, Vq)=miVi+mqVq+P (Vi=0, Vq=0), Vi represents the first The DC bias received by the mixer, Vq represents the DC bias received by the second mixer, and P(Vi, Vq) is the frequency domain output by the frequency domain analysis circuit when the mixer receives Vi and Vq. The signal is at the signal frequency of the test frequency. When P (Vi=0, Vq=0) is Vi and Vq is 0, the frequency domain signal output by the frequency domain analysis circuit is the signal size of the test frequency, and mi and mq are a coefficient; the DC bias generating circuit calculates the mi and mq in the function according to the frequency domain signals and the predetermined DC bias groups, and then calculates a first I path DC bias according to the function and a The first Q path DC bias is used as the first DC bias group, wherein the test signal determines the test frequency. The transmission circuit of claim 1, wherein the frequency domain analysis circuit operates separately on the mixer The frequency domain signals are output when the five groups of different predetermined DC bias groups are generated, and the DC bias generating circuit generates the function according to the frequency domain signals and the predetermined DC bias groups. The transmission circuit of claim 2, wherein the predetermined DC bias groups comprise a first and a second predetermined DC bias group, the predetermined I path DC bias of the first predetermined DC bias group The predetermined Q path DC bias voltage is (-Vo, 0), respectively, and the predetermined I path DC bias voltage of the second predetermined DC bias group and the predetermined Q path DC bias voltage are respectively (Vo, 0), wherein Vo is a predetermined voltage. The transmission circuit of claim 2, wherein the predetermined DC bias groups comprise a third and a fourth predetermined DC bias group, and the predetermined I path DC bias voltage of the third predetermined DC bias group is The predetermined Q path DC bias voltage is (0, -Vo), respectively, and the predetermined I path DC bias voltage of the predetermined fourth DC bias group and the predetermined Q path DC bias voltage are respectively (0, Vo), where Vo It is a predetermined voltage. The transmission circuit of claim 2, wherein the predetermined DC bias groups comprise a fifth predetermined DC bias group, the predetermined I path DC bias of the fifth predetermined DC bias group and the predetermined Q path The DC bias voltage is 0. The transmission circuit of claim 1, wherein the DC bias generating circuit generates the first DC bias group to the mixer, the frequency domain analyzing circuit operates at the first straight And outputting a first frequency domain signal, wherein the DC bias generating circuit is further configured to generate a second DC bias group according to the first frequency domain signal and the function to the mixer. A receiving circuit control method is applied to a transmitting circuit, the transmitting circuit includes a transmitting circuit and a receiving circuit, the receiving circuit includes a mixer, and the receiving circuit control method includes: Transmitting, by the transmitting circuit, a test signal; receiving, by the mixer, a plurality of predetermined DC bias groups, wherein when the mixer operates in the predetermined DC bias groups, the receiving circuit forms a complex number according to the test signal And outputting the output signals into a plurality of frequency domain signals; and generating a function according to the frequency domain signals and the predetermined DC bias groups, and generating a first DC bias group according to the function Mixer. The receiving circuit control method according to claim 8, wherein the mixer has a first mixer corresponding to an I path and a second mixer corresponding to a Q path, each of the predetermined DC bias groups One includes a predetermined I path DC bias and a predetermined Q path DC bias; the function is P(Vi, Vq)=miVi+mqVq+P (Vi=0, Vq=0), and Vi represents the first The DC bias received by the mixer, Vq represents the DC bias received by the second mixer, and P(Vi, Vq) is the frequency domain output by the frequency domain analysis circuit when the mixer receives Vi and Vq. The signal is at the signal frequency of the test frequency. When P (Vi=0, Vq=0) is Vi and Vq is 0, the frequency domain signal output by the frequency domain analysis circuit is the signal size of the test frequency, and mi and mq are a coefficient; the test signal determines the test frequency; and the step of generating the first DC bias group includes: generating mi and mq of the function according to the frequency domain signals and the predetermined DC bias groups, and according to the function A first I path DC bias voltage and a first Q path DC bias voltage are calculated as the first DC bias voltage group. The receiving circuit control method of claim 8, further comprising: generating a second DC bias group to the mixer according to a first frequency domain signal and the function, wherein the mixer operates in the first In the DC bias group, the receiving circuit generates a first output signal according to the test signal, and the first output signal is frequency-converted to become the first frequency domain signal.