TWI625634B - Method for estimating stress of electronic component - Google Patents

Abstract

A stress estimation method for electronic components. An electronic component is provided, including a first element, a second element and a plurality of conductive bumps, each conductive bump has two surfaces, the two surfaces are connected to the first and second elements respectively, and between two adjacent conductive bumps With spacing, these conductive bumps include a first conductive bump and a plurality of second conductive bumps. The stress value of the first conductive bump under a test condition parameter is calculated. The stress value of each second conductive bump under the test condition parameters is calculated according to a first calculation formula, the first calculation formula is , Σ ₂ is the stress value of each second conductive bump, L is the straight-line distance between each second conductive bump and the first conductive bump, D is the average of these spacings of these conductive bumps, r is each The radius of the surface, σ ₁ is the stress value of the first conductive bump.

Description

Electronic component stress estimation method

The invention relates to a stress estimation method of an electronic component, and in particular to a propagating stress estimation method of an electronic component.

In the semiconductor packaging process, the wafer is usually disposed on the substrate, and conductive bumps (such as solder balls) are often used as the bonding medium between the wafer and the substrate. Although the bonding method of conductive bumps is low in cost and easy to manufacture, the thermal expansion coefficient of the bonding interface is different, and the fatigue effect caused by the repeated changes in temperature or voltage during system operation is the main cause of the failure of the wafer bonding points. Fatigue damage can be divided into mechanical fatigue damage or thermal fatigue damage. Mechanical fatigue damage is caused by continuous deformation and movement, resulting in a reduction in mechanical strength. Thermal fatigue failure is due to poor matching of the thermal expansion coefficients between the two interfaces, resulting in small deformations at high and low temperatures and pulling each other, which is prone to interface peeling under long-term influence. As a result, both the chip and the underlying substrate will be damaged, which will result in a reduction in the performance and reliability of the chip packaging structure.

According to the above, most of the current finite element simulations are used to estimate the stress generated by conductive bumps in semiconductor packages under specific temperature or voltage changes. Furthermore, the life of the conductive bump is estimated. However, the calculation process of the finite element simulation is complicated and will consume a lot of calculation time. Therefore, how to quickly estimate the stress and lifetime of conductive bumps in semiconductor packages is an important issue in the art.

The invention provides a stress estimation method of an electronic component, which can quickly estimate the diffusion stress of the conductive bump of the electronic component.

The stress estimation method of the electronic component of the present invention includes the following steps. An electronic component is provided, including a first element, a second element, and a plurality of conductive bumps, wherein each conductive bump has two opposite surfaces, and the two surfaces are respectively connected to the first element and the second element. There is a gap between adjacent conductive bumps. The conductive bumps include a first conductive bump and a plurality of second conductive bumps. The stress value of the first conductive bump under a test condition parameter is calculated. Calculate the stress value of each second conductive bump under the test condition parameters according to a first calculation formula, where the first calculation formula is , Σ ₂ is the stress value of each second conductive bump, L is the straight-line distance between each second conductive bump and the first conductive bump, D is the average of these spacings of these conductive bumps, r is each The radius of the surface, σ ₁ is the stress value of the first conductive bump.

Based on the above, in the stress estimation method of the present invention, the first calculation formula The estimation concept is that the stress on the conductive bumps will gradually diffuse and accumulate around the second conductive bumps around the first conductive bumps, so the second conductive bumps farther away from the first conductive bumps, their The greater the cumulative diffusion stress. According to this concept, the present invention first calculates the stress value σ ₁ of the single conductive bump (ie the first conductive bump) in the electronic component according to the set test condition parameters, and then substitutes the stress value σ ₁ into the The stress value σ ₂ of the other conductive bumps (that is, the second conductive bumps) related to this test condition parameter can be calculated by a calculation formula. In this way, it is possible to quickly calculate the stress values of all conductive bumps and efficiently estimate the life of electronic components without using the finite element simulation which is complicated in the calculation process and consumes a large amount of calculation time.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

100、100’‧‧‧Electronic components

110‧‧‧The first component

110a, 120a‧‧‧periphery

120‧‧‧Second component

130‧‧‧conductive bump

132‧‧‧First conductive bump

134‧‧‧Second conductive bump

140‧‧‧Packing colloid

D‧‧‧spacing

h‧‧‧Distance

LT‧‧‧Life

r‧‧‧radius

S‧‧‧Surface

S602~S606‧‧‧Step

FIG. 1 is a top view of an electronic component according to an embodiment of the invention.

2 is a cross-sectional view of the electronic component of FIG. 1 taken along line I-I.

3 is a flowchart of a stress estimation method of an electronic component according to an embodiment of the invention.

FIG. 4 illustrates the test conditions of FIG. 3.

FIG. 5 illustrates the creep strain rate of the second conductive bump of FIG. 1 changing with time.

6 is a partial cross-sectional view of an electronic component according to another embodiment of the invention.

Please refer to FIGS. 1 to 3. The steps of the stress estimation method of the electronic component in this embodiment are as follows. First, an electronic component 100 as shown in FIGS. 1 and 2 is provided. The electronic component 100 includes a first element 110, a second element 120, and a plurality of conductive bumps 130. Each conductive bump 130 has two opposing surfaces S , The two surfaces S are connected and contacted respectively The radius of each surface of the first element 110 and the second element 120 is r. There is a gap between each conductive bump 130 and another adjacent conductive bump 130, and the average value of the gaps of these conductive bumps 130 is D (step S602).

In this embodiment, the electronic component 100 is, for example, a semiconductor structure, and the first element 110 and the second element 120 are, for example, substrates and wafers in the semiconductor structure. However, the invention is not limited to this. In addition, in this embodiment, the conductive bumps 130 are arranged at equal intervals, for example, so that the pitch values of the conductive bumps 130 are all D. However, the present invention is not limited to this. In other embodiments, the conductive bumps 130 may be arranged irregularly and have various pitches with different sizes, and the average value of these pitches is D.

To facilitate the description of the stress estimation method of this embodiment, the conductive bump 130 is divided into a first conductive bump 132 in the center and a plurality of second conductive bumps 134 surrounding the first conductive bump 132. That is, the conductive bump 130 includes a first conductive bump 132 and a plurality of second conductive bumps 134; the first conductive bump 132 is, for example, a conductive bump located at the geometric center of the electronic component 100, and the second conductive bump 134 is distributed between the first conductive bump 132 and the peripheral edge of the electronic component 100, for example, the peripheral edge 110 a of the first element 110 or the peripheral edge 120 a of the second element 120.

Next, the stress value σ _{1 of the} first conductive bump 132 related to a test condition parameter is calculated (step S604), for example, the test condition parameter is based on the application of temperature cycling, voltage cycling, or other types of test conditions to the electronic component 100 The set parameters are not limited by the present invention. That is, the test condition parameter in this embodiment may be a temperature change amount, a voltage change amount, or other test condition value change amounts. Then, based on the calculated stress values of the first conductive bump 132 σ _1, according to a first calculation equation was calculated for each of the second conductive bumps 134 associated with the stress test condition parameter σ _2, wherein the first computing The formula is , Σ ₂ is the stress value of each second conductive bump 134 as described above, L is the linear distance between each second conductive bump 134 and the first conductive bump 132 as described above, and D is the conductive value as described above The average value of the pitches of the bumps 130, r is the radius of each surface S as described above, and σ ₁ is the stress value of the first conductive bump 132 as described above (step S606).

The estimation concept of the first calculation formula is that the stress on the conductive bump 130 will gradually diffuse and accumulate toward the surrounding second conductive bumps 134 around the first conductive bump 132, so the farther away from the first conductive bump 132 The second conductive bump 134 has a larger cumulative diffusion stress. According to this concept, the present embodiment first calculates the stress value σ ₁ of the single conductive bump 130 (ie the first conductive bump 132) in the electronic component 100 according to the set test condition parameters, and then substitutes the stress value σ ₁ into the above The first calculation formula can be used to calculate the stress value σ ₂ of the other conductive bumps 130 (ie, the second conductive bumps 134) related to the test condition parameter. In this way, without using the finite element simulation which is complicated in the calculation process and consumes a large amount of calculation time, the stress values of all conductive bumps 130 can be quickly calculated to efficiently estimate the life of the electronic component 100.

In step S604 shown in FIG. 3, for example, the stress value σ _{1 of the} first conductive bump 132 relative to the test condition parameter is calculated according to a second calculation formula, where the second calculation formula is , E _solder is the Young's coefficient of each conductive bump 130, For the Poisson's ratio of each conductive bump 130, Δα is the difference between the thermal expansion coefficients of the first element 110 and the second element 120, and h is the distance between the first element 110 and the second element 120. In addition, ΔT is a test condition parameter that is set according to the application of temperature cycling, voltage cycling, or other types of test conditions to the electronic component 100, which will be exemplified below with reference to FIG. 4.

As shown in FIG. 4, the test condition of this embodiment is to apply a temperature cycle change to the electronic component 100, and the ΔT is a parameter that is set according to this temperature cycle change. The cycle of this temperature cycle change is, for example, 60 minutes, and the highest temperature and the lowest temperature thereof are 125 degrees Celsius and -40 degrees Celsius, respectively. In other embodiments, the temperature cycle change may be set to other appropriate periods, other appropriate temperature change amounts and temperature values, which are not limited by the present invention. In addition, the test conditions can also be changed to apply voltage cycling changes or other types of test conditions to the electronic component 100, and the test condition parameters are set accordingly, which is not limited by the present invention.

The estimation concept of the first calculation formula in step S606 shown in FIG. 3 is described in detail below. For ease of explanation, the coordinate position and stress value σ ₁ of the first conductive bump 132 at the intersection of the X axis and the Y axis in FIG. 1 are defined as (0, 0) and σ ₍₀ , ₀₎ , respectively, the X axis and Y The coordinate position and stress value σ ₂ of each second conductive bump 134 in the two-dimensional coordinates formed by the axis are defined as ( i , j ) and σ _{( i, j )} , respectively, where each second conductive bump on the X axis The stress value σ ₂ of the block 134 is σ _{( i, 0)} , and the stress value σ ₂ of each second conductive bump 134 on the Y axis is σ _{(0 , j )} . The larger the absolute value of i or the absolute value of j is , the farther the corresponding second conductive bump 134 is from the first conductive bump 132. According to the above, the stress on the conductive bump 130 will gradually diffuse and accumulate around the second conductive bumps 134 around the first conductive bump 132, so that the second conductive bump farthest from the first conductive bump 132 Block 134 accumulates larger stresses, so σ _{( i, 0) can be} approximated as N ₁ σ _{(0 , 0)} and σ _{(0 , j )} as N ₂ σ _{(0 , 0)} , σ The geometric relationship of _{( i,j )} is , Where N ₁ and N ₂ are equal to and △x is equal to the distance from the corresponding second conductive bump 134 on the X axis to the first conductive bump 132, and △y is equal to the distance from the corresponding second conductive bump 134 on the Y axis to the first conductive bump 132 distance. Derivation of the calculation formula according to the above approximation can get the calculation formula , Which is equivalent to the first calculation formula in step S606 shown in FIG. 3

In this embodiment, the life of each second conductive bump 134 is estimated based on the stress value σ _{2 of} each second conductive bump 134, as follows. Based on the stress value σ _{2 of} each second conductive bump 134, the creep strain rate of each second conductive bump is calculated according to a third calculation formula, where the third calculation formula is , Ε is the creep strain rate of each second conductive bump, , D _{L 0} is the lattice diffusion constant, d is the grain diameter, Q _NH is the hole migration chemical energy in the form of Nabe-Xiling, D _{G 0} is the grain boundary diffusion constant, δ is the equivalent grain boundary width, Q _C It is the chemical energy of hole transport in the form of Cobb, Q _f is the chemical energy of hole formation, k is the Bozeman constant, Ω is the atomic volume, P is the number of test condition periods, η is the percentage of test condition period percentage, T ( t )and Test condition function. Among them, T ( t ) and For example, it is a function corresponding to the test conditions shown in FIG. 4, the single cycle of the temperature cycle function in FIG. 4 is 60 minutes and is divided into four 15-minute single temperature condition sections, that is, the length of time of the single temperature condition section It is 0.25 times the length of a single cycle, and the test condition period percentage parameter η is defined as 0.25 accordingly.

FIG. 5 illustrates the creep strain rate of the second conductive bump of FIG. 1 changing with time. According to the above third calculation formula, the creep strain rate ε of each second conductive bump 134 at each time point can be calculated, which is, for example, as shown in FIG. 5, and the life of each second conductive bump 134 can be determined according to this. For example, when the creep strain rate ε of the second conductive bump 134 rises to 50%, it is regarded as a failure, so its life can be estimated as the corresponding LT.

The following are estimated based on the above-described embodiment of the conductive bumps life and the actual results of the comparison table, wherein, for example, is equal to 22 GPa E _solder, Equal to 0.35, D equal to 1 mm, h equal to 0.12 mm, △α equal to 17.6ppm/℃, and estimate and experiment in accordance with the test conditions shown in Figure 4, and the coordinates (2, 2), (4, 3), (6, 5) the second conductive bump 134 is estimated and compared with the experimental results.

It can be seen from the comparison table above that the life expectancy of the conductive bump estimated by the above method of this embodiment is not much different from the actual experimental results and is expected.

6 is a partial cross-sectional view of an electronic component according to another embodiment of the invention. The difference between the electronic component 100' shown in FIG. 6 and the electronic component 100 shown in FIG. 2 is that the electronic component 100' further includes an encapsulant 140, which is disposed between the first element 110 and the second element 120 and covers these Conductive bump 130. Based on the difference in this configuration, a fourth calculation formula is substituted for the first calculation formula to calculate the stress value σ _{2 of} each second conductive bump 134 related to the test condition parameter, wherein the fourth calculation formula is , E _underfill is the Young's coefficient of the encapsulating colloid, α _underfill is the thermal expansion coefficient of the encapsulating colloid, and the definitions of D, r, L, E _solder , α _solder , and ΔT are as described above.

In summary, in the stress estimation method of the present invention, the first calculation formula The estimation concept is that the stress on the conductive bumps will gradually diffuse and accumulate around the second conductive bumps around the first conductive bumps, so the second conductive bumps farther away from the first conductive bumps, their The greater the cumulative diffusion stress. According to this concept, the present invention first calculates the stress value σ ₁ of the single conductive bump (ie the first conductive bump) in the electronic component according to the set test condition parameters, and then substitutes the stress value σ ₁ into the A calculation formula can be used to calculate the stress value σ ₂ of the other conductive bumps (that is, the second conductive bumps) related to the test condition parameter. In this way, it is possible to quickly calculate the stress values of all conductive bumps and efficiently estimate the life of electronic components without using the finite element simulation, which is complicated in the calculation process and consumes a large amount of calculation time.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

Claims (7)

An electronic component stress estimation method includes: providing an electronic component including a first element, a second element and a plurality of conductive bumps, wherein each of the conductive bumps has two opposite surfaces, and each of the surfaces is circular , The two surfaces are respectively connected to the first element and the second element, and each conductive bump has a distance from the adjacent another conductive bump, the conductive bumps include a first conductive bump and A plurality of second conductive bumps; calculating the stress value of the first conductive bump related to a test condition parameter; and calculating the stress value of each second conductive bump related to the test condition parameter according to a first calculation formula, Where the first calculation formula is

, Σ ₂ is the stress value of each second conductive bump, L is the linear distance between each second conductive bump and the first conductive bump, D is the average of the spacing of the conductive bumps Value, r is the radius of each surface, and σ ₁ is the stress value of the first conductive bump. The estimation method as described in item 1 of the patent application scope, wherein the first conductive bump is located at the geometric center of the electronic component. The estimation method as described in item 1 of the patent application scope, wherein the test condition parameter is a temperature change amount or a voltage change amount. The estimation method according to item 1 of the patent application scope, wherein the step of calculating the stress value of the first conductive bump relative to the test condition parameter includes: calculating the first conductive bump related to the stress according to a second calculation formula The stress value of the test condition parameter, where the second calculation formula is

, E _solder is the Young's coefficient of each conductive bump,

Is the Poisson's ratio of each conductive bump, Δα is the difference between the thermal expansion coefficient of the first element and the second element, h is the distance between the first element and the second element, △ T is the test condition parameter. The estimation method as described in item 1 of the patent application scope further includes: estimating the life of each second conductive bump according to the stress value of each second conductive bump. The estimation method as described in item 5 of the patent application scope, wherein the step of estimating the life of each second conductive bump according to the stress value of each second conductive bump includes: calculating each second according to a third calculation formula The creep strain rate of the conductive bump, where the third calculation formula is

, Ε is the creep strain rate of each second conductive bump,

, D _{L O} is the lattice diffusion constant, d is the grain diameter, Q _NH is the hole migration chemical energy in the form of Nabe-Xiling, D _{G O} is the grain boundary diffusion constant, δ is the equivalent grain boundary width, Q _C It is the chemical energy of hole transport in the form of Cobb, Q _f is the chemical energy of hole formation, k is the Bozeman constant, Ω is the atomic volume, P is the number of test condition periods, η is the test condition period percentage parameter, T ( t )and

It is a test condition function; and the life of each second conductive bump is determined according to the creep strain rate of each second conductive bump. The estimation method as described in item 1 of the patent application scope, wherein if the electronic component further includes an encapsulant, the encapsulant is disposed between the first element and the second element and covers the conductive bumps, then A fourth calculation formula replaces the first calculation formula to calculate the stress value of each second conductive bump related to the test condition parameter, wherein the fourth calculation formula is

, E _solder is the Young's coefficient of each conductive bump, α _solder is the thermal expansion coefficient of each conductive bump, E _{underfill is} the Young's coefficient of the packaging colloid, α _{underfill is} the thermal expansion coefficient of the packaging colloid, △T is The test condition parameters.