TWI622878B - 用於在非統一記憶體架構中提供改進延遲的電腦程式、系統和方法（一） - Google Patents

用於在非統一記憶體架構中提供改進延遲的電腦程式、系統和方法（一） Download PDF

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Publication number
TWI622878B
TWI622878B TW104140795A TW104140795A TWI622878B TW I622878 B TWI622878 B TW I622878B TW 104140795 A TW104140795 A TW 104140795A TW 104140795 A TW104140795 A TW 104140795A TW I622878 B TWI622878 B TW I622878B
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Taiwan
Prior art keywords
volatile memory
page
memory device
physical
local volatile
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TW104140795A
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English (en)
Chinese (zh)
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TW201633143A (zh
Inventor
莫利史蒂芬亞瑟
千德斯特塔密歐
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高通公司
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Publication of TW201633143A publication Critical patent/TW201633143A/zh
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Publication of TWI622878B publication Critical patent/TWI622878B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/254—Distributed memory
    • G06F2212/2542—Non-uniform memory access [NUMA] architecture

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW104140795A 2014-12-04 2015-12-04 用於在非統一記憶體架構中提供改進延遲的電腦程式、系統和方法（一） TWI622878B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/560,290 US9575881B2 (en) 2014-12-04 2014-12-04 Systems and methods for providing improved latency in a non-uniform memory architecture
US14/560,290 2014-12-04

Publications (2)

Publication Number Publication Date
TW201633143A TW201633143A (zh) 2016-09-16
TWI622878B true TWI622878B (zh) 2018-05-01

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Family Applications (1)

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TW104140795A TWI622878B (zh) 2014-12-04 2015-12-04 用於在非統一記憶體架構中提供改進延遲的電腦程式、系統和方法（一）

Country Status (6)

Country Link
US (1) US9575881B2 (enExample)
EP (1) EP3227786A1 (enExample)
JP (1) JP6674460B2 (enExample)
CN (1) CN107003940B (enExample)
TW (1) TWI622878B (enExample)
WO (1) WO2016089631A1 (enExample)

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US9542333B2 (en) 2014-12-04 2017-01-10 Qualcomm Incorporated Systems and methods for providing improved latency in a non-uniform memory architecture
US10055158B2 (en) * 2016-09-22 2018-08-21 Qualcomm Incorporated Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems
US11461869B2 (en) * 2018-03-14 2022-10-04 Samsung Electronics Co., Ltd. Slab based memory management for machine learning training
US10776046B1 (en) * 2018-06-08 2020-09-15 Pure Storage, Inc. Optimized non-uniform memory access
US11734176B2 (en) * 2021-10-27 2023-08-22 Dell Products L.P. Sub-NUMA clustering fault resilient memory system

Citations (4)

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US5897664A (en) * 1996-07-01 1999-04-27 Sun Microsystems, Inc. Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of page copies
US20020065998A1 (en) * 2000-11-30 2002-05-30 International Business Machines Corporation NUMA system with redundant main memory architecture
US20090153897A1 (en) * 2007-12-18 2009-06-18 Blackmore Robert S Method, System and Program Product for Reserving a Global Address Space
US20100321397A1 (en) * 2009-06-23 2010-12-23 Boris Ginzburg Shared Virtual Memory Between A Host And Discrete Graphics Device In A Computing System

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US6049853A (en) 1997-08-29 2000-04-11 Sequent Computer Systems, Inc. Data replication across nodes of a multiprocessor computer system
US6167437A (en) 1997-09-02 2000-12-26 Silicon Graphics, Inc. Method, system, and computer program product for page replication in a non-uniform memory access system
WO1999012103A2 (en) 1997-09-05 1999-03-11 Sun Microsystems, Inc. Scalable shared memory multiprocessor system
US6871219B2 (en) 2001-03-07 2005-03-22 Sun Microsystems, Inc. Dynamic memory placement policies for NUMA architecture
US7765381B2 (en) 2003-04-04 2010-07-27 Oracle America, Inc. Multi-node system in which home memory subsystem stores global to local address translation information for replicating nodes
EP1611513B1 (en) 2003-04-04 2010-12-15 Oracle America, Inc. Multi-node system in which global address generated by processing subsystem includes global to local translation information
US8417913B2 (en) 2003-11-13 2013-04-09 International Business Machines Corporation Superpage coalescing which supports read/write access to a new virtual superpage mapping during copying of physical pages
JP4171749B2 (ja) * 2006-04-17 2008-10-29 Ｔｄｋ株式会社 メモリコントローラおよびフラッシュメモリシステム
US8392736B2 (en) 2009-07-31 2013-03-05 Hewlett-Packard Development Company, L.P. Managing memory power usage
US8719547B2 (en) * 2009-09-18 2014-05-06 Intel Corporation Providing hardware support for shared virtual memory between local and remote physical memory
EP2437161A1 (en) * 2010-10-01 2012-04-04 Intel Mobile Communications Technology Dresden GmbH Hardware accelerator module and method for setting up same
US8560757B2 (en) 2011-10-25 2013-10-15 Cavium, Inc. System and method to reduce memory access latencies using selective replication across multiple memory ports
TWI500292B (zh) * 2012-11-08 2015-09-11 Realtek Semiconductor Corp 具有節能功能的網路通訊裝置及方法
CN103257929B (zh) * 2013-04-18 2016-03-16 中国科学院计算技术研究所 一种虚拟机内存映射方法及系统
US9361233B2 (en) 2013-12-20 2016-06-07 Intel Corporation Method and apparatus for shared line unified cache
US9558041B2 (en) 2014-09-05 2017-01-31 Telefonaktiebolaget L M Ericsson (Publ) Transparent non-uniform memory access (NUMA) awareness
US9542333B2 (en) 2014-12-04 2017-01-10 Qualcomm Incorporated Systems and methods for providing improved latency in a non-uniform memory architecture

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US5897664A (en) * 1996-07-01 1999-04-27 Sun Microsystems, Inc. Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of page copies
US20020065998A1 (en) * 2000-11-30 2002-05-30 International Business Machines Corporation NUMA system with redundant main memory architecture
US20090153897A1 (en) * 2007-12-18 2009-06-18 Blackmore Robert S Method, System and Program Product for Reserving a Global Address Space
US20100321397A1 (en) * 2009-06-23 2010-12-23 Boris Ginzburg Shared Virtual Memory Between A Host And Discrete Graphics Device In A Computing System

Also Published As

Publication number Publication date
CN107003940B (zh) 2020-04-24
EP3227786A1 (en) 2017-10-11
TW201633143A (zh) 2016-09-16
US20160162399A1 (en) 2016-06-09
CN107003940A (zh) 2017-08-01
JP2018501559A (ja) 2018-01-18
WO2016089631A1 (en) 2016-06-09
US9575881B2 (en) 2017-02-21
JP6674460B2 (ja) 2020-04-01

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