TWI620330B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device includes a substrate, a first doped region, a second doped region, a gate, and a gate dielectric layer. The substrate has a first conductivity type. The first doped region is formed in the substrate and has a second conductivity type. The second doped region is formed in the substrate and has a second conductivity type. A gate is formed over the substrate and between the first and second doped regions. A gate dielectric layer is formed over the substrate and between the gate and the substrate. The gate dielectric layer has a first region and a second region. The thickness of the first region is different from the thickness of the second region.

Description

Semiconductor device and method of manufacturing same

This invention relates to a semiconductor device, and more particularly to a semiconductor device having a gate dielectric layer of a different thickness.

The semiconductor integrated circuit (IC) industry has experienced rapid growth in the past few decades. As the size of semiconductor devices continues to shrink in accordance with Moore's Law, the computing speed and process technology of the device are constantly changing. In promotion. In order to reduce the size of the device while saving process costs and providing optimum component performance, the semiconductor integrated circuit industry is constantly evolving in materials and process design.

Although the current semiconductor devices and their manufacturing methods are sufficient for their intended use, they have not been fully met in all respects, and thus the process technology of semiconductor integrated circuits still needs to be worked.

The invention provides a semiconductor device comprising a substrate, a first doped region, a second doped region, a gate and a gate dielectric layer. The substrate has a first conductivity type. The first doped region is formed in the substrate and has a second conductivity type. The second doped region is formed in the substrate and has a second conductivity type. A gate is formed over the substrate and between the first and second doped regions. A gate dielectric layer is formed over the substrate and between the gate and the substrate. Gate dielectric layer a first area and a second area. The thickness of the first region is different from the thickness of the second region.

The present invention further provides a method of fabricating a semiconductor device, comprising: providing a substrate having a first conductivity type; forming a first doped region in the substrate, wherein the first doped region has a second conductivity type Forming a second doped region in the substrate, wherein the second doped region has the second conductivity type; forming a gate on the substrate, wherein the gate is located in the first and second doping And forming a gate dielectric layer on the substrate, wherein the gate dielectric layer is between the gate and the substrate, and has a first region and a second region, the first The thickness of a region is different from the thickness of the second region.

100, 200‧‧‧ semiconductor devices

110, 210‧‧‧ substrate

121, 122, 240‧‧ ‧ well area

131, 132, 221, 222‧‧‧ doped areas

141, 231‧‧ ‧ gate

142, 232‧‧ ‧ gate dielectric layer

R ₁ ~R ₅ ‧‧‧Area

143, 233‧‧‧Insulated sidewall layer

CH‧‧‧ channel

241, 242‧‧‧Lightly doped bungee

Figure 1 is a schematic diagram of a possible semiconductor device of the present invention.

Figure 2 is another possible schematic diagram of the semiconductor device of the present invention.

3A to 3C are cross-sectional views showing respective stages of the semiconductor device 100 of the embodiment of the present invention in the method of manufacturing the same.

In order to make the objects, features and advantages of the present invention more comprehensible, the embodiments of the invention are described in detail below. The present specification provides various embodiments to illustrate the technical features of various embodiments of the present invention. The arrangement of the various elements in the embodiments is for illustrative purposes and is not intended to limit the invention. In addition, the overlapping portions of the drawings in the embodiments are for the purpose of simplifying the description, and do not mean the relationship between the different embodiments.

It must be understood that components that are specifically described or illustrated may be Various forms are known to the skilled person. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on another layer or substrate, or a layer on another layer or substrate, or between other layers or substrates. Other layers.

Figure 1 is a schematic view of a semiconductor device of the present invention. As shown, the semiconductor device 100 includes a substrate 110, doped regions 131, 132, a gate 141, and a gate dielectric layer 142. The substrate 110 can be a semiconductor substrate such as a germanium substrate. In addition, the semiconductor substrate may also be an elemental semiconductor, including germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide ), indium arsenide and/or indium antimonide; alloy semiconductors including bismuth alloy (SiGe), phosphorus arsenide alloy (GaAsP), arsenic aluminum indium alloy (AlInAs), arsenic aluminum gallium Alloy (AlGaAs), arsenic gallium alloy (GaInAs), indium gallium alloy (GaInP) and/or phosphorus indium gallium alloy (GaInAsP) or a combination of the above. Further, the substrate 110 may be a semiconductor on insulator. In an embodiment, the substrate 110 can be an undoped substrate. However, in other embodiments, the substrate 110 can also be a lightly doped substrate, such as a lightly doped P-type or N-type substrate. In this embodiment, the substrate 110 has a first conductivity type.

Doped regions 131 and 132 are formed in the substrate 110 and have a second conductivity type. In a possible embodiment, N-type doped regions 131 and 132 are formed by implanting N-type impurities. The N-type impurities include impurities such as phosphorus, arsenic, nitrogen, antimony, or a combination thereof. In another possible embodiment, P+ type doped regions 131 and 132 are formed by implanting P-type impurities. P-type impurities include impurities such as boron, gallium, aluminum, indium, or a combination thereof. In this embodiment, the second conductivity type is different from the first conductivity type. In a possible embodiment, the first conductivity type is a P type and the second conductivity type is an N type. In another possible embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

The gate 141 is formed over the substrate 110 and between the doping regions 131 and 132. In a possible embodiment, the gate 141, the doped regions 131 and 132 constitute a transistor. In this example, the gate 141 is electrically connected to a gate electrode; the doped region 131 is electrically connected to a drain electrode; and the doped region 132 is electrically connected to a source electrode. By controlling the voltage level of the gate electrode, the drain electrode and the source electrode, the crystal can be turned on or off. In this embodiment, the distance between the doping region 131 and the gate 141 is different from the distance between the doping region 132 and the gate 141, so the semiconductor device 100 is an asymmetric structure, such as a laterally diffused metal oxide. Semiconductor (Diterally Diffused Metal Oxide Semiconductor; LDMOS).

The gate dielectric layer 142 is formed over the substrate 110 and between the gate 141 and the substrate 110. In a possible embodiment, a dielectric material layer (to form a gate dielectric layer 142) and a conductive material layer (to form a gate 141) thereon are sequentially deposited on the substrate 110. on. Thereafter, the dielectric material layer and the conductive material layer are respectively patterned by a lithography and etching process to form the gate dielectric layer 142 and the gate 141.

The material of the dielectric material layer (ie, the material of the gate dielectric layer 142) may be tantalum oxide, tantalum nitride, hafnium oxynitride, high-k dielectric material, or any other suitable material. Dielectric material, or a combination of the above. The material of the high-k dielectric material may be a metal oxide, a metal nitride, a metal halide, a transition metal oxide, a transition metal nitride, a transition metal telluride, a metal oxynitride, Metal aluminate, zirconium silicate, zirconium aluminate. For example, the high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfO2, HfO3, HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO3 (BST ), Al 2 O 3 , SiO 2 , other high dielectric constant dielectric materials of other suitable materials, or combinations thereof. This dielectric material layer can be formed by the aforementioned chemical vapor deposition (CVD) or spin coating method.

The material of the conductive material layer (that is, the material of the gate electrode 141) may be amorphous germanium, a germanium germanium, one or more metals, a metal nitride, a conductive metal oxide, or a combination thereof. The above metals may include, but are not limited to, molybdenum, tungsten, titanium, tantalum, platinum or hafnium. The above metal nitrides may include, but are not limited to, molybdenum nitride, tungsten nitride, titanium nitride, and tantalum nitride. The above conductive metal oxide may include, but is not limited to, ruthenium oxide and indium tin oxide. The material of the conductive material layer can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method, for example, in an implementation. For example, an amorphous germanium conductive material layer or a polycrystalline germanium conductive material layer may be deposited by low pressure chemical vapor deposition (LPCVD) at a temperature between 525 and 650 ° C, and may have a thickness ranging from about 1000 Å to about 10000 Å.

As shown, the gate dielectric layer 142 has regions R1 and R2. The thickness of the region R1 is different from the thickness of the region R2. In the present embodiment, the thickness of the region R1 is smaller than the thickness of the region R2. When the voltage across the gate 141 and the doping region 132 reaches a critical value, a channel CH is formed under the region R1, thereby turning on the gate 141, A transistor formed by doping regions 131 and 132. Since the thickness of the region R1 is thin, the switching speed of the transistor from a conduction state to a non-conduction state or from a non-conduction state to a conduction state is faster. In addition, since the thickness of the region R2 is thick, it is possible to prevent leakage of the transistor when it is not in a conducting state.

In the embodiment, the semiconductor device 100 further includes an insulating sidewall layer 143. An insulating sidewall layer 143 is formed on sidewalls of the gate 141 and the gate dielectric layer 142. In some embodiments, an insulating layer having a thickness of about 200 to 2000 Å, such as yttrium oxide or tantalum nitride, may be deposited by LPCVD or PECVD at 350 to 850 ° C. Further, if a composite sidewall layer is formed, deposition may be performed. More than one layer of insulation. After deposition, SF6, CF4, CHF3, or C2F6 is used as an etching source, and anisotropic etching is performed by a reactive ion etching process to form insulating sidewalls on the sidewalls of the gate 141 and the gate dielectric layer 142. Layer 143.

In other embodiments, the semiconductor device 100 further includes a well region 121. The well region 121 is formed in the substrate 110 and has a second conductivity type. In a possible embodiment, the well region 121 can be formed by an ion implantation step. For example, when the second conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the well region 121 is to be formed to form the well region 121. However, when the second conductivity type is a P-type, boron ions or indium ions may be implanted in a region where the well region 121 is to be formed to form the well region 121. In the present embodiment, the doped region 131 is located in the well region 121. In a possible embodiment, the doping concentration of the doping region 131 is higher than the doping concentration of the well region 121. In addition, the doping region 131 and the gate dielectric layer 142 are spatially separated from each other.

In another embodiment, the semiconductor device 100 further includes a well region 122. The well region 122 is formed in the substrate 110 and has a first conductivity type. In a possible embodiment, the well region 122 can be formed by an ion implantation step. For example, When the first conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in the region where the well region 122 is to be formed to form the well region 122. However, when the first conductivity type is a P-type, boron ions or indium ions may be implanted in a region where the well region 122 is to be formed to form the well region 122. In a possible embodiment, the doping concentration of the well region 122 is higher than the doping concentration of the substrate 110. In the present embodiment, the doped region 132 is located in the well region 122. As shown, the gate dielectric layer 142 overlaps a portion of the well region 122.

Fig. 2 is another schematic view of the semiconductor device of the present invention. As shown, the semiconductor device 200 includes a substrate 210, doped regions 221, 222, a gate 231, and a gate dielectric layer 232. The substrate 210 has a first conductivity type. Since the manner in which the substrate 210 is formed is similar to the manner in which the substrate 110 in FIG. 1 is formed, it will not be described again.

The doping regions 221 and 222 have a second conductivity type and are formed in the substrate 210. Since the formation manner of the doping regions 221 and 222 is similar to that of the doping regions 131 and 132 of FIG. 1, it will not be described again. The gate 231 is disposed above the substrate 210 and between the doping regions 221 and 222. The gate dielectric layer 232 is disposed between the gate 231 and the substrate 210. Since the formation manner of the gate electrode 231 and the gate dielectric layer 232 is similar to that of the gate electrode 141 and the gate dielectric layer 142 of FIG. 1, it will not be described again.

In the present embodiment, the gate dielectric layer 232 has regions R3 R R5. The region R4 is located between the region R3 and the region R5. The thickness of the region R3 is the same as the thickness of the region R5, but is different from the thickness of the region R4. As shown, the thickness of the region R3 is greater than the thickness of the region R4.

In other embodiments, the semiconductor device 200 further includes a well region 240. The well region 240 is formed in the substrate 210 and has a first conductivity type. In a In a possible embodiment, the doping concentration of the well region 240 is lower than the doping concentration of the substrate 210. Since the formation of the well region 240 is the same as that of the well region 122 of FIG. 1, it will not be described again. In the present embodiment, doped regions 221 and 222 are located in well region 240.

In another possible embodiment, the semiconductor device 200 further includes Lightly Doped Drains (LDDs) 241 and 242. In the present embodiment, the lightly doped drains 241 and 242 have a second conductivity type. As shown, the lightly doped drain 241 directly contacts the doped region 221, and the lightly doped drain 242 directly contacts the doped region 222. Lightly doped gates 241 and 242 are used to avoid hot carrier effects.

In other embodiments, the semiconductor device 200 further includes an insulating sidewall layer 233. An insulating sidewall layer 233 is formed on the sidewalls of the gate 231 and the gate dielectric layer 232. Since the manner of forming the insulating sidewall layer 233 is the same as that of the insulating sidewall layer 143 of FIG. 1, it will not be described again. In the present embodiment, the insulating sidewall layer 233 overlaps the lightly doped gates 241 and 242.

3A to 3C are cross-sectional views showing respective stages of the semiconductor device 100 of the embodiment of the present invention in the method of manufacturing the same. Referring to Figure 3A, a substrate 110 is first provided. In a possible embodiment, the substrate 110 has a first conductivity type. Next, well regions 121 and 122 are formed in substrate 100. In a possible embodiment, the well region 121 has a second conductivity type and the well region 122 has a first conductivity type. The first conductivity type is different from the second conductivity type. In other embodiments, the doping concentration of the well region 122 is higher than the doping concentration of the substrate 110.

Referring to FIG. 3B, a gate dielectric layer 142 and a gate 141 are sequentially formed on the substrate 110. In an embodiment, a dielectric material layer (to form a gate dielectric layer 142) and a conductive material layer thereon are sequentially deposited in a blanket manner (for The gate electrode 141 is formed on the substrate 110, and the dielectric material layer and the conductive material layer are exposed through a lithography and etching process to form the doped regions 131 and 132. Thereafter, the dielectric material layer and the conductive material layer are respectively patterned by another lithography and etching process to form the gate dielectric layer 142 and the gate 141. In the present embodiment, the gate dielectric layer 142 can be divided into regions R1 and R2. The thickness of the region R1 is smaller than the thickness of the region R2.

Next, referring to FIG. 3C, an insulating sidewall layer 143 is formed on the sidewalls of the gate dielectric layer 142 and the gate 141. After insulating the sidewall layer 143, an ion implantation step is performed to form doped regions 131 and 132. Doped regions 131 and 132 are respectively disposed in the substrate 110 on both sides of the gate 141. In a possible embodiment, the doped region 131 is disposed in the well region 121 and has a second conductivity type, and the doped region 132 is disposed in the well region 122 and has a second conductivity type. As shown, the doped regions 132 are spatially separated from the gate dielectric layer 142. In a possible embodiment, the doping concentrations of the doping regions 131 and 132 are both higher than the doping concentration of the well region 121. In other embodiments, the gate 141, the doped regions 131 and 132 constitute a transistor.

Since the thickness of the region R1 is smaller than the thickness of the region R2, the switching time of the transistor can be shortened, such as switching from a conducting state to a non-conducting state, or switching from a non-conducting state to a conducting state. In addition, since the thickness of the region R2 is larger than the thickness of the region R1, it is possible to avoid leakage of the transistor when the transistor is not in a conducting state.

Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning In addition, unless explicitly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related technical field, and should not be interpreted as an ideal state or In the official voice.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. . For example, the system, apparatus or method of the embodiments of the present invention may be implemented in a physical embodiment of a combination of hardware, software or hardware and software. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (19)

A semiconductor device comprising: a substrate having a first conductivity type; a first doped region formed in the substrate and having a second conductivity type; and a second doped region formed on the substrate And having the second conductivity type; a gate formed on the substrate between the first and second doped regions; and a gate dielectric layer formed on the substrate And between the gate and the substrate, wherein the gate dielectric layer has a first region and a second region, the first region having a thickness different from the thickness of the second region, wherein the first doping The regions are spatially separated from the gate dielectric layer. The semiconductor device of claim 1, further comprising: a first well region formed in the substrate and having the first conductivity type, wherein the second doping region is located in the first well region in. The semiconductor device of claim 2, further comprising: a second well region formed in the substrate and having the second conductivity type, wherein the first doping region is located in the second well region Among them. The semiconductor device of claim 1, wherein the gate dielectric layer further has a third region having a thickness equal to a thickness of the first region. The semiconductor device of claim 4, wherein the second region is located between the first and third regions. The semiconductor device according to claim 5, further comprising: A well region is formed in the substrate and has the first conductivity type, wherein the first and second doping regions are located in the well region. The semiconductor device of claim 1, wherein the first doped region, the second doped region, and the gate form a transistor. The semiconductor device according to claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The semiconductor device according to claim 1, wherein the first conductivity type is an N type and the second conductivity type is a P type. A method of fabricating a semiconductor device, comprising: providing a substrate having a first conductivity type; forming a first doped region in the substrate, wherein the first doped region has a second conductivity type; forming a a second doped region in the substrate, wherein the second doped region has the second conductivity type; forming a gate on the substrate, wherein the gate is located in the first and second doped regions And forming a gate dielectric layer over the substrate, wherein the gate dielectric layer is between the gate and the substrate, and has a first region and a second region, the first region The thickness is different from the thickness of the second region. The method of manufacturing a semiconductor device according to claim 10, further comprising: forming a first well region in the substrate, wherein the first well region has the first conductivity type, the second doping region Located in the first well area. The method for manufacturing a semiconductor device according to claim 11 of the patent application, The method includes forming a second well region in the substrate, wherein the second well region has the second conductivity type, and the first doping region is located in the second well region. The method of fabricating a semiconductor device according to claim 12, wherein the first doped region and the gate dielectric layer are spatially separated from each other. The method of fabricating a semiconductor device according to claim 10, wherein the gate dielectric layer further has a third region having a thickness equal to a thickness of the first region. The method of fabricating a semiconductor device according to claim 14, wherein the second region is located between the first and third regions. The manufacturing method of the semiconductor device of claim 15, further comprising: forming a well region in the substrate, the well region having the first conductivity type, wherein the first and second doping regions are located In the well area. The method of fabricating a semiconductor device according to claim 10, wherein the first doped region, the second doped region, and the gate form a transistor. The method of manufacturing a semiconductor device according to claim 10, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The method of manufacturing a semiconductor device according to claim 10, wherein the first conductivity type is an N type and the second conductivity type is a P type.