TWI619282B - Memory device and operating method for resistive memory cell - Google Patents

Abstract

Memory device and method of operation of resistive memory cells. The memory device includes a resistive memory cell. The resistive memory cell includes a first electrode, a second electrode, and a memory film. The memory film is between the first electrode and the second electrode. The first electrode includes a bottom electrode portion and a wall electrode portion extending upward from the bottom electrode portion. The wall electrode portion is between the memory film and the bottom electrode portion. The width of the wall electrode portion and the memory film is smaller than the width of the bottom electrode portion.

Description

Memory device and method for operating resistive memory cells

The present invention relates to a memory cell and a method of operating the same, and more particularly to a resistive memory cell and method of operation thereof.

With the advancement of semiconductor technology, the shrinking capability of electronic components has been increasing, enabling electronic products to have more functions while maintaining a fixed size or even a smaller volume. As the processing volume of information becomes higher and higher, the demand for large-capacity and small-volume memory is also growing.

The current readable and writable memory system uses a transistor structure in conjunction with a memory unit for information storage, but this memory architecture has reached a bottleneck with the advancement of manufacturing technology. Therefore, advanced memory architectures have been proposed, such as phase change random access memory (PCRAM), magnetic random access memory (MRAM), and resistive random access memory. Resistive random access memory (RRAM). Among them, RRAM has the advantages of fast reading and writing speed, non-destructive reading, strong tolerance to extreme temperatures, and integration with existing CMOS (complementary metal oxide semiconductor) (CMOS) processes. It is considered to have the ability to replace all current storage. Emerging memories of media potential Recalling technology.

The present invention relates to a memory device and a method of operating a resistive memory cell. The resistive memory cell can have a large and stable switching window with good reliability.

In accordance with an embodiment of the present disclosure, a memory device is provided that includes a resistive memory cell. The resistive memory cell includes a first electrode, a second electrode, and a memory film. The memory film is between the first electrode and the second electrode. The first electrode includes a bottom electrode portion and a wall electrode portion extending upward from the bottom electrode portion. The wall electrode portion is between the memory film and the bottom electrode portion. The width of the wall electrode portion and the memory film is smaller than the width of the bottom electrode portion.

In accordance with another embodiment of the present disclosure, a memory device is provided that includes a resistive memory cell. The resistive memory cell includes a first electrode, a second electrode, and a memory film. The memory film is between the first electrode and the second electrode. The first electrode includes titanium nitride. The memory film includes titanium oxynitride. The second electrode includes titanium nitride.

According to still another embodiment of the present disclosure, a method of operating a resistive memory cell is provided, which includes the following steps. A writing step includes writing a resistive memory cell with a first width pulse or a first number of shots. After the writing step, it is verified whether the resistive memory cell reaches a predetermined resistance or current. If the resistive memory cell does not reach the predetermined resistance or current, verify whether the first width or the first number of times reaches the maximum width or the maximum number of times. If the first width or the first number does not reach the maximum width or the maximum number of times, the pulse wave of the second width or the second number of shots is written into the resistive memory cell. The second number is greater than the first number. The second width is greater than the first width.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

102, 102A, 102B‧‧‧ first electrode

104‧‧‧ memory film

106‧‧‧Material film

108‧‧‧second electrode

110‧‧‧ bottom electrode section

112‧‧‧ wall electrode section

128‧‧‧ bottom structure

130‧‧‧Semiconductor substrate

131‧‧‧Optoelectronics

132‧‧‧Source/Bungee

133‧‧‧ dielectric layer

134‧‧ ‧ gate structure

135‧‧‧gate dielectric layer

136‧‧‧ Conductive layer

137‧‧‧ gate electrode layer

138‧‧‧hard mask layer

140‧‧‧ openings

142‧‧‧ sacrificial layer

144‧‧‧ Conductive layer

270, 272, 274, 276, 278, 280, 282, 284, 286 ‧ ‧ steps

H1, H2‧‧‧ height

L1, L2‧‧‧ width

1 is a cross-sectional view of a resistive memory cell in accordance with an embodiment.

2A is a cross-sectional view of a resistive memory cell in accordance with an embodiment.

2B is a cross-sectional view of a resistive memory cell in accordance with an embodiment.

3 through 13 illustrate a method of fabricating a memory device in accordance with some embodiments.

Figure 14 is a graph showing the relationship between resistance and probability of a resistive memory cell in a set (SET) state and a reset (RESET) state, according to an embodiment.

Figure 15 is the relationship between the cycling count and the cell resistance of the resistive memory cell in the set state and the reset state.

Figure 16 shows the results of the operation of the resistive memory cell by the Enhanced Pulse Stylization (ISPP) method.

Figure 17 shows the write timing and resistance characteristics of the resistive memory cell in the reset state.

Figure 18 shows the write timing and resistance characteristics of the resistive memory cell in the set state.

Figure 19 illustrates a method of operating a resistive memory cell in accordance with an embodiment.

Fig. 20 shows the results of the operation of the resistive memory cells of the examples and the comparative examples.

The embodiment of the disclosure proposes a memory device and a method of operating a resistive memory cell. Resistive memory cells can have large and stable switching windows Good dependability.

It should be noted that the disclosure does not show all possible embodiments, and other embodiments not disclosed in the disclosure may also be applied. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting. In addition, the description in the embodiments, such as the detailed structure, the process steps, the material application, and the like, are for illustrative purposes only and are not intended to limit the scope of the disclosure. The details of the steps and the details of the embodiments may be varied and modified in accordance with the needs of the actual application process without departing from the spirit and scope of the disclosure.

According to an embodiment, the resistive memory cell includes a first electrode, a second electrode, and a memory film, wherein the memory film is between the first electrode and the second electrode. A material film can be between the memory film and the second electrode. In the embodiment, the material and structure design of the permeable memory cell can achieve excellent electrical properties.

1 is a cross-sectional view of a resistive memory cell in accordance with an embodiment. The resistive memory cell includes a first electrode 102, a memory film 104 on the first electrode 102, a material film 106 on the memory film 104, and a second electrode 108 on the material film 106.

In one embodiment, material film 106 comprises the composition of a memory material. In an embodiment, the composition of the memory material of the memory film 104 and the material film 106 includes materials having different resistances (high resistance state and low resistance state), wherein the resistance is permeable to the memory material provided to the memory film 104 and the material film 106. The pressure changes. The composition of the memory film 104 can be different from the material film 106. In one embodiment, for example, the resistive memory cell is a resistive random access memory (RRAM, ReRAM), wherein the first electrode 102 includes titanium nitride (TiN), and the memory film 104 includes titanium oxynitride (TiO _{x )} N _y ), the material film 106 comprises titanium oxide (TiO _x ), and the second electrode 108 comprises titanium nitride. The material is designed such that the resistive memory cell has a large switching window and has good reliability, such as memory function. Maintain at 250 ° C for more than 3 hours.

In another embodiment, the material film 106 comprises an electrode material. The material of the second electrode 108 may be different from the material film 106. In one embodiment, for example, the resistive memory cell is a resistive random access memory, wherein the first electrode 102 includes titanium nitride (TiN), and the memory film 104 includes titanium oxynitride (TiO _x N _y ). The film 106 comprises titanium (Ti) and the second electrode 108 comprises titanium nitride. The material is designed such that the resistive memory cell has a large switching window and is highly reliable, for example, the memory function is maintained at 250 ° C for more than 3 hours.

In some embodiments, the titanium oxide material film 106 may be a film caused by oxidation in an atmospheric environment after depositing the titanium material film 106. In some embodiments, the titanium material film 106 is subjected to an additional oxidation step to form a titanium oxide material film 106.

The material of the resistive memory cell of the present disclosure is not limited to the above-mentioned examples. In other embodiments, the electrode material of the first electrode 102, the second electrode 108 and the material film 106 may use other suitable conductive materials, such as metal or metal nitride, including a transition metal or a nitride thereof, such as tantalum (Ta), Tantalum nitride (TaN), hafnium (Hf), tantalum nitride (HfN), and the like. In various embodiments, the memory material of memory film 104 and material film 106 may use other suitable memory materials, such as metal oxides or metal oxynitrides for resistive memory materials. For example, the metal oxide comprises an oxide of a transition metal such as tantalum oxide (TaO x), hafnium oxide (HfO _x), and the like. For example, metal oxynitrides include transition metal-containing oxynitrides such as lanthanum oxynitride (TaO _x N _y ), bismuth oxynitride (HfO _x N _y ), and the like.

2A and 2B are cross-sectional views showing resistive memory cells according to other embodiments, and the differences from the resistive memory cells of Fig. 1 are explained below. The first electrode 102 includes a bottom electrode portion 110 and a wall electrode portion 112 that extends upward from the bottom electrode portion 110. The wall electrode portion 112 is between the memory film 104 and the bottom electrode portion 110. The width of the wall electrode portion 112 and the memory film 104 is smaller than the width of the bottom electrode portion 110 and may be smaller than the width of the material film 106 and the second electrode 108. The wall electrode portion 112 and the memory film 104 may have substantially the same width. The material film 106 and the second electrode 108 may have substantially the same width. In the embodiment, the height H1 of the memory film 104 is smaller than the height H2 of the first electrode 102. For example, 0 < H1/H2 < 0.1. The first electrode 102 and the memory film 104 may constitute an L shape. In an embodiment, the angle between the bottom electrode portion 110 and the wall electrode portion 112 of the L-shaped first electrode 102 may be between 135 degrees and 90 degrees.

3 through 13 illustrate a method of fabricating a memory device in accordance with some embodiments.

Referring to FIG. 3, a bottom structure 128 is provided as shown, including a transistor 131, a dielectric layer 133, and a conductive layer 136 formed on the semiconductor substrate 130. Semiconductor substrate 130 can include germanium or other suitable semiconductor material. The transistor 131 includes a source/drain 132 and a gate structure 134. Source/drain 132 may include doping A heavily doped region formed by the manner of the semiconductor substrate 130, such as an N+ doped region. The gate structure 134 can include a gate dielectric layer 135 and a gate electrode layer 137 on the gate dielectric layer 135. Gate dielectric layer 135 can include an oxide, such as hafnium oxide, or other suitable dielectric material. The gate electrode layer 137 may comprise polysilicon or other suitable electrically conductive material.

The conductive layer 136 that passes through the dielectric layer 133 can include a metal plug electrically connected to the source/drain 132. Dielectric layer 133 may comprise an oxide, a nitride, an oxynitride such as hafnium oxide, tantalum nitride, hafnium oxynitride, or other suitable dielectric material. Conductive layer 136 can comprise a metal, such as tungsten, or other suitable electrically conductive material. In one embodiment, the bottom structure 128 shown in FIG. 3 may be a structure that is planarized by chemical mechanical polishing.

Referring to FIG. 4, a hard mask layer 138 is formed on the bottom structure 128. In one embodiment, the hard mask layer 138 comprises tantalum nitride (SiN). In other embodiments, the hard mask layer 138 can use other suitable materials. In one embodiment, for example, the hard mask layer 138 may have a thickness of 1000 Å to 2000 Å, such as 1500 Å.

Referring to FIG. 5A, the hard mask layer 138 is patterned to form the opening 140. The angle of the opening 140 is not limited to the angle of 90 degrees as shown in Fig. 5A. In other embodiments, the opening 140 may have an angle greater than 90 degrees, as shown in FIG. 5B.

Referring to FIG. 6, the first electrode 102A is formed on the upper surface of the hard mask layer 138, the sidewall of the hard mask layer 138 exposed to the opening 140, and the upper surfaces of the dielectric layer 133 and the conductive layer 136. In one embodiment, for example, the first electrode 102A may have a thickness of 50 Å to 200 Å, such as 100 Å.

Referring to FIG. 7, the first electrode 102A is patterned to leave The stepped first electrode 102B covers the conductive layer 136 and a portion of the hard mask layer 138 and the dielectric layer 133 adjacent to the conductive layer 136. Through the patterning step, a portion of the dielectric layer 133 and the hard mask layer 138 adjacent to the dielectric layer 133 are also exposed.

Referring to FIG. 8, a sacrificial layer 142 is formed on the hard mask layer 138, the first electrode 102B, and the opening 140. In one embodiment, the sacrificial layer 142 can include an oxide such as tetraethoxydecane (TEOS) formed by deposition. In other embodiments, the sacrificial layer 142 can use other suitable materials.

Referring to FIG. 9, the sacrificial layer 142 and the upper portion of the first electrode 102B are removed, leaving the sacrificial layer 142 in the opening 140 and the first electrode 102 having an L shape. In one embodiment, this removal step can be performed using a chemical mechanical polishing method that can be designed to stop on the hard mask layer 138.

Referring to FIG. 10, the exposed upper portion of the first electrode 102 is oxidized to form the oxide memory film 104. The height of the memory film 104 (H1, 2A, 2B) can be controlled by an oxidation process. The oxidation method includes a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method. In one embodiment, for example, the first electrode 102 includes titanium nitride (TiN), and the memory film 104 includes titanium oxynitride (TiO _x N _y ) formed through the oxidation step.

Referring to FIG. 11, a material film 106 is formed on the memory film 104, the sacrificial layer 142, and the hard mask layer 138. In one embodiment, the thickness of the material film 106 can range from 5 Å to 50 Å, such as 10 Å. The second electrode 108 is formed on the material film 106. In one embodiment, the second electrode 108 may have a thickness of 50 Å to 500 Å, such as 400 Å.

Referring to FIG. 12A, the sacrificial layer 142, the hard mask layer 138, The material film 106 and the second electrode 108 perform a patterning step.

Referring to FIGS. 12A and 12B , the first electrode 102 of the resistive memory cell is electrically connected to the source/drain 132 of the transistor 131 via the conductive layer 136 , for example, electrically connected to the drain. In one embodiment, for example, the patterned material film 106 and the second electrode 108 have a width of 5000 Å. In the embodiment, the width L1 of the wall electrode portion 112 of the first electrode 102 is smaller than the width L2 of the conductive layer 136. For example, 0 < L1/L2 < 0.5. In one embodiment, for example, the width L1 of the wall electrode portion 112 is 10 Å to 200 Å, for example, 100 Å. The width L2 of the conductive layer 136 is 1000 Å to 5000 Å, for example, 3,000 Å.

Referring to FIG. 13, a conductive layer 144 is formed on the conductive layer 136 and the second electrode 108. Conductive layer 144 can include a metal (eg, M1) line.

Figure 14 is a diagram showing the relationship between the resistance and the probability of the set state and the reset state of the memory device (resistive memory cell) according to an embodiment, wherein the resistive memory cell is shown. It has a large switching window, that is, the resistance difference is large, so the state of setting or reset can be easily distinguished.

In the present disclosure, the inventors have found that a resistive memory cell (not limited to the resistive memory cell structure described in the present disclosure) has a problem that the resistance switching window is unstable after the cycling operation (as shown in FIG. 15). This will result in switching failure and reduced reliability. In addition, it is difficult to monitor the failed unit during operation of the memory unit. The problem of failure cannot be solved by the incremental step pulse programming (ISPP) method (as shown in Figure 16). The inventors utilized the found write timing and resistance characteristics (such as the reset feature of Figure 17). Or the setting characteristics of Fig. 18) The development of a new memory device operation method can be used to monitor the deterioration of the resistive memory cell after the cycle operation.

The following describes a method of operating a memory device according to an embodiment, which can be used, for example, to monitor degradation or health of a resistive memory cell. The method of operation includes an algorithm with a degradation detection design that improves the reliability of the resistive memory cell.

FIG. 19 illustrates an operation method of a resistive memory cell in a memory cell array according to an embodiment. Beginning at step 270. In step 272, the condition for writing the resistive memory cell is loaded.

In step 274, a setting step is performed, including setting a write pulse width or a shot count of the resistive memory cell. In one embodiment, the pulse is first set to a first width or the first number of shots. For example, N shots indicate that there are N write pulses.

In step 276, a writing step is performed, including writing a resistive memory cell with a (first) width pulse or a (first) number of shots set in step 274. In an embodiment, no verification steps are performed during the execution of the write step 276. For example, no verification steps are performed between multiple shots.

After the writing step 276, step 278 is performed to perform the verifying step, including verifying whether the written resistive memory cell reaches a predetermined resistance or current. If the resistive memory cell does not reach the predetermined resistance or current, then proceed to step 280 to verify if the (first) width or (first) number of times has reached the maximum width or maximum number of times. If it is verified in step 280 that the maximum width or maximum number of times has not been reached, then proceed to step 282: Increasing the width or number of shots of the write pulse, that is, increasing the write pulse from the first width to the second width, or increasing the number of shots from the first number to the second number. Then, the setting step 274 is performed with the (second) width or (second) number obtained after the increase, and the flow as shown in Fig. 19 is executed. In one embodiment, the degradation of the resistive memory cell can be detected by using steps 280 and 282 in the virtual frame.

In step 278, if it is verified that the resistive memory cell has reached a predetermined resistance or current, then proceed to end step 284. Further, if it is verified in step 280 that the maximum width or maximum number of times has been reached, then proceeding to step 286, the flag write fails and proceeds to end step 284.

Fig. 20 shows the results of the operation of the resistive memory cells of the embodiment (indicated by the solid line) and the comparative example (indicated by the broken line). The method of operation of an embodiment includes monitoring steps 280, 282 as shown in FIG. The operational steps of the comparative example omit steps 280, 282. It can be seen from Fig. 20 that the method of operation of the embodiment enables the resistive memory cell to maintain a stable resistance switching window after the cyclic operation.

The resistive memory cell according to the embodiment has a large switching window and is excellent in reliability. Furthermore, the method of operation according to the embodiment enables the resistive memory cell to have a stable switching window.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (5)

A memory device comprising: a resistive memory cell comprising a first electrode, a second electrode and a memory film, wherein the memory film is between the first electrode and the second electrode; and a conductive layer, wherein The first electrode includes a bottom electrode portion and a wall electrode portion extending upward from the bottom electrode portion, the wall electrode portion being between the memory film and the bottom electrode portion. The width of the wall electrode portion and the memory film is smaller than the width of the bottom electrode portion, and the width L1 of the wall electrode portion is smaller than the width L2 of the conductive layer, wherein the memory film has a height H1, and the first electrode has a height H2, 0 < H1/H2 < 0.1. The memory device of claim 1, wherein 0 < L1/L2 < 0.5. The memory device of claim 1, wherein the wall electrode portion has the same width as the memory film. The memory device of claim 1, wherein the bottom electrode portion and the wall electrode portion have an angle of between 135 degrees and 90 degrees. The memory device of claim 1, wherein the first electrode has an L shape.