TWI618191B - Semiconductor devices, through-substrate via structures and methods for forming the same - Google Patents

Abstract

The semiconductor device includes a via structure through the substrate, a first metal layer and electronic components on the via structure through the substrate, and a second metal layer and another electronic component under the via structure of the substrate. The via structure penetrating through the substrate includes a through hole extending from the first surface of the semiconductor substrate to the opposite second surface, and an acute angle is sandwiched between the sidewall of the through hole and the second surface on the side of the semiconductor substrate, and the via structure of the through substrate A conductive layer filled in the through hole and a semiconductor layer disposed between the conductive layer and the semiconductor substrate are also included.

Description

Semiconductor device, via structure through substrate, and method of forming same

The present invention relates to a semiconductor device, and more particularly to a via structure that penetrates a substrate in a semiconductor device and a method of forming the same.

In the traditional two-dimensional (2D) process technology, the metal wires must be elongated on the plane, and the two devices can be connected through many different structural layers, resulting in signal attenuation and cost increase. Therefore, in order to break through this bottleneck, a semiconductor three-dimensional (3D) integrated circuit (IC) technology has been developed, in which a through-substrate via (TSV) is one of the core technologies, and a long-distance metal. The wires are vertically turned on by the TSV technology to change the signal transmission mode from horizontal to vertical, which can increase the stack density, reduce the size, reduce the power consumption, and improve the signal transmission speed, thereby increasing the performance of the product. widely.

Although the through-substrate via structures and their formation methods are sufficient for their intended use, they have not been fully met in all respects. Therefore, there is still a need for a through-hole via technology. .

The present disclosure provides an embodiment of a via structure through the substrate and The formation method is such that through the through hole having a taper angle, the generation of internal pores of the material filled in the through hole is reduced. In addition, by the arrangement of the semiconductor layer located in the through hole and between the conductive layer and the semiconductor substrate, the planarization process of the bottom surface of the semiconductor substrate is overcome (also referred to as back grind (BG)). Because the material difference between the inside and the outside of the hole is too large, it is easy to cause the conductive layer in the through hole to protrude outside the semiconductor substrate due to the uneven distribution of stress and the difference in etching selectivity to the polishing liquid, resulting in flatness of the semiconductor substrate. There is still a problem of unevenness on the surface after the chemical process.

According to some embodiments, a via structure is provided through the substrate. The through-substrate via structure includes a through hole extending from the first surface of the semiconductor substrate to the opposite second surface, and an acute angle is sandwiched between the sidewall of the through hole and the second surface on the side of the semiconductor substrate. The through-substrate via structure further includes a conductive layer filled in the through hole, and a semiconductor layer disposed in the through hole and interposed between the conductive layer and the semiconductor substrate.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a through hole extending from a first surface of the semiconductor substrate to an opposite second surface, and an acute angle is sandwiched between the sidewall of the through hole and the second surface on the side of the semiconductor substrate. The semiconductor device further includes a conductive layer filled in the through hole. The semiconductor device further includes a semiconductor layer disposed in the through hole and interposed between the conductive layer and the semiconductor substrate. Further, the semiconductor device includes a first metal layer adjacent to the first surface and electrically connected to the electronic component, and the second metal layer, adjacent to the second surface, and electrically connected to the other electronic component.

According to some embodiments, a method of forming a via structure through a substrate is provided. The method of forming the via structure through the substrate is included in the semiconductor A hole is formed in the substrate, a semiconductor layer is formed on the sidewall and the bottom surface of the hole, and a conductive layer is formed on the semiconductor layer and the semiconductor substrate, wherein the conductive layer fills the hole. The method for forming the via structure of the through substrate further comprises: performing a first planarization process on a top surface of the semiconductor substrate, removing a conductive layer other than the hole, and performing a second planarization process on the bottom surface of the semiconductor substrate to remove a portion of the semiconductor The substrate is such that the surface of the semiconductor substrate is coplanar with the semiconductor layer on the bottom surface of the hole, wherein the sidewall of the hole and the surface of the semiconductor substrate have an acute angle on the side of the semiconductor substrate.

100‧‧‧through via structure

101‧‧‧Semiconductor substrate

101a‧‧‧ first surface

101b‧‧‧ second surface

101B‧‧‧ bottom

101F‧‧‧ top surface

102‧‧‧ hole

102B‧‧‧Bottom of the hole

102S‧‧‧ sidewall of the hole

102’‧‧‧through holes

103‧‧‧Semiconductor layer

105‧‧‧Barrier layer

107‧‧‧ Conductive layer

110‧‧‧First metal layer

115, 125‧‧‧ electronic components

120‧‧‧Second metal layer

200‧‧‧Semiconductor device

Θ‧‧‧ acute angle

We can better understand the point of view of the disclosure by the following detailed description in conjunction with the accompanying drawings. It is worth noting that some features may not be drawn to scale according to industry standard practice. In fact, the dimensions of different features may be increased or decreased for clarity of discussion.

1-8 are cross-sectional schematic views showing different stages of formation of a via structure through a substrate in accordance with some embodiments of the present disclosure; and FIG. 9 is a cross-sectional view showing the formation of a semiconductor device in accordance with some embodiments of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing the various components of the semiconductor device provided. Specific examples of the components and their configurations are described below to simplify the description of the present disclosure. Of course, these are merely examples and are not intended to limit the disclosure. For example, reference to a first element formed above a second element in the description may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements. Make Embodiments in which they are not in direct contact. Furthermore, the disclosure may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of clarity and clarity, and is not intended to represent the relationship of the various embodiments and/

Some variations of the embodiments are described below. In the various figures and illustrated embodiments, like reference numerals are used to design It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

The present disclosure provides an embodiment of a via structure that forms a through substrate. 1-8 are cross-sectional schematic views showing different stages of forming a via structure 100 through the substrate shown in FIG. 8 in accordance with some embodiments of the present disclosure.

According to some embodiments, as shown in FIG. 1, a hole 102 is formed in the semiconductor substrate 101. The semiconductor substrate 101 may be made of germanium or other semiconductor material, or the semiconductor substrate 101 may comprise other elemental semiconductor materials such as germanium (Ge). In some embodiments, the semiconductor substrate 101 is made of a compound semiconductor such as tantalum carbide, gallium nitride, gallium arsenide, indium arsenide or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor such as germanium, tantalum carbide, gallium arsenide or indium gallium phosphide. In some embodiments, the semiconductor substrate 101 comprises a silicon-on-insulator (SOI) substrate. In some embodiments, the semiconductor substrate 101 comprises an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer overlying the bulk semiconductor. In some embodiments, the semiconductor substrate 101 can be a lightly doped P-type or N-type substrate.

Following the foregoing, as shown in FIG. 1, the holes 102 can be formed by a suitable process such as a lithography and etching process. It should be noted that the hole 102 is from the top surface 101F of the semiconductor substrate 101 toward the bottom surface of the semiconductor substrate 101. 101B extends but does not extend to the bottom surface 101B. Further, the side wall 102S of the hole 102 and the bottom surface 102B of the hole 102 have an acute angle θ with an extended dotted line on the side of the semiconductor substrate 101. In other words, the hole 102 has a tapered cross section from the top surface 101F toward the bottom surface 102B. In some embodiments, the acute angle θ is in the range of angles below about 88 degrees and above about 60 degrees, and the aspect ratio of the holes 102 is about 20 or more.

According to some embodiments, as shown in FIG. 2, a semiconductor layer 103 is formed on the sidewall 102S and the bottom surface 102B of the hole 102, and on the top surface 101F of the semiconductor substrate 101. In some embodiments, the material of the semiconductor layer 103 may be polycrystalline germanium or germanium oxide, by a chemical vapor deposition (CVD) process, a flowable chemical vapor deposition (FCVD) process, an atomic layer. Atomic layer deposition (ALD) process, low-pressure chemical vapor deposition (LPCVD) process, plasma enhanced chemical vapor deposition (PECVD) process, other suitable processes or The combination of the foregoing is formed.

In some embodiments, as shown in FIG. 2, a portion of the semiconductor layer 103 on the bottom surface 102B of the hole 102 has a thickness t ₁ , and a portion of the semiconductor layer 103 on the sidewall 102S of the hole 102 has a thickness t ₂ , wherein the thickness T _{1 is} greater than the thickness t ₂ , which further ensures that in the subsequent second planarization process (also referred to as the bottom polishing process, as shown in FIG. 8 ), the portion of the semiconductor layer 103 on the bottom surface 102B of the hole 102 can be prevented. The conductive layer 107 in the hole protrudes, thereby preventing the protruding conductive layer 107 from being scratched.

According to some embodiments, as shown in FIG. 3, on a semiconductor substrate The top surface 101F of 101 performs a planarization process to remove the semiconductor layer 103 outside the hole 102 and expose the top surface 101F of the semiconductor substrate 101. The planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, an etching process, other suitable processes, or a combination of the foregoing. In some embodiments, this step may be omitted. After the filling of the holes 102 is completed, a planarization process is performed to remove all materials outside the holes 102 until the top surface 101F of the semiconductor substrate 101 is exposed.

Following the foregoing, as shown in FIG. 4, a barrier layer 105 is formed in the hole 102 and on the top surface 101F of the semiconductor substrate 101, and the barrier layer 105 is formed on the semiconductor layer 103, and a part of the barrier layer 105 is formed. Formed on the bottom surface of the hole 102. The formation of the barrier layer 105 serves to stably bond the subsequently formed conductive layer 107 (as shown in FIG. 5). In some embodiments, the material of the barrier layer 105 may be titanium or titanium nitride by a chemical vapor deposition (CVD) process, a flow chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, and a low voltage. A chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, other suitable processes, or a combination of the foregoing.

According to some embodiments, as shown in FIG. 5, a conductive layer 107 is formed in the hole 102 and on the top surface 101F of the semiconductor substrate 101, and the conductive layer 107 is formed on the semiconductor layer 103 and the barrier layer 105. In some embodiments, the conductive layer 107 comprises a metal or other suitable conductive material, such as: tungsten, copper, nickel, aluminum, WSix, polysilicon, or a combination thereof, and the conductive layer 107 is processed by a chemical vapor deposition (CVD) process. Flow chemical vapor deposition (FCVD) process, atomic layer deposition (ALD) process, low pressure chemical vapor deposition (LPCVD) process, plasma enhanced chemical vapor deposition (PECVD) process, other suitable processes, or groups of the foregoing Formed together.

Following the foregoing, as shown in FIG. 6, a first planarization process is performed on the top surface 101F of the semiconductor substrate 101 to remove the barrier layer 105 and the conductive layer 107 outside the hole 102, and expose the top surface 101F of the semiconductor substrate 101. . In some embodiments, the first planarization process comprises a chemical mechanical polishing (CMP) process, a polishing process, an etching process, other suitable processes, or a combination of the foregoing.

According to some embodiments, as shown in FIG. 7, a first metal layer 110 is formed on the top surface 101F of the semiconductor substrate 101, and an electronic component 115 is formed on the first metal layer 110. In some embodiments, electronic component 115 can include one or more layers of conductive or dielectric layers. After the first metal layer 110 and the electronic component 115 are formed, a carrier tape may be formed on the electronic component 115 to facilitate subsequent planarization processing for the bottom surface 101B of the semiconductor substrate 101.

Next, as shown in FIG. 8, a second planarization process is performed on the bottom surface 101B of the semiconductor substrate 101 to remove a portion of the semiconductor substrate 101 under the hole 102 such that the surface of the semiconductor substrate 101 and the bottom surface of the hole 102 are on the bottom surface of the hole 102. The semiconductor layers 103 are coplanar. In some embodiments, the second planarization process further removes a portion of the semiconductor layer 103 on the bottom surface of the hole 102, but does not expose the barrier layer 105 and the conductive layer 107 on the semiconductor layer 103 and within the hole 102.

It is to be noted that the thickness of the semiconductor layer 103 on the bottom surface of the hole 102 is greater than the thickness of the remaining portion of the semiconductor layer 103 before the second planarization process is performed. In some embodiments, the thickness of the semiconductor layer 103 on the bottom surface of the hole 102 may be greater than, equal to, or less than the thickness of the remaining portion of the semiconductor layer 103 after the second planarization process is performed. In addition, the second flattening system The process includes a chemical mechanical polishing (CMP) process, a polishing process, an etching process, other suitable processes, or a combination of the foregoing.

According to some embodiments, as shown in FIG. 8, after the second planarization process is performed, a via structure 100 is formed through the substrate. The via structure 100 through the substrate has a through hole 102' extending from the first surface 101a of the semiconductor substrate 101 to the opposite second surface 101b of the semiconductor substrate 101. It is to be noted that an acute angle θ is sandwiched between the side wall of the through hole 102' and the second surface 101b of the semiconductor substrate 101 on the side of the semiconductor substrate 101, and the acute angle θ is in an angular range of about 88 degrees or less and about 60 degrees or more. Further, the semiconductor layer 103 is located in the through hole 102' and interposed between the conductive layer 107 filled in the through hole 102' and the semiconductor substrate 101, and a part of the semiconductor layer 103 is located under the conductive layer 107. In other words, the semiconductor layer 103 on the bottom surface of the through hole 102' is located under the conductive layer 107. In some embodiments, a barrier layer 105 is disposed between the semiconductor layer 103 and the conductive layer 107 to facilitate bonding.

In some embodiments, the semiconductor layer 103 may be made of polycrystalline germanium. Since the material of the semiconductor layer 103 is the same or similar to the material of the semiconductor substrate 101, the semiconductor layer 103 and the semiconductor substrate 101 are etched for the polishing liquid during the second planarization process. The selection selectivity is substantially the same, and it is less likely to cause uneven stress distribution. Therefore, after the second planarization process is performed, the conductive layer 107 filled in the through hole 102' is not exposed, and the semiconductor layer 103 on the bottom surface of the through hole 102' is coplanar with the semiconductor substrate 101. In other words, the first surface 101a of the semiconductor substrate 101 is coplanar and flat with the top surface of the via structure 100 penetrating the substrate, and the second surface 101b of the semiconductor substrate 101 is coplanar and flat with the bottom surface of the via structure 100 penetrating the substrate. The conductive layer 107 does not protrude from the second surface 101b of the semiconductor substrate 101, thereby reducing the probability that the conductive layer 107 will be scratched during subsequent processing or transportation.

FIG. 9 is a cross-sectional view showing the formation of a semiconductor device 200 in accordance with some embodiments of the present disclosure.

According to some embodiments, as shown in FIG. 9, after the second planarization process is performed, the second metal layer 120 is formed on the via structure 100 penetrating the substrate, and another electronic component is formed under the second metal layer 120. 125. In some embodiments, electronic component 125 can include one or more layers of conductive or dielectric layers. In some embodiments, the via structure 100 through the substrate is electrically connected to the electronic component 115 located above the via structure 100 of the substrate through the first metal layer 110, and electrically connected to the via structure of the through substrate through the second metal layer 120. Another electronic component 125 below 100 is formed to form semiconductor device 200.

In some embodiments, the materials of the first metal layer 110 and the second metal layer 120 are CrAu, TiAu, TiNiAu, TiNiAg or a combination thereof, and may be by plating, chemical vapor deposition (CVD), physical vapor phase. Formed by physical vapor deposition (PVD) or a combination of the foregoing. In some embodiments, electronic components 115 and 125 can be part of two different wafers. In some other embodiments, the electronic component 115 can be electrically connected to a portion of the integrated circuit, and the electronic component 125 can be electrically coupled to a portion of another integrated circuit.

The present disclosure provides an embodiment of a via structure through a substrate and a method of forming the same, and a semiconductor device including the via structure through the substrate, through a through hole having a taper angle, reducing internal pores of the conductive layer filled in the through hole And the generation of internal pores of the semiconductor layer surrounding the conductive layer. In addition, by a semi-conductor located in the through hole and between the conductive layer and the semiconductor substrate The body layer is disposed in the same or similar relationship with the material inside and outside the hole. When the second planarization process is performed, the etching selectivity of the semiconductor layer and the semiconductor substrate to the polishing liquid is substantially the same, and the stress distribution is not easily generated. In the event that, after the second planarization process is performed, a flat surface of the semiconductor substrate can be produced.

The above summary of the several embodiments is characterized in that the subject matter of the present disclosure can be more fully understood by those of ordinary skill in the art. Those having ordinary skill in the art should understand that they can design or modify other processes and structures based on the present disclosure to achieve the same objects and/or advantages as the embodiments described herein. It is also to be understood by those of ordinary skill in the art that the present invention is not limited to the spirit and scope of the disclosure, and that they can be practiced without departing from the spirit and scope of the disclosure. Various changes, substitutions and substitutions.

Claims (15)

A via structure extending through a substrate, comprising: a uniform via hole extending from a first surface of a semiconductor substrate to an opposite second surface, and a sidewall of one of the through holes and the second surface being between the semiconductor substrate The side clip has an acute angle; a conductive layer is filled in the through hole; and a semiconductor layer is disposed in the through hole and between the conductive layer and the semiconductor substrate, wherein a portion of the semiconductor layer is electrically conductive Below the layer and coplanar with the second surface. The through-substrate via structure of claim 1, wherein the semiconductor layer surrounds the conductive layer. The through-substrate via structure according to claim 1, wherein the semiconductor layer is polycrystalline germanium. The through-substrate via structure according to claim 1, wherein the acute angle is within an angle range of 88 degrees or less and 60 degrees or more. The through-substrate via structure according to claim 1, further comprising: a barrier layer disposed between the conductive layer and the semiconductor layer, and a portion of the barrier layer is located at the bottom of the through hole . A semiconductor device comprising: a permanent via hole extending from a first surface of a semiconductor substrate to an opposite second surface, and an acute angle between the sidewall of one of the through holes and the second surface on the side of the semiconductor substrate a conductive layer filled in the through hole; a semiconductor layer disposed in the through hole and interposed between the conductive layer and the semiconductor substrate, a portion of the semiconductor layer being under the conductive layer and coplanar with the second surface; a first metal layer Adjacent to the first surface and electrically connected to an electronic component; and a second metal layer adjacent to the second surface and electrically connected to the other electronic component. The semiconductor device of claim 6, wherein the semiconductor layer surrounds the conductive layer. The semiconductor device of claim 6, wherein the semiconductor layer is polycrystalline germanium. The semiconductor device according to claim 6, wherein the acute angle is within an angular range of 88 degrees or less and 60 degrees or more. The semiconductor device of claim 6, further comprising: a barrier layer disposed between the conductive layer and the semiconductor layer, and a portion of the barrier layer is located at a bottom of the through hole. A method for forming a via structure through a substrate, comprising: forming a hole in a semiconductor substrate; forming a semiconductor layer on a sidewall and a bottom surface of the hole; forming a conductive layer on the semiconductor layer and the semiconductor substrate a layer, wherein the conductive layer fills the hole; a first planarization process is performed on a top surface of the semiconductor substrate to remove the conductive layer except the hole; and a second planarization process is performed on a bottom surface of the semiconductor substrate , remove one Dividing the semiconductor substrate such that a surface of the semiconductor substrate is coplanar with the semiconductor layer on the bottom surface of the hole; wherein the sidewall of the hole and the surface of the semiconductor substrate have an acute angle on the side of the semiconductor substrate . The method for forming a through-substrate via structure according to claim 11, wherein the thickness of the semiconductor layer on the bottom surface of the hole is greater than the rest of the semiconductor layer before the second planarization process is performed. The thickness of the part. The method of forming a via structure through the substrate as described in claim 11, wherein the second planarization process thins the thickness of the semiconductor layer on the bottom surface of the hole. The method for forming a via structure through the substrate as described in claim 11, wherein the conductive layer is not exposed after the second planarization process is performed. The method for forming a through-substrate via structure according to claim 11, further comprising: forming a barrier on the semiconductor layer and the semiconductor substrate after forming the semiconductor layer and before forming the conductive layer a layer, a portion of the barrier layer is formed on the bottom surface of the hole.