TWI613500B - Pixel structure - Google Patents

Abstract

A pixel structure includes a substrate, a gate, a capacitor electrode, a first insulating layer, an active layer, a drain and a source, and an extension electrode. The gate is placed on the substrate. The capacitor electrode is disposed on the substrate and separated from the gate. The first insulating layer covers the gate and the capacitor electrode, wherein the first insulating layer has a recess, and the recess is located directly above the capacitor electrode. The active layer is disposed on the first insulating layer. The drain and the source are disposed on the active layer and are separated from each other. The extension electrode extends from the drain or source into the recess.

Description

Pixel structure

The present disclosure relates to a display device, and in particular to a pixel structure of a display device.

When a high voltage is to be used to drive a display panel, the display panel often requires a large component size (eg, larger gate, drain, and/or source size) to withstand high voltages, but large size components will cause parasitic Capacitance (such as the capacitance generated by the gate and the drain) rises sharply, which in turn increases the feed through voltage. However, excessive feedthrough voltage may adversely affect the display panel.

Embodiments of the present invention can reduce the feedthrough voltage of a display device.

According to an embodiment of the invention, a pixel structure includes a substrate, a gate, a capacitor electrode, a first insulating layer, an active layer, a drain and a source, and an extension electrode. The gate is disposed on the substrate. The capacitor electrode is disposed on the substrate and separated from the gate. The first insulating layer covers the gate and the capacitor electrode, wherein the first insulating layer has a recess, and the recess is located in the capacitor Extremely above. The active layer is disposed on the first insulating layer. The drain and the source are disposed on the active layer and are separated from each other. The extension electrode extends from the drain or source into the recess.

In some embodiments, the first insulating layer includes a gate insulating portion. The gate insulation is located directly above the gate. A thickness of the gate insulating portion is greater than a distance between a bottom surface of the recess and the capacitor electrode.

In some embodiments, one of the sidewalls of the recess is located directly above the capacitor electrode.

In some embodiments, the recess has a depth, and a top edge of the recess is spaced apart from the capacitor electrode by a ratio of depth to distance between 1/9 and 7/9.

In some embodiments, one of the bottom surfaces of the recess is separated from the capacitor electrode by a distance between 1000 Å and 4000 Å.

In some embodiments, the pixel structure further includes at least one insulating protrusion protruding from a bottom surface of the recess.

In some embodiments, the insulating protrusion is integrally formed with the first insulating layer.

In some embodiments, the number of at least one insulating protrusion is plural, and the insulating protrusions are spaced apart from each other on the bottom surface of the recess.

In some embodiments, the insulating protrusions have the same thickness.

In some embodiments, the recess has a depth, and a top surface of the insulating protrusion is spaced apart from the capacitor electrode by a distance between 1/9 and 7/9.

In some embodiments, the extension electrode extends further onto the insulating protrusion.

In some embodiments, the extension electrodes are undulating and have a plurality of alternating peaks and troughs.

In some embodiments, the pixel structure further includes a second insulating layer, the second insulating layer has a first portion and a second portion connected, the first portion covers the active layer, the source and the drain, and the second portion covers The electrodes are extended, and the second portion is undulating and has a plurality of alternating peaks and troughs.

In some embodiments, the pixel structure further includes a third insulating layer, and the third insulating layer covers the second insulating layer, wherein the third insulating layer has a capacitor covering portion, the capacitor covering portion is directly above the capacitor electrode, and the capacitor The cover portion has a top surface and a bottom surface, and the top surface and the bottom surface have different shapes.

In some embodiments, the bottom surface of the capacitor cover is conformal to the second portion of the second insulating layer.

In some embodiments, the pixel structure further includes a pixel electrode, and the pixel electrode penetrates the second insulating layer and contacts the source or the drain, wherein a part of the pixel electrode is directly above the capacitor electrode, and the pixel electrode This portion is different from the shape of the second portion of the second insulating layer.

According to an embodiment of the invention, a pixel structure includes a substrate, a gate, a capacitor electrode, a first insulating layer, an active layer, a drain, and a source. The gate is disposed on the substrate. The capacitor electrode is disposed on the substrate and separated from the gate. The first insulating layer covers the gate and the capacitor electrode, wherein the thickness of the first insulating layer above the gate is greater than the thickness of the first insulating layer The thickness of the top right. The active layer is disposed on the first insulating layer. The drain and the source are disposed on the active layer and are separated from each other.

In some embodiments, the first insulating layer directly above the capacitor electrode has a plurality of protrusions.

In the above embodiment, the capacitor electrode can form a storage capacitor with the extension electrode. Since the first insulating layer has a recess directly above the capacitor electrode, and the extension electrode extends into the recess, the recess can shorten the extension electrode and the capacitor electrode. Distance, thereby increasing the value of the storage capacitor. Since the feedthrough voltage is inversely related to the value of the storage capacitor, an increase in the value of the storage capacitor can help reduce the feedthrough voltage.

The above description is only for explaining the problems to be solved by the present invention, the technical means for solving the problems, the effects thereof, and the like, and the specific details of the present invention will be described in detail in the following embodiments and related drawings.

100‧‧‧Substrate

102‧‧‧ upper surface

200‧‧‧ gate

300‧‧‧Capacitance electrode

400‧‧‧First insulation

410‧‧‧ dent

410a‧‧‧ dent

411‧‧‧ bottom

412‧‧‧ Side wall

413‧‧‧ top edge

420‧‧‧gate insulation

500‧‧‧ active layer

600‧‧‧汲polar

700‧‧‧ source

800‧‧‧Extended electrode

810‧‧‧ dent

820‧‧‧ Protrusion

900‧‧‧Second insulation

910‧‧‧Part 1

920‧‧‧Part II

921‧‧‧ dent

922‧‧‧ Protrusion

1000‧‧‧third insulation

1010‧‧‧Capacitor Coverage

1011‧‧‧ top surface

1012‧‧‧ bottom

1100‧‧‧ pixel electrodes

Section 1120‧‧‧

1200‧‧‧Insulation protrusion

1210‧‧‧ top surface

T1‧‧‧ thickness

T2‧‧‧ distance

T3‧‧‧ distance

T4‧‧‧ distance

D1‧‧ depth

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 1 is a cross-sectional view along line 2 of FIG. 1; FIG. 3 is a top view of a display device according to an embodiment of the present invention; and FIG. 4 is a cross-sectional view along line 4 of FIG. .

The embodiments of the present invention are disclosed in the following drawings, and for the purpose of clarity However, it should be understood by those skilled in the art that the details of the invention are not essential to the details of the invention. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

1 is a top view of a display device in accordance with an embodiment of the present invention. Figure 2 is a cross-sectional view along line 2 of Figure 1. As shown in FIGS. 1 and 2, in the present embodiment, the display device may include a pixel structure including a substrate 100, a gate 200, a capacitor electrode 300, a first insulating layer 400, an active layer 500, and a germanium. The pole 600 and the source 700 and the extension electrode 800. The gate 200 and the capacitor electrode 300 are disposed on the substrate 100 and are separated from each other. For example, the gate 200 and the capacitor electrode 300 may be disposed on the same surface of the substrate 100 (eg, the upper surface 102) at a distance. In some embodiments, the gate 200 can be formed with the capacitive electrode 300 and can comprise the same material. The first insulating layer 400 covers the gate 200 and the capacitor electrode 300.

The drain 600 and the source 700 are disposed on the active layer 500 and are separated from each other. As shown in FIG. 2, the gate 200, the first insulating layer 400, the active layer 500, the drain 600, and the source 700 may form a thin film transistor (TFT) for driving the display device. As shown in FIG. 2, the first insulating layer 400 can separate the capacitor electrode 300 from the extension electrode 800. That is, the capacitor electrode 300 and the extension electrode 800 can be located on opposite sides of the first insulating layer 400 (for example, upper and lower sides) Side) and is completely blocked by the first insulating layer 400 edge. Due to the separation of the capacitor electrode 300 from the extension electrode 800, the capacitor electrode 300 and the extension electrode 800 can form a storage capacitor in the form of a parallel plate capacitor.

，其中C_s為儲存電容值，C_gd為閘極與汲極所產生之電容值，C_FPL為前面板堆疊(front panel lamination；FPL)之電容值，V_GH為電晶體開啟時之閘極電壓值(例如：掃描線通電時之電壓值)，V_GL為電晶體關閉時之閘極電壓值(例如：掃描線關閉時之電壓值)。如此饋通電壓公式所示，饋通電壓值△V與儲存電容值C_s成負相關。因此，儲存電容值的提升將有助於可降低饋通電壓。 It can be understood that the feedthrough voltage value ΔV of the display device satisfies

Where C _s is the storage capacitor value, C _gd is the capacitance value generated by the gate and the drain, C _FPL is the capacitance of the front panel lamination (FPL), and V _GH is the gate when the transistor is turned on. The voltage value (for example, the voltage value when the scan line is energized), and V _GL is the gate voltage value when the transistor is turned off (for example, the voltage value when the scan line is turned off). Thus as shown in formula feed-through voltage, the feed-through voltage △ V value of the storage capacitor C _s a negative correlation. Therefore, an increase in the value of the storage capacitor will help to reduce the feedthrough voltage.

Therefore, the embodiment of the present invention can achieve the effect of the feedthrough voltage reduction by increasing the storage capacitor value. Further, the first insulating layer 400 has a recess 410, and the recess 410 is located directly above the capacitor electrode 300. That is, the recess 410 overlaps the projection of the capacitor electrode 300 on the upper surface 102 of the substrate 100. In some embodiments, the extension electrode 800 can extend from the drain 600 into the recess 410, as shown in FIG. In other embodiments, the extension electrode 800 can also extend from the source 700 into the recess 410. In this way, the distance between the extension electrode 800 and the lower capacitor electrode 300 can be shortened, so that the storage capacitor value formed by the two electrodes can be increased, thereby reducing the feedthrough voltage of the display device.

In some embodiments, as shown in FIG. 2, the first insulating layer 400 includes a gate insulating portion 420 that is located directly above the gate 200, and the gate insulating portion 420 has a thickness thicker than a portion of the first insulating layer 400 located directly above the capacitor electrode 300. That is, the embodiment of the present invention can form the recess 410 of the first insulating layer 400 directly above the capacitor electrode 300 without thinning the gate insulating portion 420. As such, the gate insulating portion 420 can still maintain a sufficient thickness to enable the gate 200 to operate at a high gate voltage.

Specifically, the gate insulating portion 420 has a thickness T1. One bottom surface 411 of the recess 410 is spaced apart from the capacitor electrode 300 by a distance T2. In other words, the distance T2 is also the thickness of the first insulating layer 400 between the bottom surface 411 of the recess 410 and the capacitor electrode 300. As shown in FIG. 2, the thickness T1 of the gate insulating portion is larger than the distance T2 between the bottom surface 411 of the recess 410 and the capacitor electrode 300. That is, the thickness of a portion of the first insulating layer 400 directly above the capacitor electrode 300 can be reduced to be lower than the thickness T1 by the formation of the recess 410. Thereby, the distance between the extension electrode 800 and the capacitor electrode 300 can be shortened to increase the storage capacitance, and the thickness of the gate insulating portion 420 can be not reduced, thereby facilitating high voltage operation. Therefore, by the design in which the thickness T1 is larger than the distance T2, the reduction of the feedthrough voltage and the operation of the high gate voltage can be balanced.

In some embodiments, the recess 410 can be formed by etching the first insulating layer 400. The depth of the recess 410 can then be controlled by the parameters of the etch (eg, the duration of the etchant and/or etch). The recess 410 may taper in a direction toward the substrate 100 due to the characteristics of the etching process. Further, the recess 410 can also have a side wall 412. The side wall 412 is standing on the bottom surface 411 of the recess 410, and the side wall 412 and the bottom surface 411 can define an angle θ. Meanwhile, and the included angle θ is an obtuse angle greater than 90 degrees, so that the recess 410 can be tapered in a direction toward the substrate 100.

In some embodiments, as shown in FIG. 2, the sidewall 412 of the recess 410 is located directly above the capacitor electrode 300. Therefore, the recess 410 as a whole can be positioned directly above the capacitor electrode 300. In other words, the projection of the recess 410 on the upper surface 102 of the substrate 100 is entirely within the capacitive electrode 300. Such a design can help the thickness of the other portion of the first insulating layer 400 not directly above the capacitor electrode 300 to be greater than the distance T2. Thereby, the first insulating layer 400 can be maintained in sufficient insulation.

As shown in FIG. 2, the recess 410 has a top edge 413, and the distance between the top edge 413 and the bottom surface 411 is defined as the depth D1 of the recess 410. The top edge 413 of the recess 410 is separated from the capacitor electrode 300 by a distance T3, and the ratio of the depth D1 to the distance T3 may be between 1/9 and 7/9, but the invention is not limited thereto. The ratio of the depth D1 to the distance T3 described above can help form the desired recess 410 such that the extended electrode 800 in the recess 410 and the lower capacitive electrode 300 can produce a desired storage capacitance value.

As shown in FIG. 2, in some embodiments, the distance T3 between the top edge 413 of the recess 410 and the capacitor electrode 300 may be substantially the same as the thickness T1 of the gate insulating portion 420, so the thickness of the gate insulating portion 420. The ratio of T1 to the depth D1 of the recess may also be between 1/9 and 7/9, but the invention is not limited thereto.

In some embodiments, as shown in FIG. 2, the bottom surface 411 of the recess 410 is spaced apart from the capacitor electrode 300 by a distance T2 of between about 1000 Å and about 4000 Å. In some embodiments, the distance T3 is about 4500 Å, and The depth D1 is between approximately 500 Å and 3500 Å.

As shown in FIG. 2, since the extension electrode 800 extends into the recess 410, the extension electrode 800 may have a recess 810 located in the recess 410. In some embodiments, the recess 810 is substantially identical in shape to the recess 410. Further, the recess 810 may taper in a direction toward the substrate 100.

In some embodiments, as shown in FIG. 2, the pixel structure further includes a second insulating layer 900, the second insulating layer 900 has a first portion 910 and a second portion 920 connected thereto, and the first portion 910 covers the active Layer 500, source 700 and drain 600, and second portion 920 cover extension electrode 800. In some embodiments, as shown in FIG. 2, the second portion 920 is conformal to the extension electrode 800. In other words, the second portion 920 can have a recess 921 that is substantially identical in shape to the recess 810 of the extended electrode 800. Further, the recess 921 may be tapered in a direction toward the substrate 100.

In some embodiments, as shown in FIG. 2, the pixel structure further includes a third insulating layer 1000, and the third insulating layer 1000 covers the second insulating layer 900, wherein the third insulating layer 1000 has a capacitor covering portion 1010, and the capacitor covers The portion 1010 is located directly above the capacitor electrode 300, and the capacitor covering portion 1010 has opposite top surfaces 1011 and bottom surfaces 1012, and the top surface 1011 and the bottom surface 1012 have different shapes. In some embodiments, the top surface 1011 can be a substantially flat surface, and the bottom surface 1012 is conformal with the second portion 920 of the second insulating layer 900, that is, the bottom surface 1012 is locally raised to embed the second portion 920. The depression 921.

In some embodiments, as shown in FIG. 2, the pixel structure further includes a pixel electrode 1100, and the pixel electrode 1100 penetrates the third insulating layer 1000. The drain 600 is in contact with the second insulating layer 900. In other embodiments, the pixel electrode 1100 can also contact the source 700 without contacting the drain 600. A portion 1120 of the pixel electrode 1100 is located directly above the capacitor electrode 300. Portion 1120 of pixel electrode 1100 is located on top surface 1011 of capacitor cover 1010 and conforms to top surface 1011. Since the second portion 920 of the second insulating layer 900 is not conformal to the top surface 1011 of the capacitor covering portion 1010, the portion 1120 of the pixel electrode 1100 and the second portion 920 of the second insulating layer 900 are different in shape. For example, portion 1120 of pixel electrode 1100 can be substantially flat.

In some embodiments, the material of the pixel electrode 1100 may include a metal such as aluminum, platinum, silver, titanium, molybdenum, zinc, tin, Chromium or other suitable metal or alloy, but the invention is not limited thereto. In other embodiments, the material of the pixel electrode 1100 may also include a transparent conductive material.

FIG. 1 illustrates an exemplary configuration of the recess 410 in the pixel structure, wherein the shape of the outline of the recess 410 in the upper view may be a rectangle. In other embodiments, the shape of the contour of the recess 410 in the upper view may also be a circle, an ellipse or other polygon or the like.

3 is a top view of a display device in accordance with an embodiment of the present invention. Figure 4 is a cross-sectional view along line 4 of Figure 3. The main difference between the pixel structure of the present embodiment and the pixel structure is that, in the embodiment, the pixel structure further includes at least one insulating protrusion 1200 protruding from the bottom surface 411 of the recess 410. In some embodiments, as shown in FIG. 4, The number of at least one insulating protrusion 1200 is a plurality, and the insulating protrusions 1200 are spaced apart from each other on the bottom surface 411 of the recess 410. The other features shown in Fig. 4 and those already mentioned in Figs. 1 and 2 are as described above with reference to Figs. 1 and 2, and the description will not be repeated in order to maintain the simplicity of the specification.

In some embodiments, as shown in FIG. 4, the insulating protrusion 1200 and the first insulating layer 400 may be integrally formed, so that the structural strength of both may be improved. That is, the insulating protrusion 1200 and the first insulating layer 400 may contain the same material. As such, the insulating protrusions 1200 can be formed by etching on the first insulating layer 400. Therefore, the number and arrangement of the insulating protrusions 1200 disposed in the recess 410 can be designed according to the desired storage capacitance value, and the desired feedthrough voltage can be obtained. In some embodiments, the insulating protrusions 1200 may be tapered in a direction toward the substrate 100 based on the characteristics of the etching. In some embodiments, since the plurality of insulating protrusions 1200 are formed by the same etching process for the first insulating layer 400, the insulating protrusions 1200 may have the same thickness.

In the present embodiment, the recess 410 is partitioned into a plurality of recesses 410a by the insulating protrusions 1200. In some embodiments, as shown in FIG. 3, the recesses 410a may be arranged in an array in the pixel structure, but the invention is not limited thereto. The shape of the outline of the recess 410a in the upper view may be a rectangle, a circle, an ellipse, or other polygons, etc., but the invention is not limited thereto. Other features shown in FIGS. 3 and 4 that have been mentioned in FIGS. 1 and 2 are as described above with respect to FIGS. 1 and 2, and will not be repeated in order to maintain the simplicity of the specification. Narrative.

In some embodiments, as shown in FIG. 4, the insulating protrusions The top surface 1210 of the 1200 is separated from the capacitor electrode 300 by a distance T4, and the ratio of the depth D1 of the recess 410 to the distance T4 is between 1/9 and 7/9. In some embodiments, the distance T4 can be substantially the same as the distance T3.

In some embodiments, as shown in FIG. 4, the extension electrode 800 may further have at least one protrusion 820. The protrusion 820 is located directly above the insulating protrusion 1200 and conforms to the insulating protrusion 1200. As shown in FIG. 4, the extension electrode 800 may have a plurality of protrusions 820 located directly above the plurality of insulating protrusions 1200, respectively. Therefore, the extension electrode 800 has an undulating shape and has a plurality of alternately arranged peaks and troughs. In some embodiments, since the protrusions 820 are conformal to the insulating protrusions 1200, the protrusions 820 may also be tapered in a direction toward the substrate 100.

In some embodiments, as shown in FIG. 4, the second portion 920 of the second insulating layer 900 may further have at least one protrusion 922. The protrusion 922 is located directly above the protrusion 820 and conforms to the protrusion 820. Thus, as shown in FIG. 4, the second portion 920 can be undulating and have a plurality of alternating peaks and troughs.

In some embodiments, as shown in FIG. 4, the bottom surface 1012 of the capacitor cover 1010 is conformal with the second portion 920 of the second insulating layer 900. Thus, the bottom surface 1012 can be undulating with a plurality of alternating peaks and troughs.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧Substrate

102‧‧‧ upper surface

200‧‧‧ gate

300‧‧‧Capacitance electrode

400‧‧‧First insulation

410‧‧‧ dent

411‧‧‧ bottom

412‧‧‧ Side wall

413‧‧‧ top edge

420‧‧‧gate insulation

500‧‧‧ active layer

600‧‧‧汲polar

700‧‧‧ source

800‧‧‧Extended electrode

810‧‧‧ dent

900‧‧‧Second insulation

910‧‧‧Part 1

920‧‧‧Part II

921‧‧‧ dent

1000‧‧‧third insulation

1010‧‧‧Capacitor Coverage

1011‧‧‧ top surface

1012‧‧‧ bottom

1100‧‧‧ pixel electrodes

Section 1120‧‧‧

T1‧‧‧ thickness

T2‧‧‧ distance

T3‧‧‧ distance

D1‧‧ depth

Claims (18)

A pixel structure includes: a substrate; a gate disposed on the substrate; a capacitor electrode disposed on the substrate and separated from the gate; a first insulating layer covering the gate and the capacitor An electrode, wherein the first insulating layer has a recess, and the recess is located directly above the capacitor electrode; an active layer is disposed on the first insulating layer; a drain and a source are disposed on the active layer Separating from each other; and an extension electrode extending from the drain or the source into the recess. The pixel structure of claim 1, wherein the first insulating layer comprises a gate insulating portion directly above the gate, and a thickness of the gate insulating portion is greater than a bottom surface of the recess and the capacitor electrode A distance apart. The pixel structure of claim 1, wherein one of the sidewalls of the recess is located directly above the capacitor electrode. The pixel structure of claim 1, wherein the recess has a depth, and a top edge of the recess is separated from the capacitor electrode by a distance from the distance between 1/9 and 7/9. between. The pixel structure as claimed in claim 1, wherein the recess One of the bottom surfaces is spaced from the capacitor electrode by a distance between 1000 Å and 4000 Å. The pixel structure of claim 1, further comprising: at least one insulating protrusion protruding from a bottom surface of the recess. The pixel structure of claim 6, wherein the insulating protrusion is integrally formed with the first insulating layer. The pixel structure of claim 6, wherein the number of the at least one insulating protrusions is plural, and the insulating protrusions are spaced apart from each other on the bottom surface of the recess. The pixel structure of claim 8, wherein the insulating protrusions have the same thickness. The pixel structure of claim 6, wherein the recess has a depth, and a top surface of the insulating protrusion is spaced apart from the capacitor electrode by a distance between 1/9 and 7/9 between. The pixel structure of claim 6, wherein the extension electrode extends further to the insulating protrusion. The pixel structure according to claim 1, wherein the extension electrode has an undulating shape and has a plurality of peaks and troughs alternately arranged. The pixel structure of claim 1, further comprising: a second insulating layer having a first portion and a second portion connected to each other, the first portion covering the active layer, the source and the drain, The second portion covers the extension electrode, and the second portion has an undulating shape and has a plurality of alternately arranged peaks and troughs. The pixel structure of claim 13, further comprising: a third insulating layer covering the second insulating layer, wherein the third insulating layer has a capacitor covering portion directly above the capacitor electrode, and the capacitor The cover portion has a top surface and a bottom surface, and the top surface has a different shape from the bottom surface. The pixel structure of claim 14, wherein the bottom surface of the capacitor cover is conformal to the second portion of the second insulating layer. The pixel structure of claim 13, further comprising: a pixel electrode extending through the second insulating layer and contacting the source or the drain, wherein a portion of the pixel electrode is directly above the capacitor electrode And the portion of the pixel electrode is different from the shape of the second portion of the second insulating layer. A pixel structure includes: a substrate; a gate disposed on the substrate; a capacitor electrode disposed on the substrate and separated from the gate; a first insulating layer covering the gate and the capacitor electrode, wherein a thickness of the first insulating layer above the gate is greater than the first insulation a layer directly above the capacitor electrode; an active layer disposed on the first insulating layer; and a drain and a source disposed on the active layer and separated from each other. The pixel structure of claim 17, wherein the first insulating layer directly above the capacitor electrode has a plurality of protrusions.