TWI612421B - Method of dynamically arranging data for flash memory - Google Patents

Abstract

The invention discloses a method for dynamically aligning data of a flash memory, which is applied to a flash storage device having a microcontroller and a flash memory, and includes the following steps: the microcontroller receives a data writing instruction including a logical start address ; Obtain the cumulative offset and update the cumulative offset based on the logical start address and the configuration unit capacity of the flash memory; add the updated logical offset to the logical start address to obtain the physical start address; And, starting from the physical start address of the flash memory, the data corresponding to the data write command is written into the flash memory. The invention can effectively improve the random read and write efficiency of the flash memory.

Description

Method for dynamically aligning data of flash memory

The invention relates to flash memory, in particular to a method for dynamically aligning data of flash memory.

Flash memory (flash memory 10 as shown in FIGS. 1A and 1B) has the characteristics of full page writing and block erasing, that is, when data is written, the page must be used as the minimum writing unit. When erasing data, the minimum erasing unit must be the block containing multiple pages.

In order to improve the data writing efficiency of the flash memory according to the above characteristics of the flash memory, the existing flash storage device is provided with a set of buffer memory (buffer memory 12 as shown in FIGS. 1A and 1B), and its capacity It is the same as the single page capacity of the flash memory 10 (such as 4096 bytes, or 4KB). When receiving the data to be written into the flash memory 10, the flash storage device arranges and stores the received data in the buffer memory 12, and fills the remaining space of the buffer memory 12, and then All the arranged data in the buffer memory 12 is written to the specific physical start address of the flash memory 10. In this way, the flash storage device can quickly write data to the flash memory 10 in units of pages.

Please refer to FIG. 1A, which is a schematic diagram of an existing sequential write and is used to explain how an existing flash storage device performs sequential write in units of pages. First, the flash storage device sequentially receives three pieces of data to be written from the outside (usually the host). Then, the flash storage device uses part of the first data The data D11 and the old data X1 of the flash memory 10 fill the buffer memory 12, and all the data of the buffer memory 12 are directly written into the flash memory 10. Next, the flash storage device clears the buffer memory 12, and fills the buffer memory 12 with the remaining data D12 of the first data and part of the data D21 of the second data (the data addresses of multiple pieces of data written in sequence are Continuous), and write all the data of the buffer memory 12 directly into the flash memory 10. Next, the flash storage device clears the buffer memory 12, fills the buffer memory 12 with the remaining data D22 of the second data and part of the data D31 of the third data, and directly writes all the data of the buffer memory 12 to the flash memory Flash memory 10. Finally, the flash storage device fills the buffer memory 12 with the remaining data D32 of the third data and the old data X2 of the flash memory 10, and writes all the data of the buffer memory 12 directly into the flash memory 10. Thereby, the flash storage device can write multiple pieces of data to the flash memory 12 in units of pages.

Please continue to refer to FIG. 1B, which is a schematic diagram of an existing random write to illustrate how the existing flash storage device performs random write in units of pages.

First, the flash storage device sequentially receives three data to be written and the write address of each data from the outside. Then, the flash storage device fills the buffer memory 12 with the partial data D11 of the first data and the old data X1 of the flash memory 10, and according to the write address of the first data, all of the buffer memory 12 The data is written directly into the flash memory 10. Then, the flash storage device clears the buffer memory 12, fills the buffer memory 12 with the remaining data D12 of the first data and the old data X2 of the flash memory 10, and according to the write address of the first data All data in the buffer memory 12 is directly written into the flash memory 10. With this, the flash storage device completes the writing of the first data.

Then, the flash storage device fills the buffer memory 12 with the partial data D21 of the second data and the old data X3, and writes all the data of the buffer memory 12 to the flash memory according to the write address of the second data 10. Empty the buffer memory 12, the remaining data D22 and the old data X4 of the second data The buffer memory 12 is filled, and all data of the buffer memory 12 is written into the flash memory 10 according to the writing address of the second data. With this, the flash storage device completes writing the second data.

Then, the flash storage device fills the buffer memory 12 with the partial data D31 of the third data and the old data X5, and writes all the data of the buffer memory 12 to the flash memory according to the write address of the third data 10. Empty the buffer memory 12, fill the buffer memory 12 with the remaining data D32 of the third data and the old data X6, and write all the data of the buffer memory 12 according to the write address of the third data Flash memory 10. With this, the flash storage device completes the writing of the third data.

In order to perform random writing in units of pages, the existing flash storage device must fill the remaining space of the buffer memory 12 with the old data of the flash memory 10, resulting in poor writing performance.

Taking FIG. 1B as an example, if the single-page capacity of flash memory 10 (that is, the capacity of buffer memory 12) is 4KB, the existing flash storage device must be performed twice in order to write each data (occupying 4KB of space) Write operation (a total of 8KB of data is written), that is, an additional 4KB of old data must be written, and the write bandwidth is wasted.

The main object of the present invention is to provide a method for dynamically aligning data in a flash memory, which can effectively reduce the amount of redundant data when data is randomly written into the flash memory.

In one embodiment, a method for dynamically aligning data of a flash memory is applied to a flash storage device having a microcontroller and a flash memory, including: a) controlling the microcontroller to continuously detect the A usage state of the flash storage device; b) receiving a data write command, where the data write command includes a logical start address; c) obtaining a cumulative offset when the usage state matches a required alignment state , And update the accumulation based on the logical start address and a configuration unit capacity of the flash memory Offset to obtain an updated cumulative offset; d) the logical start address is added to the updated cumulative offset to obtain a physical start address; and e) from the flash memory The starting address of the entity starts writing data corresponding to the data writing instruction into the flash memory.

In one embodiment, a method for dynamically aligning data of a flash memory is applied to a flash storage device having a microcontroller and a flash memory, including: a) controlling the microcontroller to receive a first A data writing instruction, wherein the first data writing instruction includes a first logical start address; b) according to the first logical start address, a configuration unit capacity of the flash memory and an initial cumulative bias Calculate a first cumulative offset; c) add the first logical start address to the first cumulative offset to obtain a first physical start address; d) from the flash memory The start address of the first entity starts to write data corresponding to the first data write command to the flash memory; e) receives a second data write command, wherein the second data write command includes a A second logical start address; f) calculating a second cumulative offset based on the second logical start address, the configuration unit capacity and the first cumulative offset; g) starting the second logical start Add the second cumulative offset to obtain a second physical start address; and h) from the fast The second physical start address of the flash memory starts to write data corresponding to the second data write command into the flash memory.

The invention can effectively improve the random read and write efficiency of the flash memory.

10‧‧‧Flash memory

12‧‧‧buffer memory

20‧‧‧Flash storage device

200‧‧‧Flash memory

202‧‧‧buffer memory

204‧‧‧Microcontroller

22‧‧‧Host

X1-X6‧‧‧Old data

D11, D12, D21, D22, D31, D32, A1, A2, B1, B2, C1, C2

O1, O2, O3‧‧‧single offset

S10-S16‧‧‧ Writing procedure

S200-S220‧‧‧Reading and writing steps

FIG. 1A is a schematic diagram of conventional sequential writing.

FIG. 1B is a schematic diagram of existing random writing.

FIG. 2 is a structural diagram of a flash storage device according to a first embodiment of the invention.

FIG. 3 is a flowchart of a method for dynamically aligning data in a first embodiment of the present invention.

4 is a flowchart of a method for dynamically aligning data in a second embodiment of the present invention.

5 is a schematic diagram of continuous alignment of the present invention.

FIG. 6 is a schematic diagram of the random write of FIG. 5.

7 is a schematic diagram of conditional alignment of the present invention.

FIG. 8 is a schematic diagram of the random write of FIG. 7.

The following is a detailed description of a preferred embodiment of the present invention with reference to the drawings.

Please refer first to FIG. 2, which is a structural diagram of a flash storage device according to a first embodiment of the present invention. The flash storage device 20 of the present invention mainly includes a flash memory 200, a buffer memory 202, and a microcontroller 204.

Flash memory 200 (such as NAND flash memory) is used to store data, including multiple blocks (Block, the smallest unit of data erasing), each block includes multiple pages (ie, data access The smallest unit).

The buffer memory 202 is electrically connected to the flash memory 200 for temporarily storing data. Moreover, the capacity of the buffer memory 202 is a multiple of the page capacity of the flash memory 200 (such as 4KB, 8KB, or 16KB).

The microcontroller 204 (such as an MCU) is electrically connected to the buffer memory 202 and can be electrically connected (such as via a USB interface or a SATA interface) to the external host 22. The microcontroller 204 can write data to the flash memory 200 via the buffer memory 202 or write data from the flash memory 200 via the buffer memory 202 according to the data writing instruction or the data reading instruction from the host 22 read out.

Please refer to FIG. 3 for a flow chart of the method for dynamically aligning data in the first embodiment of the present invention. The dynamic data alignment method in each embodiment of the present invention is mainly implemented by the flash storage device 20 shown in FIG. 2. Specifically, the flash storage device 20 further includes firmware, which can be stored In the built-in memory of the microcontroller 204. Moreover, after the microcontroller 204 executes the aforementioned firmware, the flash storage device 20 can be controlled to execute the steps of the dynamic data alignment method of each embodiment of the present invention. The dynamic alignment data method of this implementation includes the following steps.

Step S10: The microcontroller 204 determines whether a data writing request is received. Specifically, the microcontroller 204 determines whether any data writing instruction has been received from the host 22.

In one embodiment, the data write command includes a set of logical start addresses based on the logic block address (Logic Block Address) mechanism and the data length of the data to be written. More specifically, the logical block addressing mechanism is a general mechanism that describes the address of the data on the storage device of the computer (such as the host 22), and the logical start address based on this mechanism can be recognized by most computers.

If the microcontroller 204 receives the data writing instruction, step S12 is executed. Otherwise, the dynamic alignment data method ends.

Step S12: The microcontroller 204 obtains the cumulative offset and the configuration unit capacity of the flash memory 200, and updates the acquired cumulative offset according to the acquired configuration unit capacity to obtain the updated cumulative offset.

Specifically, the microcontroller 204 calculates the updated cumulative offset based on the acquired cumulative offset and the configuration unit capacity. The configuration unit capacity (such as 4KB, 8KB, or 16KB) is the single-time minimum access capacity of the flash memory 200, that is, the capacity of a single page of the flash memory 200, which is manufactured by the manufacturer when the flash memory 200 is shipped from the factory Set based on hardware specifications.

The cumulative offset is used to indicate the address offset between the general logical start address and the physical start address based on the addressing mechanism of the flash memory 200.

In addition, the initial value of the accumulated offset is 0 (that is, the flash memory 200 has not been written with data, or the address offset operation has not been performed although data has been written), and is executed as the address offset operation is performed The frequency gradually increased.

Step S14: The microcontroller 204 calculates a group of physical start addresses corresponding to the logical start address according to the logical start address of the data writing instruction and the updated cumulative offset.

In one embodiment, the microcontroller 204 uses the logical start address plus the updated cumulative offset as the corresponding physical start address, where the corresponding way can be determined by the microcontroller 204, and this way It can be well known to those with ordinary knowledge in the art, so it will not be repeated here.

Step S16: The microcontroller 204 writes the data corresponding to the data write command into the flash memory 200 starting from the physical start address of the flash memory 200.

In one embodiment, the microcontroller 204 first writes the data arrangement corresponding to the data write instruction to the buffer memory 202, and then starts to write the arranged data from the physical start address of the flash memory 200. The buffer memory 202 is directly written into the flash memory 200.

It is worth mentioning that in the prior art, when the logical start address is not aligned with the physical start address of any page of the flash memory 200, if the logical start address is directly used as the physical start address Writing data will cause the data to be written into two different pages, which reduces the writing efficiency (two write operations for one piece of data). Therefore, in the present invention, the address offset operation is first performed during the write operation to calculate the address offset between the logical start address and the physical start address closest to the page (ie step S12), and Perform offset compensation to obtain the physical start address of a specific page (ie, step S14). In this way, when the microcontroller 204 continuously writes data from the physical start address to the cache memory 200 (ie, step S16), the written data will be located on the same page, which can improve the writing efficiency ( (One write only needs to be written once).

Then, the microcontroller 204 executes step S10 again to determine whether another write request is received.

Please refer to FIG. 5, which is a schematic diagram of continuous alignment of the present invention to exemplify how the present invention performs data alignment and random write operations. Figure 5 (A) shows a schematic diagram of the logical block addressing mechanism FIG. 5 (B) is a schematic diagram of the addressing mechanism of the flash memory 200. In this example, the single page size of the flash memory 200 is 8 KB, and the initial value of the cumulative offset (that is, the initial cumulative offset) is 0.

The microcontroller 204 receives the data write command from the host 22 for the first time, that is, the first data write command write (4,8), which means that the first logical start address is 4 (meaning 4K, which is 4096), and is to be written The first data length of the data is 8 (the unit is KB, which is Kilo Bytes). Next, the microcontroller 204 determines that the first logical start address is not aligned with the physical start address (such as 0, 8, 16 ...) of any page that can be written to the flash memory 200 and the execution bit is required Address offset operation, and calculate the single offset O1 (ie the first offset) is 4 (meaning 4K, that is 4096), that is, the first logical start address can be aligned after offset by the first offset The physical start address of the specific writable page of the flash memory 200 (ie, the first physical start address).

Next, the microcontroller 204 updates the initial cumulative offset to obtain the updated cumulative offset (which is 4, which is the first cumulative offset), and adds the first cumulative offset to the first logical start address (4) Shift the amount (4) to obtain the corresponding first physical start address (8), and continuously write the data of the first data write command from the first physical start address (8) of the flash memory 200 . In this way, data that is not aligned to any writable page of the flash memory 200 can be written to the same page (that is, the page corresponding to the first physical start address (8)).

In addition, the microcontroller 204 can also execute a record instruction record (4, 4) to record the first logical start address (4) and the corresponding first cumulative offset (4) in the lookup table, to For reading this data in the future.

When the microcontroller 204 receives the data write command (ie, the second data write command write (24, 8)) from the host 22 again, it can determine the second logical start address (24) plus the latest first accumulation The offset (4) is not aligned with the physical start address (such as 32) of any writeable page of the flash memory 200, but the address offset operation must be performed and the single offset O2 ( That is, the second offset) is 4.

Next, the microcontroller 204 updates the first cumulative offset to obtain the updated cumulative offset (8, that is, the second cumulative offset, adding the second to the previous first cumulative offset (4) Offset (4)), add the second logical start address (24) to the second cumulative offset (8) to obtain the corresponding second physical start address (32), and from the flash memory 200 The second physical start address (32) starts to continuously write the data of the second data writing instruction. Furthermore, the microcontroller 204 also executes a record instruction record (24, 8) to record the second logical start address (24) and the corresponding second cumulative offset (8) in the lookup table.

When the microcontroller 204 receives the data write command (ie, the third data write command write (36, 8)) from the host 22 again, it can determine the third logical start address (36) plus the latest second accumulation The offset (8) is not aligned with the physical start address (such as 48) of any writable page of the flash memory 200, but the address offset operation must be performed and the single offset O3 ( That is, the third offset) is 4.

Next, the microcontroller 204 updates the cumulative offset to obtain the updated cumulative offset (12, which is the third cumulative offset), and adds the third cumulative start offset (36) to the third cumulative offset (12) to obtain the corresponding third physical start address (48), and continuously write data of the third data write command from the third physical start address (48) of the flash memory 200. In this way, the data of any page of the originally unaligned flash memory 200 will be written to the same page (that is, the page corresponding to the physical start address (48)). Moreover, the microcontroller 204 also executes a record instruction record (36, 12) to record the third logical start address (36) and the corresponding third cumulative offset (12) in the lookup table.

Please continue to refer to FIG. 6, which is a schematic diagram of the random write of FIG. 5 to explain in more detail how the present invention performs a random write operation. In this example, the capacity of the buffer memory 202 is the same as the single page capacity of the flash memory 200 (for example, both are 8KB).

The microcontroller 204 first writes the data (including sub-data A1, A2) of the first data write command into the buffer memory 202, and then starts buffering from the first physical start address of the flash memory 200 All data of the memory 202 is written to a specific page of the flash memory 200.

Next, the microcontroller 204 clears the buffer memory 202, and writes the data (including the sub-data B1, B2) of the second data write command to the buffer memory 202, and then from the flash memory 200 The second physical start address starts to write all the data of the buffer memory 202 to a specific page of the flash memory 200.

Next, the microcontroller 204 clears the buffer memory 202, and writes the data (including sub-data C1, C2) of the third data write command to the buffer memory 202, and then from the third entity of the flash memory 200 The starting address starts to write all the data of the buffer memory 202 to a specific page of the flash memory 200.

It is worth mentioning that, after the foregoing operations, the logical start address of each data write command has been converted to the physical start address of the specific page in the aligned flash memory 200, that is, the The data will be written to the same page (only one write operation is required), but not to different pages (that is, multiple write operations are not required).

The present invention can effectively write data to the same page of the flash memory by performing an address offset operation on the logical start address, and can effectively reduce the number of writes, thereby extending the life of the flash memory and effectively fast Random read and write efficiency of flash memory.

Although the dynamic data alignment method in the foregoing embodiment can effectively reduce the number of flash memory writes, however, each time the address offset operation is performed, the capacity of the flash memory is wasted (a single offset shown in FIG. 5) The memory space corresponding to the shifts O1, O2, O3 will not store data.) If the address offset operation is performed on all data write commands, the available capacity of the flash memory will be quickly reduced.

To solve the above problem, the present invention further proposes another dynamic data alignment method, which can achieve a balance between reducing the number of writes and reducing the waste of flash memory capacity. Please refer to FIG. 4 for a flow chart of a method for dynamically aligning data according to a second embodiment of the present invention. The method for dynamically aligning data in this embodiment includes the following steps.

Step S200: The microcontroller 204 continuously detects the use state of the flash storage device 20. The aforementioned usage state may be the number of writes or duration accumulated during the period of unupdated cumulative offset, and the fast The remaining available capacity of the flash memory 200 or the total number of writing or erasing times of a specific block (block) are not limited thereto.

Step S202: The microcontroller 204 determines whether a data reading and writing request is received. Specifically, the microcontroller 204 determines whether any data writing instruction or any data reading instruction is received from the host 22.

In one embodiment, the data read command includes a set of logical start addresses based on the logical block addressing mechanism and the data length of the data to be read.

If the microcontroller 204 receives the data writing instruction, step S204 is executed. If the microcontroller 204 receives the data reading instruction, step S216 is executed. If the microcontroller 204 does not receive any data read and write commands, the dynamic data alignment method ends.

Step S204: The microcontroller 204 determines whether the detected usage state meets the preset required alignment state.

For example, the microcontroller 204 can determine whether the cumulative number of writes (such as 8) during the period of continuous unupdated cumulative offset is not less than the preset number of writes (such as 10), and the period of continuous unupdated cumulative offset Whether the duration of the flash memory (such as 3 minutes) is not less than the preset duration (such as 5 minutes), and whether the remaining available capacity of the flash memory 200 (such as 30GB) is greater than the preset capacity (such as 1GB) or a specific block (Block) Whether the total write times or total erase times (such as 50,000 times) is greater than the preset write times or preset erase times (such as 80,000 times).

If the micro-controller 204 determines that the current usage state meets the alignment-needed state, step S206 is executed to perform the address offset operation and then the write operation. If it is determined that the current use state does not match the alignment-required state, the microcontroller 204 executes step S210 to directly perform the write operation.

Step S206: The microcontroller 204 calculates a single offset (the first offset as shown in FIG. 5) according to the logical start address of the data writing instruction, the cumulative offset, and the configuration unit capacity of the flash memory 200 O1, the second offset O2 or the third offset O3).

In one embodiment, the sum of the logical start address, the cumulative offset, and the calculated single offset is a multiple of the configuration unit capacity of the flash memory 200. For example, if the logical start address is 4, the cumulative offset is 0, and the configuration unit capacity is 8, then the single offset can be 4 (optimum), 12, 20, etc.

In another example, the microcontroller 204 calculates the sum (28) of the logical start address (such as 24) and the cumulative offset (such as 4), and then calculates the sum divided by the configured unit capacity (such as 8) The remainder (4), and calculate the difference (4) between the configuration unit capacity (8) and this remainder (4), and then use the difference (4) as the single offset (4).

Step S208: The microcontroller 204 updates the cumulative offset. Specifically, the microcontroller 204 adds the calculated single offset to the acquired cumulative offset to obtain the updated cumulative offset.

Step S210: The microcontroller 204 adds the updated logical offset to the logical start address of the data write command to obtain the physical start address.

It is worth mentioning that, if the use state matches the alignment-needed state, the microcontroller 204 adds the updated cumulative offset obtained in step S208 as the physical start address. If the usage state does not match the alignment required state (that is, the cumulative offset will not be updated during this write operation), the microcontroller 204 uses the logical start address plus the acquired cumulative offset as the physical start Address.

Step S212: The microcontroller 204 first writes the data arrangement corresponding to the data write command to the buffer memory 202, and then starts to write the arranged data from the buffer memory from the physical start address of the flash memory 200 202 is directly written into the flash memory 200.

Step S214: the microcontroller 204 writes the logical start address of the data write command and the latest cumulative offset (if updated, the updated cumulative offset; if not updated, the obtained cumulative offset The shift amount) corresponds to the record in the lookup table. Then the microcontroller 204 executes step S202 again.

If the microcontroller 204 receives the data read command in step S202, step S216 is executed: the microcontroller 204 queries the lookup table to obtain the logical start address corresponding to the data read command. Product offset (ie, the updated cumulative offset recorded in step S214 or the acquired cumulative offset).

Taking Figure 5 as an example, the lookup table records three records of record (4, 4), record (24, 8), and record (36, 12). If the logical start address of the data read instruction is 4, the corresponding cumulative offset is 4, if the logical start address is 24, the corresponding cumulative offset is 8, if the logical start address is 36, the corresponding cumulative offset is 12.

Step S218: The microcontroller 204 adds the logical start address of the data read instruction to the accumulated offset found to obtain the corresponding physical start address. For example, if the logical start address is 24 and the cumulative offset is 8, the corresponding physical start address is 32.

Step S220: The microcontroller 204 continuously reads the data corresponding to the data reading instruction from the physical start address of the flash memory 200 according to the data length of the data reading instruction.

In one embodiment, the microcontroller 204 first reads the data corresponding to the data read command continuously from the physical start address of the flash memory 200, and stores the read data in the buffer memory 202 In the process, the data stored in the buffer memory 202 is sent to the source of the data read command (such as the host 22).

It is worth mentioning that since the present invention has aligned all the data stored in the flash memory 200 with each page (ie, the data corresponding to each data write command will be stored on the same page), when the data is to be read At this time, the microcontroller 204 only needs to perform a read operation (read a single page) on the flash memory 200 once, which can effectively improve the read efficiency. .

Please refer to FIG. 7, which is a schematic diagram of conditional alignment of the present invention, to exemplify how the present invention performs conditional data alignment and random write operations conditionally. FIG. 7 (A) shows a schematic diagram of the logical block addressing mechanism, and FIG. 7 (B) shows a schematic diagram of the flash memory 200 addressing mechanism. In this example, the single page size of the flash memory 200 is 8KB, and the initial value of the cumulative offset (that is, the initial cumulative offset) is 0. In addition, the microcontroller 204 performs the address offset operation at intervals, that is, the data alignment is performed only when the data write command is received an odd number of times (eg, 1, 3, 5, 7, ...).

The microcontroller 204 receives the data write command from the host 22 for the first time, namely the first data write command write (4, 8). Then, the microcontroller 204 judges that data alignment needs to be performed according to the setting (this is an odd number of times), and further determines that the first logical start address is not aligned with the physical start bit of any writable page of the flash memory 200 The address offset operation must be performed and the single offset O1 (ie the first offset) is calculated to be 4.

Then, the microcontroller 204 updates the cumulative offset to obtain the updated cumulative offset (4, that is, the first cumulative offset), and adds the first cumulative offset to the first logical start address (4) Amount (4) to obtain the corresponding first physical start address (8), and continuously write data of the first data write command from the first physical start address (8) of the flash memory 200. Moreover, the microcontroller 204 also executes a record instruction record (4, 4) to record the first logical start address (4) and the corresponding first cumulative offset (4) in the lookup table.

When the microcontroller 204 receives the data write command (ie, the second data write command write (24, 8)) from the host 22 for the second time, it can judge according to the setting that data alignment is not required (this time is an even number of times), And the latest first cumulative offset (4) is directly obtained and directly used as the second cumulative offset, and the second logical start address (24) is added to the second cumulative offset (4) to obtain the corresponding The second physical start address (28), and the data of the second data write command is continuously written from the physical start address (28) of the flash memory 200. Moreover, the microcontroller 204 also executes a record instruction record (24, 4) to record the second logical start address (24) and the corresponding second cumulative offset (4) in the lookup table.

As can be seen from FIG. 7 (B), the data of the second data writing instruction is not aligned with the single page of the flash memory 200, which makes the reading and writing efficiency of this data poor. Moreover, since the address offset operation is not performed, no extra capacity is wasted in this write operation.

When the microcontroller 204 receives the data write command from the host 22 for the third time (ie, the third data write command write (36, 8)), it can determine that the data alignment needs to be performed according to the setting (this is an odd number of times), and Further determine the third logical start address (36) plus the latest second cumulative offset (4) to align the physical start address (eg 40) of the specific page of the flash memory 200 without executing The address offset operation calculates the single offset O3 (ie, the third offset) as 0, and the second cumulative offset (4) can be directly used as the third cumulative offset.

Next, the microcontroller 204 adds the third logical start address (36) to the third cumulative offset (4) to obtain the corresponding third physical start address (40), and then flash memory 200 The starting address (40) of the third entity starts to continuously write the data of the third data writing instruction. In addition, the microcontroller 204 also executes a record instruction record (36, 4) to record the third logical start address (36) and the corresponding third cumulative offset (4) in the lookup table.

In this way, the data of the originally unaligned third data writing instruction will be written to the same page after data alignment.

Please continue to refer to FIG. 8, which is a schematic diagram of the random write of FIG. 7 to explain in more detail how the random write operation of the present invention is performed. In this example, the capacity of the buffer memory 202 is the same as the single page capacity of the flash memory 200 (for example, both are 8KB).

Since the data of the first data write command has been data aligned (the sub data A1 and A2 are on the same page), the microcontroller 204 only needs to perform one write operation to buffer all the data of the first data write command The memory 202 writes a specific page of the flash memory 200.

Since the data of the second data write command is not aligned (the sub-data B1 and B2 are on different pages), the microcontroller 204 must perform two write operations to write all the data of the second data write command In the flash memory 200, the first time is to fill the buffer memory 202 with the sub-data B1 and the old data X1 of the flash memory 200, and then write to a specific page of the flash memory 200, the second time Yes After filling the buffer memory 202 with the sub-data B2 and the old data X2 of the flash memory 200, the specific page of the flash memory 200 is written.

Since the data of the third data write command has been data aligned (the sub data C1 and C2 are on the same page), the microcontroller 204 only needs to perform one write operation to buffer all the data of the third data write command The memory 202 writes a specific page of the flash memory 200.

By performing data alignment conditionally, the present invention can effectively reduce the number of writes and reduce the waste of flash memory capacity.

The above are only the preferred specific examples of the present invention, and the patent scope of the present invention is not limited by this, so any equivalent changes in applying the content of the present invention are included in the scope of the present invention in the same way. Bright.

S10-S16‧‧‧ Writing procedure

Claims (10)

A method for dynamically aligning data of a flash memory, applied to a flash storage device having a microcontroller and a flash memory, including the following steps: a) controlling the microcontroller to continuously detect the flash storage device A usage state of b; b) receiving a data write command, where the data write command includes a logical start address; c) obtaining a cumulative offset when the usage state matches a required alignment state, and according to the The logical start address and a configuration unit capacity of the flash memory update the cumulative offset to obtain an updated cumulative offset; d) the logical start address corresponds to the updated cumulative offset Record in a lookup table; e) add the logical start address to the updated cumulative offset to obtain a physical start address; f) after the step c), the use state does not meet the need In the aligned state, add the logical start address to the cumulative offset to obtain the physical start address; and g) Write the corresponding data from the physical start address of the flash memory The data is written to the flash memory. The method for dynamically aligning data of a flash memory according to claim 1, wherein the usage state is a number of writes or a duration during which the microcontroller has not updated the accumulated offset. The method for dynamically aligning data of a flash memory as described in claim 2, wherein the step c is to update the accumulation when the write count is not less than a preset write count or the duration is not less than a preset duration Offset. The method for dynamically aligning data of a flash memory according to claim 1, wherein the step c further includes the following steps: c1) calculating a single offset, wherein the logical start address, the accumulated offset obtained The sum of the displacement and the single offset is a multiple of the unit capacity of the configuration; and c2) The single offset is added to the acquired cumulative offset to obtain the updated cumulative offset. The method for dynamically aligning data of a flash memory according to claim 4, wherein the step c1 is to calculate a remainder after dividing the sum of the logical start address and the obtained cumulative offset by the configuration unit capacity And calculate a difference between the configuration unit capacity and the remainder to obtain the single offset. The method for dynamically aligning data of a flash memory according to claim 1, further comprising the following steps: h1) receiving a data read command, wherein the data read command includes the logical start address and a data length; h2) Query the lookup table to obtain the updated cumulative offset corresponding to the logical start address; h3) Add the updated logical cumulative address to the logical start address to obtain the physical start address ; And h4) According to the data length, the data corresponding to the data read instruction is continuously read from the physical start address of the flash memory. The method for dynamically aligning data of a flash memory according to claim 1, wherein the step g) is to first write the data into a buffer memory of the flash storage device, and then write the data after the arrangement into The buffer memory is directly copied to the flash memory and written into the flash memory from the physical start address. A method for dynamically aligning data of a flash memory, applied to a flash storage device having a microcontroller and a flash memory, including the following steps: a) controlling the microcontroller to receive a first data write command , Where the first data write instruction includes a first logical start address; b) calculate a first offset based on the first logical start address and a configuration unit capacity of the flash memory, wherein The sum of the first logical start address and the first offset is a multiple of the capacity of the configuration unit; c) add an initial cumulative offset to the first offset to obtain a first cumulative offset; d) record the first logical start address and the first cumulative offset in a corresponding Look-up table; e) adding the first logical start address to the first cumulative offset to obtain a first physical start address; f) the first physical start bit from the flash memory The address begins to write data corresponding to the first data write command to the flash memory; g) receives a second data write command, wherein the second data write command includes a second logical start address; h) Calculate a second offset based on the second logical start address and the configuration unit capacity, where the sum of the second logical start address and the second offset is a multiple of the configuration unit capacity; i) The second offset is added to the first cumulative offset to obtain a second cumulative offset; j) The second logical start address and the second cumulative offset are correspondingly recorded in The lookup table; k) adding the second logical start address to the second cumulative offset to obtain a second physical start address; and l) from the flash memory The second solid start address of the body will be the beginning of the second data write command to write data to the flash memory. The method for dynamically aligning data of a flash memory according to claim 8, wherein the step b is to calculate the sum of the first logical start address and the initial cumulative offset divided by the configuration unit capacity A remainder, and calculate a first difference between the configuration unit capacity and the first remainder to obtain the first offset; the step h is to calculate the second logical start address and the first cumulative offset The sum of is divided by a second remainder after the configuration unit capacity, and a second difference between the configuration unit capacity and the second remainder is calculated to obtain the second offset. The method for dynamically aligning data of a flash memory according to claim 8, further comprising the following steps: m1) Receive a first data read command, where the first data read command includes the first logical start address and a first data length; m2) query the lookup table to obtain the corresponding first logical start The first accumulated offset of the address; m3) the first logical start address is added to the first accumulated offset to obtain the first physical start address; m4) according to the first data length Continuously reading data corresponding to the first data reading instruction from the first physical start address of the flash memory; m5) receiving a second data reading instruction, wherein the second data reading instruction includes The second logical start address and a second data length; m6) query the lookup table to obtain the second cumulative offset corresponding to the second logical start address; m7) start the second logical start Add the second cumulative offset to obtain the second physical start address; and m8) continuously read from the second physical start address of the flash memory according to the second data length Data corresponding to the second data read instruction.