TWI608479B - Self-refresh control device and volatile semicondcutor memory device - Google Patents

Description

Self-refresh control device and volatile semiconductor memory device

The present invention relates to, for example, a self refresh control device for a volatile semiconductor memory device such as a dynamic access memory (hereinafter referred to as DRAM), and a volatilization using the self-refresh control circuit Sex semiconductor memory device.

Recently, personal electronic devices such as mobile phones are being popularized, and these electronic devices generally operate using a battery. The DRAM in the personal electronic device must maintain the data stored using the self-refresh by the battery. Therefore, it is necessary to provide an electronic machine capable of performing a self-refresh function with further reduced power consumption.

In general, in DRAM, a test that cannot be self-refreshed cannot be performed before repair is performed by redundant memory. The reason for this is that the refresh timer must be optimized by repairing the fuse circuit on the on-chip timer circuit. Thus, the only way to guarantee self-refresh is by testing with a pause test. [Prior Art Document] [Patent Literature]

[Patent Document 1] Japanese Patent Application Publication No. 2005/0068829 [Patent Document 2] Japanese Patent Laid-Open No. Hei 5-274873 JP-A-2001-155482 [Patent Document 5] Japanese Patent Laid-Open No. Hei 11-339467 (Problem to be Solved by the Invention)

1 is a flow chart showing a flow of processing of a wafer test in a conventional example. In Fig. 1, the wafer test includes a low temperature test (S1), a high temperature test (S2), a repair process by a redundant memory (S3), and a high temperature test (S4).

In the self-refresh, in the high-temperature test of step S2, the default timer cycle is measured, and in the repair process of step S3, the expected timing is adjusted based on the measured timer period. The cycle (expected value) is used to fix the self-refresh timer. Further, after the high temperature test is performed in step S4, the fail chip is discarded. Moreover, in the pause test and other functions, after the low temperature test (S1) and the high temperature test (S2), the fail bit is repaired based on the redundant data. Further, after the high temperature test is performed in step S4, the failed wafer is discarded.

However, since the fuse circuit of the self-refresh timer is optimized without repair, self-refresh cannot be performed in the wafer test of the conventional example, and as shown in FIG. 1, the pause test is performed instead of the self-refresh.

2 is a flow chart when the self-refresh timer is optimized in the wafer test of FIG. As shown in FIG. 2, the preset self-refresh timer period is measured in the high temperature test (S2), and the self-refresh timer period is measured based on the measured self-refresh timer period to calculate the expected timer period (expected value). The fuse repair information is subjected to the repair processing of the fuse in step S3. Further, in step S4, the high temperature test is performed, and after the timer period is optimized, the self refresh can be tested. In FIG. 2, the preset timer period is set to be faster than the expected value of the timer period, and the preset timer period of each semiconductor wafer is deviated, and the preset timer period cannot be used in the self-refresh test.

FIG. 3 is a timing chart showing a self-refresh operation after the self-refresh timer is repaired in the conventional example. In FIG. 3, based on the clock CK, /CK clock enable signal (CKE), the optimized self-refresh timer output indication signal SELFR and self-refresh request signal SELFA are generated as internal signals to control Self-refresh. At the beginning of the self-refresh period, the self-refresh timer (t11) is started, and at the end of the self-refresh period, the self-refresh timer (t15) is stopped. During the self-refresh period, corresponding to each optimized self-refresh timer output indication signal SELFR, trigger starts self-refresh (t21, t22, t23), self-refreshed X address (address) Increment in increments.

Fig. 4 is a timing chart for explaining a difference between a self-refresh and a pause test in the conventional example. In the self-refresh (SR) mode, multiple refreshes are activated during the self-refresh period, but no functional actions are performed under the pause test. In the self-refresh period, in order to reduce the power consumption at the time of self-refresh, a plurality of internal voltage generators are set to a standby mode. Since there is a different action noise and internal voltage supply state between the pause test and the self-refresh test, it is desirable to not only perform the pause test but also the self-refresh test.

Further, for example, Patent Documents 1 to 5 disclose that self-refresh is not performed before the wafer test is trimmed, or self-refresh is not performed in the wafer test.

An object of the present invention is to solve the above problems and to provide a self-refresh control device and a volatile semiconductor memory device using the self-refresh control device. The self-refresh control device is implemented before trimming of a wafer test compared to a conventional example. Self-refresh testing, which can significantly improve yield in wafer testing. [Means for solving the problem]

A self-refresh control device for a volatile semiconductor memory device according to a first aspect of the invention is for use in a volatile semiconductor memory device including a self-refresh control circuit for using a first control signal from a self-refresh timer Controlling self-refresh of the volatile semiconductor memory device, the self-refresh control device characterized by: a logic circuit that inputs an external self-refresh request signal to the self-refresh control circuit in the test mode.

In the self-refresh control device, the logic circuit inputs the external self-refresh request signal to the self-refresh control circuit in the test mode instead of the first control signal.

Further, the logic circuit inputs the external self-refresh request signal to the self-refresh control circuit in place of the first control signal, thereby invalidating the operation of the self-refresh timer.

Further, in the self-refresh control device, the self-refresh control circuit periodically performs self-refresh.

Further, the self-refresh control device further includes an instruction control and test mode setting circuit that generates a second control signal for controlling the self-refresh timer based on a predetermined external signal and outputs the second control signal to the self-refresh timer.

A volatile semiconductor memory device according to a second aspect of the invention is characterized by comprising the self-refresh control device. [Effects of the Invention]

Therefore, according to the present invention, the self-refresh test can be performed before the wafer test is trimmed, so that the yield in the wafer test can be greatly improved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same components are denoted by the same reference numerals.

FIG. 5 is a circuit diagram showing an example of a circuit configuration of a self-refresh control device for a DRAM according to an embodiment of the present invention. The DRAM has a plurality of word lines and a plurality of bit lines, and the volatile memory elements are respectively connected at intersections of the word lines and the bit lines. The plurality of volatile memory elements of the DRAM are periodically self-refreshed, but in the present embodiment, the self-refresh timer 12 on the wafer is not used from the setting of the test mode, and the redundant fuse is repaired. The external self-refresh request signal EXSELF is issued, for example, from an external circuit such as a memory tester, and the self-refresh is tested based on the external self-refresh request signal EXSELF.

In FIG. 5, the self-refresh control device of the present embodiment includes a command control and test mode setting circuit 10, a timer cycle adjusting fuse circuit 11, a self-refresh timer 12, an input buffer (buffer) 13, and a self-executing DRAM. The refresh self-refresh control circuit 14, the NAND gates 21 to 23, the NOR gate 24, and the inverter 25 are formed.

For the command control and test mode setting circuit 10, the input clock CK, the clock/CK, the clock enable signal CKE, the chip select signal /CS, the row address strobe signal /RAS , row address strobe signal /CAS, write enable signal / WE, bank address BA and address Add. The command control and test mode setting circuit 10 generates a self-refresh stop signal SELFS when the self-refresh timer is started, after the self-refresh timer is started, based on the input signal.

The self-refresh start signal SELFT and the self-refresh stop signal SELFS are input to the inverse gate 21, and the self-refresh stop signal SELFS is also input to the inverse gate 22 and the inverse gate 24. The output signal of the anti-gate 21 is input to the self-refresh timer 12 to control its action. The period of the self-refresh timer 12 is set to a predetermined preset value before the repair, and is set to the set value from the timer period adjustment fuse circuit 11 after the repair. The self-refresh timer 12 generates a self-refresh signal at the set period and outputs it to the inverse gate 22. The output signal of the opposite gate 22 is input to the inverse gate 23.

On the other hand, an external self-refresh request signal EXSELF from an external circuit such as a memory tester is output to the inverse gate 23 via the input buffer 13 via the inverse gate 24 and the inverter 25. The inverse gate 23 generates a self refresh request signal SELFA based on the input two signals and outputs it to the self refresh control circuit 14 to control the self refresh operation of the self refresh control circuit 14.

In the self-refresh control device configured as described above, after entering the test mode, the self-refresh timer 12 stops its operation by the self-refresh stop signal SELFS. In the test mode, the self-refresh is input from the external refresh request signal EXSELF to the self-refresh control circuit via the input buffer 13, the inverse gate 24, the inverter 25, and the inverse gate 23. 14, so you can test the self-refresh. At this time, the conventional self-refresh related signal (output signal from the self-refresh timer 12) is blocked by the gate 23 (logic circuit) from being input to the self-refresh control circuit 14. Thereby, the self-refresh timer 12 is not used, and its operation becomes invalid.

Fig. 6 is a timing chart showing an operation example of the self-refresh control device of Fig. 5; In Fig. 6, the following timings indicate the following. (1) t0: start of test mode, (2) t1: start of self-refresh, (3) t2, t4: input of external self-refresh request signal EXSELF, (4) t3, t5: start of self-refresh operation.

As is clear from FIG. 6, in the test mode, the self-refresh can test the self-refresh based on the external self-refresh request signal EXSELF.

Hereinafter, the operation and effect of the embodiment configured as described above will be described.

In the wafer test of the conventional example, the self-refresh cannot be tested under the self-refresh action condition until the self-refresh timer 12 is optimized. However, the use of the self-refresh control device of the present embodiment has the following effects. (1) The wafer test yield can be greatly improved. The self-refresh can be tested and the invalid bits generated by the self-refresh can be replaced with redundant cells. (2) The yield of the final test performed before the memory chip is shipped can be greatly improved. The self-refresh period can be easily changed from the external circuit by the external self-refresh request signal EXSELF. The timer value of the self-refresh timer 12 can be set such that the self-refresh timer 12 has a deviation of the self-refresh timer 12 and the hold time of the memory cell due to a deviation of the process. The margin to the (margin).

As described above, according to the present embodiment, an appropriate self-refresh period can be appropriately set in consideration of the yield of the final test and the wafer test. In the present embodiment, only the logic circuit of the gate element (reverse gate 23, reverse gate 24, and inverter 25) smaller than the conventional example, the input buffer 13 and its input pad are added. These parts hardly affect the chip size, and although an additional wafer test time of, for example, about 200 milliseconds is required, it is considered that the self-refresh in the test mode should be tested to ensure the self-refresh function.

The present invention differs from Patent Document 1 to Patent Document 5. (1) Patent Document 1 Patent Document 1 sets an expected timer period for a self-refresh timer in a trimming procedure of a fuse. Based on the results of the final test, an electrical fuse circuit is used to set the self-refresh cycle again. Therefore, the invention of Patent Document 1 is not in the wafer test, and self-refresh is self-tested before the trimming timer.

(2) Patent Document 2 In Patent Document 2, the hold time for self-refresh is compensated by performing a pause test. The fuse of the self-refresh timer is set based on the result of the pause test. Therefore, the invention of Patent Document 2 does not test self-refresh in wafer testing.

(3) Patent Document 3 In Patent Document 3, a self-refresh timer is set from the system side. This means that the self-refresh timer is set after the assembly of the semiconductor memory device. Here, the self-refresh timer has a mode register that uses the test mode and is set at the address terminal. Therefore, the patent of Patent Document 3 does not test self-refresh, and does not set a self-refresh timer in the wafer test.

(4) Patent Document 4 In Patent Document 4, in the fuse trimming process, the self-refresh timer is set to an expected timer period. In the final test, an electrical fuse circuit was used in test mode to set the self-refresh period again. This cannot take advantage of the wafer shipping business. Therefore, the invention of Patent Document 4 does not test self-refresh in wafer testing.

(5) Patent Document 5 The circuit of Patent Document 5 has a circuit for outputting an internal self-refresh cycle to an external pad, and a memory tester of the wafer tester measures a self-refresh cycle. When the measured value is faster or slower than the expected value, the trimming fuse of the self-refreshing timer is cut. In the invention of Patent Document 5, self-refresh is not tested in the wafer test.

As described above, the embodiment according to the present invention is unique in the following points. (1) In order to improve the yield of the wafer test, the self-refresh test can be performed without using an unoptimized self-refresh timer. (2) In order to improve the yield of the final test, the self-refresh timer period using the test mode can be changed in consideration of the yield of the final test and the wafer test. [Industrial availability]

As described in detail above, according to the present invention, a self-refresh control device and a volatile semiconductor memory device using the self-refresh control device can be provided, the self-refresh control device being trimmed in a wafer test compared to a conventional example The self-refresh test was performed before, so the yield in the wafer test can be greatly improved.

10: command control and test mode setting circuit 11: timer cycle adjustment fuse circuit 12: self-refresh timer 13: input buffer 14: self-refresh control circuit 21, 22, 23: reverse gate 24: reverse or gate 25 : Inverter Add: Address BA: Memory Address CK, /CK: Clock CKE: Clock Enable Signal EXSELF: External Self-Refresh Request Signal

S1~S4‧‧‧ steps

SELFA‧‧‧ self-refresh request signal

SELFS‧‧‧ self-refresh stop signal

SELFT‧‧‧ self-refresh start signal

SELFR‧‧‧Self-refresh timer output indication signal

T0~t5, t11~t15, t21~t23‧‧‧

/CAS‧‧‧ line address strobe signal

/CS‧‧‧Wafer selection signal

/RAS‧‧‧Row address strobe signal

/WE‧‧‧Write enable signal

1 is a flow chart showing a flow of processing of a wafer test in a conventional example. 2 is a flow chart when the self-refresh timer is optimized in the wafer test of FIG. FIG. 3 is a sequence diagram showing a self-refresh operation after repairing the self-refresh timer in the conventional example. Fig. 4 is a timing chart for explaining a difference between a self-refresh and a pause test in the conventional example. FIG. 5 is a circuit diagram showing an example of a circuit configuration of a self-refresh control device for a DRAM according to an embodiment of the present invention. Fig. 6 is a timing chart showing an operation example of the self-refresh control device of Fig. 5;

10: command control and test mode setting circuit 11: timer cycle adjustment fuse circuit 12: self-refresh timer 13: input buffer 14: self-refresh control circuit 21, 22, 23: reverse gate 24: reverse or gate 25 : Inverter Add: Address BA: Memory address CK, /CK: Clock CKE: Clock enable signal EXSELF: External self-refresh request signal SELFA: Self-refresh request signal SELFS: Self-refresh stop signal SELFT: Self Refresh start signal /CAS: row address strobe signal /CS: chip select signal /RAS: column address strobe signal /WE: write enable signal

Claims (5)

A self-refresh control device for a volatile semiconductor memory device having a self-refresh control circuit for controlling self-control of the volatile semiconductor memory device based on a first control signal from a self-refresh timer Refreshing, the self-refresh control device is characterized by: a logic circuit that inputs an external self-refresh request signal to the self-refresh control circuit in a test mode; and an instruction control and test mode setting circuit based on the specified external signal A second control signal for controlling the self-refresh timer is generated and output to the self-refresh timer. The self-refresh control device according to claim 1, wherein the logic circuit inputs the external self-refresh request signal to the self-refresh control in the test mode instead of the first control signal Circuit. The self-refresh control device according to claim 2, wherein the logic circuit inputs the external self-refresh request signal to the self-refresh control circuit instead of the first control signal, thereby The action of the self-refresh timer is invalid. The self-refresh control device according to any one of claims 1 to 3, wherein the self-refresh control circuit periodically performs the self-refresh. A volatile semiconductor memory device, comprising the self-refresh control device according to any one of claims 1 to 4.