TWI604582B - Solder bump arrangements for large area analog circuitry - Google Patents

Description

Solder bump configuration for large area analog circuitry

The present disclosure relates to integrated circuits (ICs) and, more particularly, to solder bump arrangements for use with large area analog circuitry of integrated circuits.

Portions of integrated circuits (ICs) that include analog circuits are often considered highly sensitive. These areas of the integrated circuit may be affected by electrical, thermal, and mechanical gradients. The design of high-performance analog circuits relies on the efficient processing of these gradients, especially for analog circuits that occupy large areas in integrated circuits.

For example, consider a current source used in a digital to analog converter (DAC). This current source can occupy a large area of the integrated circuit. For example, a "current steering" type of digital to analog converter typically includes a current source that occupies a large area and a plurality of current steering switches that route current to a selected output. , depending on the digit code entered or provided. Typically, the current source is made up of an array of unit cells. The size of the current source can be on the order of square millimeters. The high performance digital to analog converter must cancel the electrical, thermal and mechanical gradients that occur in the integrated circuit, otherwise the linearity of the digital to analog converter will degrade.

Wire bond packages are often used for integrated circuits with most analog circuits Package. In wire bond packages, bond pads are distributed around the integrated circuit to avoid bonding pads placed over sensitive analog circuits. However, as flip chip technology becomes more and more common, reliable mechanical attachment of the die to another structure, such as a package substrate or interposer, requires a minimum density of solder bumps. Modern integrated circuits are implemented using flip chip technology and avoid the use of solder bumps on sensitive analog circuits to avoid performance degradation of analog circuits. However, avoiding the formation of bumps over most of this integrated circuit may violate the minimum density design rules for integrated circuit fabrication and may cause problems with the structural integrity of the resulting integrated circuit.

In one aspect, an integrated circuit (IC) includes an analog region of a die in an integrated circuit. The analog area includes an analog circuit. The integrated circuit further includes a plurality of solder bumps implemented on a surface of the die. The plurality of solder bumps are in an area that is vertically aligned with the analog region of the die.

In another aspect, a method for fabricating an integrated circuit is described. The method of fabrication includes performing an analog region within a die of the integrated circuit. The analog area includes an analog circuit. The method of fabrication includes positioning a plurality of solder bumps on a surface of the die. The area of the plurality of solder bumps on the surface of the die is vertically aligned with the analog region of the die.

100‧‧‧ integrated circuit

105‧‧‧Intermediary

110‧‧‧ grain

115‧‧‧ grain

120‧‧‧ grain

125‧‧‧Package substrate

130‧‧‧ analogy area

205‧‧‧ solder bumps

210‧‧‧ Conductive layer

215‧‧‧ wire

220‧‧‧Perforation

225‧‧‧ solder bumps

235‧‧‧through hole

505‧‧‧p type substrate part

510‧‧‧n type area or well

515‧‧‧metal layer

520‧‧‧metal layer

530‧‧‧metal layer

535‧‧‧Insulation materials

540‧‧‧ gate

545‧‧‧ gate

550‧‧‧ gate

555‧‧‧through hole

1200‧‧‧ integrated circuit

1205‧‧‧Grade mounting structure

1210‧‧‧ grain

1215‧‧‧ grain

1220‧‧‧ grain

1225‧‧‧ solder bumps

1230‧‧‧ analogy area

1300‧‧‧ method

1305‧‧‧

1310‧‧‧ square

1315‧‧‧ square

1 is a block diagram showing a top view of an exemplary multi-die integrated circuit (IC).

Figure 2 is a cross-sectional side view of the integrated circuit of Figure 1.

Figure 3-1, Figure 3-2, Figure 3-3, and Figure 3-4 are block diagrams, which are illustrated in Figure 1. And the layout of the analogous area of the integrated circuit in Fig. 2.

4 is a bottom plan view of a portion of the area of FIG. 3.

Figure 5 is a cross-sectional side view of a portion of a die of the integrated circuit of Figures 1 and 2.

Figure 6 is an exemplary solder bump configuration.

Figure 7 is another exemplary solder bump configuration.

Figure 8 is another exemplary solder bump configuration.

Figure 9 is another exemplary solder bump configuration.

Figure 10 is another exemplary solder bump configuration.

Figure 11 is another exemplary solder bump configuration.

Figure 12 is a cross-sectional side view of another integrated circuit.

FIG. 13 is a flow chart illustrating an exemplary method of fabricating an integrated circuit.

While the present disclosure has been summarized by the scope of the appended claims, it is believed that The processes, machines, fabrications, and any variations provided in the present disclosure are provided for illustrative purposes. Any specific structural and functional details are not to be construed as limiting, but merely as a basis for the scope of the patent application, and as a representative basis, to teach the person skilled in the art to use it in various ways. In the structure. Further, the terms and phrases used in the present disclosure are not intended to be limiting, but the description of the described features are provided.

The present disclosure relates to integrated circuit (IC), and more particularly to solder bump configuration for large area analog circuitry in integrated circuits. Typically, integrated circuits The analog circuit is sensitive to a variety of factors including, but not limited to, electrical, thermal, and mechanical gradients within the integrated circuit. Solder bumps are widely used in flip chip circuit designs to bond crystal grains together. It is further known that solder bumps induce a mechanical gradient in the form of varying stresses for each of the solder bumps and adjacent grains. The stress induced by the solder bumps can adversely affect the devices implemented within the die and thus affect the performance of any circuitry that relies on or utilizes these devices.

Thus, conventional design techniques avoid placing solder bumps in vertical alignment with large areas of analog circuits in flip chip circuit designs. However, the area occupied by the analog circuit of the integrated circuit may be so large that avoiding placing the solder bumps perpendicular to the area violates the design rules for specifying minimum solder bump density requirements. Violations of this design rule can also adversely affect the performance and structural integrity of the integrated circuit. For example, without proper density of solder bumps, one or more of the grains in the integrated circuit may be bowed.

In accordance with the configuration of the present invention described in this disclosure, a solder bump configuration that can be implemented in vertical alignment with a region of an integrated circuit including an analog circuit is disclosed. By using the solder bump configuration disclosed in this specification, a flip chip circuit fabrication technique can be used, although the integrated circuit has one or more dies, and the integrated circuit includes a large area analog circuit. Because the solder bumps can be implemented over the entire surface area of the die while being vertically aligned with the area of the analog circuit, the design rules associated with solder bump density are not violated.

In some cases, implementing the solder bump configuration to be vertically aligned with the analog region within the die does not degrade the performance of the analog circuit within the analog region. In other cases, the solder bump configuration is implemented to be vertically aligned with the analog region within the die to improve the analog power in the analog region The effectiveness of the road. More specific aspects of the solder bump configuration will be described below with reference to the accompanying drawings.

The elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to the other elements for the purpose of clarity. Further, it should be appropriately considered that the component symbols are repeated in the various figures to indicate corresponding, similar or similar features.

1 is a block diagram showing a top view of an exemplary multi-die integrated circuit (IC) 100. A multi-die integrated circuit is an integrated circuit that includes two or more dies in a single package. The integrated circuit 100 is an example of a "stacked chip integrated circuit" formed by stacking a plurality of crystal grains. As shown, the integrated circuit 100 includes an interposer 105, a die 110, a die 115, a die 120, and a package substrate 125. Each of the die 110, the die 115, and the die 120 has a bottom surface that is attached to the upper surface of the interposer 105. In one aspect, the die 110, the die 115, and the die 120 are attached to the interposer 105 using flip chip technology. The bottom surface of the interposer 105 is attached to the top surface of the package substrate 125.

The interposer 105 is a crystal grain having a flat surface on which the crystal grains 110, the crystal grains 115, and the crystal grains 120 are horizontally stacked. As shown, the die 110, the die 115, and the die 120 are located side by side on the flat surface of the interposer 105, respectively. Although the interposer 105 is shown as including three dies in FIG. 1, it should be understood that the integrated circuit 100 is shown for illustrative purposes only. The multi-die integrated circuit may include less than three dies attached to the interposer or more than three dies attached to the interposer.

The interposer 105 is a die attach structure, such as a type of crystal that provides a common mounting surface and electrical coupling point for each of the die 110, the die 115, and the die 120. Granular mounting structure. Fabrication of the interposer 105 can include one or more processing steps that allow one or more conductive layers to be deposited for patterning to form a wire. These conductive layers may be formed of aluminum, gold, copper, nickel, various tellurides, and/or the like. The interposer 105 can be fabricated using one or more additional processing steps that allow deposition of one or more dielectric or insulating layers, such as, for example, hafnium oxide.

The interposer 105 can also include vias, as well as through vias (TVs). The vias may be through silicon vias (TSVs), through glass vias (TGVs), or other perforated structures depending on the particular material used to implement the interposer 105 and its substrate. When the interposer 105 is implemented as a passive die, the interposer 105 may have only various types of solder bumps, vias, wires, vias, and under bump metallization (UBM). When implemented in active die, the interposer 105 can include additional processing layers to form one or more active devices associated with electrical devices, such as transistors, diodes, etc., including PN junctions.

Each of the die 110, the die 115, and the die 120 may be implemented as a passive die or active die including one or more active devices. For example, one or more of the die 110, the die 115, and the die 120 may be a memory die, a processor (central processing unit) die configured to execute a code, or have a programmable circuit Grain, dedicated integrated circuit dies, mixed signal dies, or the like. In one aspect, each of die 110, die 115, and die 120 can be the same or uniform. In another aspect, the die 110 can be implemented as one type of die, while the die 115 is implemented as another different type of die, and the die 120 is implemented as another different type of crystal grain. For example, the integrated circuit 100 can include a processor die, a programmable integrated circuit, and a memory coupled to the interposer 105. Body grain. In another example, integrated circuit 100 can be formed with two memories and a processor attached to interposer 105. The examples provided in the specification are for illustrative purposes only and are not intended to be limiting.

As used herein, "programmable die" refers to a die that includes a programmable circuit and is therefore programmable to implement a particular logic function. A specific example of a programmable die is a field programmable gate array (FPGA) die. FPGA dies are typically included in a programmable block array. These programmable blocks may include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory (BRAM), multipliers, digital signal processing blocks (DSPs). , processor, clock manager, delay locked loop (DLL), and more.

Each of the programmable blocks typically includes both a programmable interconnect circuit and a programmable logic circuit. Programmable interconnect circuits typically include a large number of interconnects of varying length interconnected by Programmable Interconnect Points ("PIP"). The programmable logic circuit implements user-designed logic using, for example, programmable elements such as function generators, registers, arithmetic logic, and the like.

The programmable interconnect circuit and the programmable logic circuit are usually programmed by loading a stream of configuration configuration data into an internal configuration setting memory unit, the configuration setting memory unit defining the How the programmable components are configured. The configuration settings can be read from the memory (eg, from an external PROM) or written to the FPGA by an external device. The collective state of the individual memory cells then determines the functionality of the FPGA.

Another specific example of a programmable die is a complex and programmable logic package. Set or CPLD. A CPLD contains two or more "function blocks" that are connected together and connected to input/output (I/O) resources by interconnecting switch matrices. Each functional block of the CPLD includes an AND/OR structure similar to that used in both a programmable logic array (PLA) and a programmable array logic (PAL) device. In CPLDs, configuration settings are typically stored in non-volatile memory on the wafer. In some CPLDs, the configuration settings data is stored in non-volatile memory on the wafer and then downloaded to volatile memory as part of the initial configuration (stylized) sequence.

For all of these programmable dies, the function of the die is controlled by the data bits provided to the die for its purpose. The data bits can be stored in volatile memory (eg, as static memory cells in FPGAs and certain CPLDs), in non-volatile memory (eg, as in flash memory in some CPLDs) Body, or in any other type of memory unit.

Other exemplary stylized dies may be implemented in other ways, such as by fuse or antifuse techniques. The term "programmable dies" includes, but is not limited to, these types of dies, and further covers only partially programmable dies. For example, the programmable dies include a combination of hard-coded transistor logic and a programmable switch structure that can be programmatically interconnected to the hard-coded transistor logic. It should be appreciated that the programmable die may include one or more portions of the programmable circuit, as well as other non-programmable circuits (such as analog circuits) or other fixed circuits (such as hardwired processing). One or more parts of a device or the like.

As shown, the die 110 includes an analog region 130. The analog region 130 includes an analog circuit. The analog circuit can be implemented in the analog region 130, and the analog circuit example can These include, but are not limited to, switched capacitor filters, switched capacitor analog to digital converters (ADCs), current sources, for example, for digital to analog converters (DACs), or the like. In any event, analog region 130 is shown for illustrative purposes. Those skilled in the art will appreciate that the analog region 130 is implemented within the die 110 and that the analog region 130 is not visible in the actual schematic of the integrated circuit 100 from the top view shown in FIG.

2 is a cross-sectional side view of the integrated circuit 100 of FIG. 1. More specifically, FIG. 2 illustrates the integrated circuit 100 taken along the cutting line 2-2 of FIG. Each of the die 110 , the die 115 , and the die 120 are electrically coupled and mechanically coupled to the first planar surface of the interposer 105 via solder bumps 205 . In one example, the solder bumps 205 are implemented as microbumps.

As shown, one or more solder bumps 205 are implemented to be vertically aligned with the analog region 130 of the die 110. When the solder bumps are within the area on the surface of the die 110 that is directly below the analog region 130, such as the bottom surface, the solder bumps 205 will be vertically aligned with the analog region 130. The area on the bottom surface of the die 110 is vertically aligned with the analog region 130, and this area is a projection of the outer periphery of the analog region 130 projected onto the bottom surface of the die 110. Thus, any solder bumps 205 located within the area defined by the projected perimeter of the analog region 130 are said to be vertically aligned with the analog region 130.

Interposer 105 includes one or more conductive layers 210. The conductive layer 210 is illustrated in the interposer 105 as a dashed line. Conductive layer 210 is implemented using any of a variety of metal layers as previously described. The conductive layer 210 is processed to form a patterned metal layer, while the wires 215 of the interposer 105 are implemented. The wires implemented in the interposer 105 are coupled to at least two different dies, such as die 110 and die 115, die 115 and die 120, or die 110 and die 120, and the wire is said to be It is an inter-die wire.

For purposes of illustration, Figure 2 illustrates several conductors 215 that are considered to be inter-die conductors. Wire 215 passes an inter-die signal between die 110, die 115, and/or die 120. For example, each of the wires 215 may couple two different solder bumps 205 below the die 110, the die 115, and/or between different dies of the die 120, thereby allowing the die 110, die 115 The intergranular signals between, and/or between the dies 120 are exchanged. The wire 215 can be a data wire or a power supply wire, such as ground (Vss) and/or a different or higher voltage potential (Vcc). One or more solder bumps 205, including solder bumps that are vertically aligned with the analog region 130, may be coupled to signal wires and/or power supply wires. Further, one or more solder bumps, including solder bumps that are vertically aligned with the analog region 130, may be electrically floating and provide only a mechanical connection between the die and the die mounting structure.

Different ones of the conductive layers 210 can be coupled together using the perforations 220. In general, the vias 220 are portions of a conductive material, such as metal, used to create a vertical power transfer path. In this regard, the vertical portion of the wire 215 that contacts the solder bump 205 will be implemented as a via 220. The use of multiple conductive layers within the interposer 105 to implement the interconnect allows a greater number of signals to be routed and more complex routing of signals to be implemented within the interposer 105.

Solder bumps 225 can be used to mechanically couple and/or electrically couple the bottom planar surface of interposer 105 to package substrate 125. The package substrate 125 is another type of die mounting structure. In one aspect, solder bumps 225 can be implemented to control controlled collapse chip connection balls. The package substrate 125 includes a conductive path (not shown) that couples different solder bumps 225 to one or more nodes below the package substrate 125. Accordingly, one or more solder bumps 225 pass through circuitry or wires of the package substrate 125 to couple the circuitry within the interposer 105 to a node external to the integrated circuit 100.

The vias 235 are vias for forming electrical connections that extend vertically through a substantial portion, if not all, of the interposer 105. Vias 235, like wires and vias, can be formed from any of a variety of different electrically conductive materials including, but not limited to, copper, aluminum, gold, nickel, various tellurides, and/or the like. One or more vias 235 can be coupled to the signal conductors, Vss, and/or Vcc. As shown, each via 235 extends upwardly from the bottom surface of the interposer 105 to the conductive layer 210 of the interposer 105. Via 235 may be further coupled to solder bumps 205 by a combination of one or more conductive layers 210 and one or more vias 220.

3-1, 3-2, 3-3, and 3-4 are block diagrams illustrating an alternative layout of a portion of the integrated circuit 100 of Figs. 1 and 2. More specifically, FIG. 3-1, FIG. 3-2, FIG. 3-3, 3-4, and illustrates a further arrangement, together referred to as Q ^N layout for analog region 130 of die 110. For purposes of illustration, the analog region 130 is formed entirely of analog circuits. As previously mentioned, the analog region 130 can include a switched capacitor filter, a switched capacitor analog to digital converter, a digital to analog converter, a current source, one or more or all combinations of the above, a portion of which Wait. In one aspect, the various blocks depicted in Figures 3-1, 3-2, 3-3, and/or 3-4 may represent circuit components, such as, for example, capacitors in a capacitor array. Circuit elements, resistor circuit elements in a resistor array, unit current sources in a current source array, or the like. In this regard, the analog region 130 can represent a majority of the array circuit elements of the die 110 or regions of analog circuits.

For purposes of discussion and not limitation, consider the case of analog region 130 depicted in Figures 3-1, 3-2, 3-3, and 3-4 below, which implements one from a plurality of smaller current sources. Battery. For example, the current source of analog region 130 can be implemented as part of a digital to analog converter. For example, the current source of the analog region 130 can be implemented as a temperature A current source is calculated in which the current contributions from the various units are summed and routed to the appropriate switches.

Figure 3-1 illustrates an example of four quadrant (Q ² ) layouts. In the Q ² layout, the switching sequence of current sources can be randomized using several different techniques. In one aspect, individual current sources are implemented in a common centroid configuration, but these open relationships control different cells, and these open relationships are either random or organized for random operation. In another aspect, the location of the cells is random, but the switches are ordered or switched in a predetermined order. In either case, randomization helps to reduce the overall nonlinearity (INL) of the transfer function of the digital to analog converter.

Figure 3-1 shows an example in which the analog region 130 is implemented using a common centroid method. For purposes of illustration, the x-y coordinate system is overlapped with the analog region 130. As shown, each quadrant includes block A, block B, block C, and block D. Further, each of the block A, the block B, the block C, and the block D includes 16 units marked with 1 to 16. Although the unit is illustrated only for block A, it should be noted that each of block A, block B, block C, and block D has 16 units.

In a common centroid configuration, the analog circuit shown is symmetric to both the x-axis and the y-axis. Block A, block B, block C, and block D above the x-axis are mirrored below the x-axis. Similarly, block A, block B, block C, and block D on the left side of the y-axis are mirrored to the right of the y-axis. The same action is performed on the cells in each block.

A given current source may include multiple cells from different blocks of analog region 130. For example, a given current source may include cells A1 from each quadrant of region 130. The current source is split in a symmetrical manner with respect to both the x-axis and the y-axis. Other current sources can be implemented in a similar manner, that is, symmetric x-axis and y-axis, although different numbers of cells may be required. Control the current source in the case of the common centroid configuration as shown in Figure 3. The switch will be randomized instead of following the current source's position.

The purpose of providing Figure 3-1 is for illustration. Therefore, the examples described with reference to FIG. 3-1 are not intended to be limiting. Other layouts can be used to implement analog circuits within the analog region 130, which also benefits from the solder bump configuration described in this disclosure. This layout may or may not use a common centroid method. Further examples are depicted in Figures 3-2, 3-3, and 3-4.

The x-axis and the y-axis are not shown in each of Figures 3-2, 3-3, and 3-4. However, for the purpose of reference, the center or origin of each structure will be displayed. 3-2 is a block diagram illustrating an exemplary Q ¹ rotational walkout layout that may be used to implement analog circuits within the analog region 130. As shown, the layout shown in Figure 3-2 includes block 1, block 2, block 3, and block 4.

3-3 is a block diagram illustrating an exemplary Q ² rotational walkout layout that can be used to implement an analog circuit within the analog region 130. Figure 3-3 illustrates the details of increasing the number of layers, with the uppermost layer shown as containing block A, block B, block C, and block D. Each of block A, block B, block C, and block D is broken down into further details, and each of which includes block 1, block 2, block 3, and block 4, or unit 1, unit 2, unit 3. And unit 4.

Figure 3-4 is a block diagram, which illustrates the exemplary layout move rotation Q ^3, which may be used to implement the analog circuits within the analog region 130. Figures 3-4 illustrate the details of increasing the number of layers, with the uppermost layer shown as containing block I, block II, block III, and block IV. Each of Block I, Block II, Block III, and Block IV is exploded to show further details, and each of which includes Block A, Block B, Block C, and Block D. Each of block A, block B, block C, and block D is further broken down to illustrate additional details, and each of which includes block 1, block 2, block 3, and block 4, or unit 1, unit 2 , unit 3, and unit 4. The examples are provided for illustration and breadth and are therefore not intended to limit the scope of the inventive arrangements described herein.

4 is a bottom plan view of a portion of region 130 of FIG. 3. More specifically, FIG. 4 illustrates the transistor structure of the multi-finger, in which the square labeled "G" represents the gate, the source level is obscured by cross hatching, and the pupil level is shaded by vertical hatching. Metal traces are also exemplified. The manner in which the solder bumps 205 are placed is illustrated relative to the analog circuit 130 in the analog region. The solder bumps 205 can be implemented as microbumps that are shown in a translucent manner to illustrate how the solder bumps 205 are actually implemented on the bottom surface of the die 110, with the analog region 130 being implemented in the die 110 . FIG. 4 illustrates the solder bumps 205 being vertically aligned with the analog region 130.

FIG. 5 is a cross-sectional side view of a partial region 130 within the die 110. FIG. 5 is a simplified diagram illustrating the relative positions of solder bumps 205 on the analog circuit of die 110. In the example shown in Figure 5, the analog circuit is part of the current source. The solder bumps 205 may be implemented as microbumps formed on the surface of the die 110 (eg, the bottom surface). The view presented in FIG. 5 has been reversed for purposes of clarity and illustration, so that solder bumps 205 formed on the bottom surface of die 110 as shown in FIG. 2 are shown at the top of FIG.

As shown, portions of the illustrated die 110 include a p-type substrate portion 505 having various n-type regions or wells 510. The region between metal layer 515, gate 520, and gate 530 may be an insulating material 535, such as hafnium oxide. Gate 540, gate 545, and gate 550 can be implemented using polysilicon. One or more vias 555 can couple the portions of the transistor to metal layer 515, metal layer 520, and/or metal layer 530. It should be noted that FIG. 5 is a simplified diagram. Thus, portions of the die 110 illustrated in FIG. 5 may include one or more other layers not illustrated, such as: a UBM layer under the solder bumps, other layers over the insulating material 535, or the like. 205.

Although FIG. 5 presents an example of using an n-type transistor, it should be understood that a p-type transistor can also be used or included in the analog region 130. Moreover, the specific types of integrated circuit fabrication techniques and materials described with reference to FIG. 5 are for illustrative purposes and are not intended to be limiting.

Figure 6 is an exemplary solder bump configuration for use with an integrated circuit. For example, the solder bump configuration of FIG. 6 can be used in conjunction with the integrated circuit of FIGS. 1 and 2. More specifically, FIG. 6 illustrates a bottom view of a portion of the surface of the die 110 that is vertically aligned with the analog region 130. For purposes of illustration, an x-y coordinate system is shown on the graph to illustrate the distribution or configuration of solder bumps 205. The array of solder bumps 205 shown in FIG. 6 includes a plurality of columns (eg, row 1, row 2, row 3, and row 4), and a plurality of columns (eg, column 1, column 2, And column 3). As shown, the row of solder bumps 205 are perpendicular to the column of solder bumps 205.

The horizontal spacing refers to the continuity of the solder bumps 205 of the same column, or the distance between adjacent ones. The horizontal interval is also called "x-pitch". For example, adjacent solder bumps 205 of the three columns include solder bumps at coordinates (1, 3) and (2, 3). In one example, the horizontal spacing between adjacent solder bumps 205 can be specified in accordance with the design rules of the particular integrated circuit fabrication process used. The horizontal spacing may be the minimum distance allowed, the maximum distance allowed, or some distance allowed between the minimum distance and the maximum distance, in accordance with the design rules for specifying the density of the solder bumps 205.

Vertical spacing refers to the distance between successive, or adjacent, solder bumps 205 in the same row. Vertical spacing is also referred to as "y-spacing." For example, adjacent solder bumps include solder bumps at row 1 at coordinates (1, 2) and (1, 3). In one example, in The vertical spacing between adjacent solder bumps 205 can be specified in accordance with the design rules of the particular integrated circuit fabrication process used. The vertical spacing may be the minimum distance allowed, the maximum distance allowed, or some distance allowed between the minimum distance and the maximum distance, in accordance with the design rules for specifying the density of the solder bumps 205.

In one aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to a power supply signal. The power supply signal can be Vss. In another example, the power supply signal can be Vcc. In another example, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to the data signals within the die 110 and/or the interposer 105. In another aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be mechanical solder bumps. As mechanical solder bumps, the solder bumps do not form an electrical connection between the die and/or die mounting structure, such as an open circuit, a floating node, or no connection to any other circuitry of the integrated circuit at all. Therefore, the mechanical solder bumps are only used to form a mechanical bond between the die and the die mounting structure for structural integrity.

Figure 6 illustrates a solder bump configuration in which solder bumps are placed in columns and columns are perpendicular to rows. Therefore, the x pitch and the y pitch remain fixed. Further, there is no offset in the column or in the row. However, other solder bump configurations can be implemented in which one or more offsets can be used. The offset of the y coordinate applied to the solder bump is referred to as "offset_Y".

In some cases, a uniform offset can be applied across a plurality of different solder bumps, both for the x-coordinate and/or the y-coordinate. For example, a uniform offset can be applied across all solder bumps in a row, all solder bumps in a column, or all solder bumps in both rows and columns. In this case, adjacent solder bumps in the same row or in the same column The x-spacing and y-spacing are kept constant. In other cases, regardless of the x-coordinate and/or y-coordinate of the solder bump, an offset to a plurality of different solder bumps may be applied in accordance with each solder bump. For example, the offset from one solder bump to another solder bump can vary and can be further varied in a non-linear manner. Depending on the case, the x-pitch and/or y-pitch may be different for each of the adjacent pairs of solder bumps in the applied offset column and/or row. Therefore, the x-pitch and/or y-pitch does not remain fixed. The offset applied to the solder bump configuration is described in further detail with reference to Figures 7-11.

Figure 7 is another exemplary solder bump configuration used in conjunction with an integrated circuit. The solder bump configuration of FIG. 7 can be used in conjunction with the integrated circuit of FIGS. 1 and 2. FIG. 7 illustrates a bottom view of a portion of a die 110 that is vertically aligned with the analog region 130. For purposes of illustration, an x-y coordinate system is shown on the graph to illustrate the distribution or configuration of solder bumps 205. The configuration of the solder bumps 205 shown in FIG. 7 can be used as an alternative to that described with reference to FIG.

As shown, each column is offset from the top along the x-axis by a predetermined amount called "offset_X". The offset_X is smaller than the horizontal interval between the solder bumps. After applying an offset to each column, the horizontal and vertical intervals can remain fixed. For example, the solder bumps of column 3 begin at coordinates (1, 3). The coordinates of the next solder bump of column 3 are (2, 3). The solder bumps of column 2 start at coordinates (1+offset_X, 2). The next solder bump coordinate of column 2 is (2+offset_X, 2). The solder bump of column 1 begins at coordinates (1+(2 * offset_X), 1). The next solder bump coordinate of column 1 is (2+(2 * offset_X), 1).

The x-pitch and y-pitch can be set according to the design rules of the particular integrated circuit technology used. In one aspect, the x-pitch and/or y-pitch can be set to the minimum allowed interval, the maximum allowed interval, or some interval between them. It should be noted that offset_X is less than Horizontal interval or x spacing. Further, the array of solder bumps 205 shown in FIG. 7 includes a plurality of columns (eg, column 1, column 2, and column 3) and a plurality of rows. The line is represented by line segment 1-1, line segment 2-1, line segment 3-1, and line segment 4-1. As shown, although the solder bumps 205 are still arranged in rows, the rows are not perpendicular to the columns due to the offset relationship of each individual column. In the example of Figure 7, offset_X is added to the x-coordinate of the affected solder bump. In another example, offset_X can be subtracted.

In one aspect, offset_X can be measured by the fingers of the transistor that implements the current source in analog region 130. Thus, offset_X can be a single finger, two fingers, or the like. The finger can be defined as the gate polysilicon area of the transistor, at least in terms of size. Thus, the fingers define the width (W) and length (L) of the area corresponding to the gate polysilicon. In one example, offset_X can be set to a value greater than W. When offset_X is greater than one or more fingers, it should be understood that the distance indicated by offset_X includes any necessary between adjacent transistors in the horizontal direction, depending on the design rules of the particular integrated circuit technology used. Area or interval.

In one aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to a power supply signal. The power supply signal can be Vss. In another example, the power supply signal can be Vcc. In another example, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to the data signals within the die 110 and/or the interposer 105. In another aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be mechanical solder bumps.

Figure 8 is another exemplary solder bump configuration for use with an integrated circuit. The solder bump configuration of FIG. 8 can be used in conjunction with the integrated circuit of FIGS. 1 and 2. Figure 8 illustrates A bottom view of a portion of the die 110 that is vertically aligned with the analog region 130. Again, for purposes of illustration, the x-y coordinate system is shown on the graph to illustrate the distribution or configuration of the solder bumps 205. The configuration of the solder bumps 205 shown in FIG. 8 can be used as an alternative to that described with reference to FIGS. 6 and 7.

Fig. 7 illustrates an example in which columns are shifted, and Fig. 8 illustrates an example in which rows are shifted. As shown, each row is offset from the leftmost side along the y-axis by a predetermined amount called "offset_Y". The offset_Y is smaller than the vertical interval between the solder bumps. The horizontal and vertical intervals can remain fixed after an offset is applied to each row. For example, the solder bump of row 1 begins at coordinates (1, 3). The coordinates of the other solder bumps of row 1 are (1, 2) and (1, 1). The solder bumps of row 2 begin at coordinates (2, 3-offset_Y). The coordinates of the other solder bumps of row 2 are (2, 2-offset_Y) and (2, 1-offset_Y). The solder bumps of row 3 begin at coordinates (3, 3-(2 * offset_Y)). The next solder bump coordinate of row 3 is (3,2-(2 *offset_Y)).

The x-pitch and y-pitch can be set according to the design rules of the particular integrated circuit technology used. In one aspect, the x-pitch and/or y-pitch can be set to the minimum allowed interval, the maximum allowed interval, or some interval between them. Furthermore, the array of solder bumps 205 shown in FIG. 8 includes a plurality of rows (eg, row 1, row 2, row 3, and row 4) and a plurality of columns. The column is represented by line segment 1-1, line segment 2-1, and line segment 3-1. As shown, although the solder bumps 205 are still arranged in rows, the rows are not perpendicular to the columns due to the offset relationship of each individual column. In the example of Figure 8, offset_Y is subtracted from the y-coordinate of the affected solder bump. In another example, offset_X can be added.

The offset_Y, like offset_X, can be measured by the fingers of the transistor that implements the current source in the analog region 130. The offset can be a single finger, two fingers Shape, or the like. In one example, offset_Y can be set to a value greater than L associated with the finger. However, it should be noted that offset_Y is still smaller than the vertical interval or the y-space. When offset_Y is greater than one or more fingers, it should be understood that depending on the design rules of the particular integrated circuit technology used, the distance indicated by offset_Y includes any necessary between adjacent transistors in the vertical direction. Area or interval.

In one aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to a power supply signal. The power supply signal can be Vss. In another example, the power supply signal can be Vcc. In another example, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to the data signals within the die 110 and/or the interposer 105. In another aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be mechanical solder bumps.

Figure 9 is another exemplary solder bump configuration used in conjunction with an integrated circuit. The solder bump configuration of FIG. 9 can be used in conjunction with the integrated circuit of FIGS. 1 and 2. FIG. 9 illustrates a bottom view of a portion of a die 110 that is vertically aligned with the analog region 130. Again, for purposes of illustration, the x-y coordinate system is shown on the graph to illustrate the distribution or configuration of the solder bumps 205. The configuration of the solder bumps 205 shown in FIG. 9 can be used as an alternative to that described with reference to FIGS. 6 to 8.

FIG. 9 illustrates an example in which both columns and rows are shifted. As shown, each column is offset from the top along the x-axis by offset_X. In addition, each row is offset from the leftmost side along the y-axis by offset_Y. It should be noted that offset_X may be less than the horizontal spacing between adjacent solder bumps in the same column, while offset_Y may be less than the vertical spacing between adjacent solder bumps in the same row.

The horizontal interval can remain fixed after an offset is applied to each column. same Ground, the vertical spacing can remain fixed after an offset is applied to each row. For example, row 1 includes solder bumps at coordinates (1, 3), (1+offset_X, 2), and (1+(2 * offset_X), 1). Row 2 includes solder bumps at coordinates (2, 3-offset_Y), (2+offset_X, 2-offset_Y), and (2+(2*offset_X), 1-offset_Y).

It should be noted that the x-pitch and y-pitch can be set according to the design rules of the particular integrated circuit technology used. In one aspect, the x-pitch and/or y-pitch can be set to the minimum allowed interval, the maximum allowed interval, or some interval between them.

Both offset_X and offset_Y can be measured by the fingers of the transistor that implements the current source in analog region 130. Thus, the offset can be a single finger, two fingers, or the like. In one example, offset_X can be set equal to offset_Y. In one example, offset_X can be set to not equal to offset_Y. In this case, offset_X can be set to be greater or smaller than offset_Y. Further, although the array of solder bumps 205 shown in FIG. 9 includes a plurality of rows and a plurality of columns, the columns and rows are not perpendicular to each other.

In one aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to a power supply signal. The power supply signal can be Vss. In another example, the power supply signal can be Vcc. In another example, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to the data signals within the die 110 and/or the interposer 105. In another aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be mechanical solder bumps. It should be noted that the offset of either offset_X or offset_Y can be added to or subtracted from the given coordinates. The application of the offset is not limited to the embodiments provided in this specification.

The examples illustrated in Figures 6 through 9 utilize solder bumps for x spacing A fixed interval between the Y and Y spacing. As discussed, the offset applied to each of the solder bumps can be varied, with a solder bump configuration in which the x-pitch and/or y-pitch does not remain fixed. The change in the applied offset can be non-linear.

Figure 10 is another exemplary solder bump configuration for use with an integrated circuit. The solder bump configuration of FIG. 10 can be used in conjunction with the integrated circuit of FIGS. 1 and 2. FIG. 10 illustrates a bottom view of a portion of a die 110 that is vertically aligned with the analog region 130. Again, for purposes of illustration, the x-y coordinate system is shown on the graph to illustrate the distribution or configuration of the solder bumps 205. The configuration of the solder bumps 205 shown in FIG. 10 can be used as an alternative to that described with reference to FIGS. 6 through 9.

Fig. 10 illustrates an example in which the offset_X of one solder bump to the next solder bump changes in the same column. In addition, offset_X changes in a non-linear manner. As shown, the solder bumps of column 2 have a fixed x pitch. The coordinates of the solder bumps of column 2 are (1, 2), (2, 2), (3, 2) and (4, 2). However, in column 1, the x spacing does not remain fixed. The first solder bump of column 1 has an offset of offset_X. The second solder bump of column 1 has an offset of 2*offset_X. The third solder bump of column 1 has an offset of 4*offset_X, and the like. The coordinates of the solder bumps of column 1 are (1+offset_X,1), (2+(2 * offset_X),1), (3+(4 * offset_X),1), and (4+(8 * offset_X) ),1). It should be noted that although the offset is added in this example, the offset can also be subtracted.

In one aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to a power supply signal. The power supply signal can be Vss. In another example, the power supply signal can be Vcc. In another example, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to the crystal The data signal in the particle 110 and/or the interposer 105. In another aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be mechanical solder bumps.

Figure 11 is another exemplary solder bump configuration for use with an integrated circuit. The solder bump configuration of FIG. 11 can be used in conjunction with the integrated circuit of FIGS. 1 and 2. FIG. 11 illustrates a portion of a bottom view of a die 110 that is vertically aligned with the analog region 130. Again, for purposes of illustration, the x-y coordinates are superimposed to illustrate the distribution or configuration of the solder bumps 205. The configuration of the solder bumps 205 illustrated in FIG. 11 can be used as an alternative to the solder bumps 205 described with respect to FIGS. 6-10.

Fig. 11 illustrates an example in which the offset_Y of one solder bump to the next solder bump changes in the same row. In addition, offset_Y will change in a non-linear manner. As shown, the solder bumps of row 1 have a fixed y-pitch. The coordinates of the solder bumps of column 1 are (1, 4), (1, 3), (1, 2) and (1, 1). However, in line 2, the y-pitch does not remain fixed. The first solder bump of row 2 has an offset of offset_Y. The second solder bump of row 2 has an offset of 2*offset_Y. The third solder bump of row 2 has an offset of 4*offset_Y, and the like. The coordinates of the solder bumps of row 2 are (2, 4-offset_Y), (2, 3-(2 * offset_Y)), and (2, 2-(4 * offset_Y)), respectively. Although the offset is subtracted in the example of Figure 11, the offset can also be used.

In one aspect, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to a power supply signal. The power supply signal can be Vss. In another example, the power supply signal can be Vcc. In another example, one or more, or all, of the solder bumps 205 that are vertically aligned with the analog region 130 can be coupled to the data signals within the die 110 and/or the interposer 105. In another aspect, the analogy region 130 One or more, or all, of the solder bumps 205 that are vertically aligned may be mechanical solder bumps.

Referring to the digital to analog converter case, the solder bump configuration described in relation to Figure 6 is applied to an analog circuit as compared to a digital to analog converter in which the solder bumps are not vertically aligned with the analog circuit. Improved overall nonlinearity can be provided. For example, as explained in relation to Figure 6, solder bumps are formed to be vertically aligned with analog circuits in a digital to analog converter to provide improvements from 4 LSB to 16 LSB on a 16-bit scale. . The current source of the digital to analog converter can be implemented with respect to Figure 3 and its description, for example, using a common centroid configuration, Figure 3-2, Figure 3-3, Figure 3-4, or other configuration. Applying the offsets as shown in Figures 7 through 12 to the solder bump configuration and using this solder bump on the analog circuit or portion thereof, will provide a digital to analog converter as described in relation to Figure 6 Greater improved overall nonlinearity.

FIG. 12 is a cross-sectional side view of the integrated circuit 1200. As shown, integrated circuit 1200 includes a plurality of dies 1210, 1215, 1220 mounted on die mounting structure 1205. In this example, the die attach structure 1205 is a package substrate. The die 1210, the die 1215, and the die 1220 are attached to the die attach structure 1205 through a plurality of solder bumps 1225. For example, solder bumps 1225 can be bumps of C4. In this example, die 1210 includes an analog region 1230 that is substantially as described with respect to analog region 130. One or more solder bumps 1225 can be vertically aligned with the analog region 1230. Any of a variety of solder bump configurations described in this specification can be used in solder bumps 1225 that are vertically aligned with analog regions 1230, for example, with respect to Figures 6-11. Figure 12 illustrates an example in which the techniques described in this disclosure can be applied to dies mounted on a package substrate where no interposer is used.

The inventive configuration described in the present disclosure can be improved when one or more dies When using most of the analog circuits, the performance of the multi-die integrated circuit formed by flip chip technology is utilized. A solder bump configuration can be formed over the entire surface of the die and vertically aligned with the analog circuitry implemented within the die. The described variety of solder bump configurations facilitates digital to analog converters, improving the performance of analog circuits from the standpoint of reducing INL.

In one aspect, the solder bump configurations illustrated in the present disclosure seek for staggered columns, rows, columns and rows, and/or individual solder bumps, so that the stresses caused by the devices in the analog circuit are dispersed throughout The components have been equally stressed with respect to the individual components. For example, the horizontal spacing (eg, x-spacing) of the solder bumps can be selected such that the total stress in each row of the fingers will average to the same value. The vertical spacing (e.g., y-pitch) of the solder bumps can be selected such that the position of the solder bumps translates to apply the same average stress to each column. The offsets applied in column to column, and/or row to row are used to avoid error accumulation effects.

In one example, the solder bump density, whether offset column and/or row, can be set to approximately 14%. However, this value is provided for illustrative purposes only. Solder bump density higher than 14% and solder bump density below 14% may result in improved operation of the analog circuit.

FIG. 13 is a flow chart illustrating an exemplary method 1300 of fabricating an integrated circuit. Any of the various solder bump configurations described in this disclosure can be used in fabricating integrated circuits. For purposes of illustration, and not limitation, FIG. 13 merely illustrates a simplified manufacturing process.

Method 1300 can begin at block 1305 where a die is created. Standard integrated circuit fabrication techniques well known in the art can be used to build the dies into a multilayer semiconductor structure. An analog region is implemented within the die as part of the creation of the die. The analog area includes an analog circuit. Various types of analog circuits, or any of the portions described in this disclosure, can be implemented. Although the die includes an analogous region, it should be understood that the die may include It is a type of circuit, such as a digital circuit.

In block 1310, the formation of solder bumps is performed. The solder bumps are positioned or implemented on the surface of the die. In one aspect, the area of the solder bump positioned on the surface of the die is perpendicular to the analog region located in the die. Solder bumps that are vertically aligned with the analog regions can be implemented with any of the solder bump configurations described in this disclosure. In addition, it should be understood that the solder bumps used in the area vertically aligned with the analog regions may be solder bump configurations or solder implemented on the surface of the die surface that is vertically aligned with the analog regions. The bump pattern is different.

At a block 1315, the die can be attached to the die attach structure. In one example, the die attach structure is a package substrate. In another aspect, the die attach structure is an interposer. In any case, the first surface of the die attach structure can be attached to the first surface of the die using a plurality of solder bumps.

The solder bump connections are configured or implemented as part of the attachment process of the formation of solder bumps and/or blocks 1315 of block 1310. In one aspect, one or more of the areas that are vertically aligned with the analog regions, or all of the solder bumps, can be maintained as mechanical solder bumps. In another aspect, one or more of the areas vertically aligned with the analog region, or all of the solder bumps are coupled to a power supply voltage. In another aspect, one or more of the areas that are vertically aligned with the analog region, or all of the solder bumps can be coupled to the data signal.

It will be appreciated that various combinations of the above connections can also be implemented. For example, one or more of the solder bumps described in the area may be mechanical solder bumps, while one or more other solder bumps described in the area are coupled to a power supply voltage. In area One or more of the solder bumps described herein may be mechanical solder bumps, while one or more other solder bumps described in the area are coupled to the data signal. One or more solder bumps described in the area may be coupled to a power supply voltage, while one or more other solder bumps described in the area are coupled to the data signal. In yet another example, one or more of the solder bumps described in the area may be mechanical solder bumps, and one or more other solder bumps described in the area may be coupled to the data signal. One or more other solder bumps described in the area may be coupled to the power supply voltage.

Depending on the implementation of the die attach structure, the inventive arrangements disclosed in this specification can be applied to a single die integrated circuit structure or a multi-die integrated circuit structure in which the die can be attached The package substrate is attached to the package substrate. In the case of a multi-die integrated circuit structure, two or more dies may be attached to the package substrate. In an alternative multi-die integrated circuit structure, two or more dies may be attached to the interposer, which is then attached to the package substrate. One or more or all of such multi-die integrated circuit structures may include analog regions having solder bump configurations as described in this disclosure.

For the purposes of illustration, specific terminology names are set forth in order to provide a thorough understanding of the various inventive concepts disclosed herein. However, the terms used in the specification are for the purpose of illustrating the features described, and are not intended to be limiting.

The terms "a" and "an" are used in the specification to mean one or more and not one. The term "plurality" as used in this specification is defined as two or more, not two. The term "another" as used in this specification is defined as at least a second or more. The term "coupled" as used in this specification is defined as a connection, whether it is a direct way without any intervening elements, or having one or more intervening elements interlinked, Unless otherwise stated. The two components can also be coupled in a mechanical, electrical or communication link via a communication channel, path, network or system.

The term "and/or" used in the specification means and includes any and all possible combinations of one or more of the associated listed items. It is to be understood that the phrase "comprises" or "comprises" and "includes", when used in this specification, is specifically intended to mean the existence of the recited features, integers, steps, operations, components and/or components. The presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof. It should also be understood that although the terms first, second, etc. may be used in the specification to describe various elements, these elements are not limited by these terms, as these terms are used only to distinguish one element from another.

In this specification, the same reference words are used to refer to terminals, signal lines, wires, and their corresponding signals. Accordingly, the terms "signal", "wire", "connection", "terminal" and "pin" in this specification can be used interchangeably at any time. For example, the power supply signal carries a power supply voltage or a power supply voltage potential. The term "power supply signal" can be used interchangeably with the terms "power supply voltage" or "power supply voltage potential". It should be understood that the terms "signal", "wire" or the like may represent one or more signals, for example, transmitting a single bit through a single wire or transmitting multiple parallel bits through a plurality of parallel wires. Further, each wire or signal may represent two-way communication between two or more elements to which all of the signals or wires are connected as in this case.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of the exemplified process, machine, manufacture, and/or system of one or more features described in this specification. In some alternative implementations, the functions noted in the block diagrams may be similar to those noted in the figures. The order occurs differently. For example, two consecutive blocks shown in the figures may be executed simultaneously, depending on the functionality involved.

The structure, materials, acts, and all equivalents of all components, steps, and functional elements in the scope of the claims are intended to include any structure, material, or .

The features disclosed in the present specification may be embodied in other forms without departing from the spirit or essential attributes. Accordingly, the scope of the following claims should be construed as the

130‧‧‧ analogy area

205‧‧‧ solder bumps

Claims (19)

An integrated circuit comprising: an analog region of a die of the integrated circuit, the analog region comprising an analog circuit; and a plurality of solder bumps implemented on a surface of the die, the plurality of solder a bump is in a region vertically aligned with the analog region of the die; wherein the plurality of solder bumps comprise: a first row of solder bumps having a fixed spacing; and a second row of solder bumps, Wherein the vertical spacing between adjacent solder bumps in the second row of solder bumps varies non-linearly as the vertical offset between successive pairs of solder bumps in the second row of solder bumps increases . The integrated circuit of claim 1, wherein the analog circuit comprises a plurality of current sources. The integrated circuit of claim 2, wherein the plurality of current sources are arranged in a common centroid layout. The integrated circuit of claim 1, wherein at least a portion of the analog circuit comprises a plurality of circuit elements arranged in a Q ^N layout. The integrated circuit of claim 1, wherein the plurality of solder bumps comprise: a first column of solder bumps; and a second column of solder bumps; wherein the second column of solder bumps is The first column of solder bumps are offset from a direction parallel to the second column of solder bumps. The integrated circuit of claim 5, wherein a horizontal interval between adjacent solder bumps in the second column of solder bumps is fixed. The integrated circuit of claim 5, wherein the horizontal spacing between adjacent solder bumps in the second column of solder bumps varies. The integrated circuit of claim 1, further comprising: a die attach structure having a first surface; wherein the first surface of the die is attached to the plurality of solder bumps to The first surface of the die attach structure. The integrated circuit of claim 8, wherein the die attach structure is an interposer. The integrated circuit of claim 8, wherein the die mounting structure is a package substrate. The integrated circuit of claim 1, wherein at least one of the plurality of solder bumps is coupled to a power supply voltage. The integrated circuit of claim 1, wherein at least one of the plurality of solder bumps is coupled to a data signal. The integrated circuit of claim 1, wherein at least one of the plurality of solder bumps is a mechanical solder bump. The integrated circuit of claim 1, wherein the analog circuit comprises at least one of a plurality of resistors, a plurality of capacitors, or a plurality of inductors. An integrated circuit comprising: an analog region of a die of the integrated circuit, the analog region comprising an analog circuit; Implementing a plurality of solder bumps on a surface of the die, the plurality of solder bumps being in a region vertically aligned with the analog region of the die; wherein the plurality of solder bumps The method includes: a first column of solder bumps having a fixed interval; and a second column of solder bumps, wherein a horizontal interval between adjacent solder bumps of the second column of solder bumps follows the second column of solder bumps The horizontal offset between successive pairs of solder bumps in the block increases non-linearly. The integrated circuit of claim 15, wherein the analog circuit comprises a plurality of current sources. The integrated circuit of claim 15, wherein the plurality of solder bumps comprise: a first row of solder bumps; and a second row of solder bumps; wherein the second row of solder bumps are The first row of solder bumps are offset from a direction parallel to the second row of solder bumps. The integrated circuit of claim 17, wherein the vertical spacing between adjacent solder bumps in the second row of solder bumps is fixed. The integrated circuit of claim 17, wherein the vertical spacing between adjacent solder bumps in the second row of solder bumps varies.