TWI602422B - Image processing device and method thereof - Google Patents

Description

Image processing device and method thereof

The present invention relates to an apparatus and method thereof, and more particularly to an image processing apparatus and method thereof that reduce the amount of hardware required to process an image.

The existing image processing module has a lack of large storage area, and the main reasons are as follows:

1. At least three buffers are needed: in order to detect the boundary of an image with a plurality of pixel values, the existing image processing module needs at least a 3×3 mask to simultaneously detect vertical and horizontal boundaries, such as As shown in Fig. 1 and Fig. 2, Fig. 1 is a mask for the left and right rows of coefficients with a non-zero weight to detect the level boundary, and Fig. 2 is a mask for the upper and lower rows of coefficients with a non-zero weight for detecting Vertical boundary, but whether it is detecting the horizontal boundary or detecting the vertical boundary, the image processing module needs to store the three columns of pixel values of the image to perform the operation using the 3×3 mask. Therefore, the image processing The module needs at least three buffers to store the three columns of pixel values, so that the hardware storage area is too large.

2. Each buffer has a large storage space: each buffer of the existing image processing module needs to store the R value of each pixel of each column of the image. (Red), G value (Green) and B value (Blue), therefore, each buffer needs to have a large storage space.

Accordingly, a first object of the present invention is to provide an image processing method capable of reducing a storage area of a hard body.

Therefore, the image processing method of the present invention is executed by an image processing device. The image processing device includes an image processing module. The image processing module includes a buffer for receiving an image, and receives the image and electrically connects the buffer. a serial to parallel output unit, and a processing unit electrically connected to the serial to parallel output unit, wherein the image comprises M columns of pixel columns, each column of pixels includes N pixel values, and 2≦M 3≦N, and M and N are positive integers. The image processing method comprises a step (A), a step (B), a step (C), and a step (D).

Step (A): the serial-to-parallel output unit receives a temporary serial data from the buffer, the temporary serial data comprising an n-th pixel value of the m-th column of pixels arranged in a series Up to the pth pixel value, the serial to parallel output unit converts the temporary serial data into a first parallel output, the first parallel output comprising the nth picture of the mth column of pixels arranged in parallel The prime value is to the pth pixel value, where 2≦pn, p≦N, 1≦m≦M-1, 1≦n≦N-2, and p, m, n are positive integers.

Step (B): the serial-to-parallel output unit receives a live serial data from the image, the live serial data comprising the n-th pixel of the (m+1)th column of pixel columns arranged in series a value to a p-th pixel value, the serial-to-parallel output unit converting the instantaneous serial data into a second parallel output, the second parallel output comprising the (m+1)th column of pixels arranged in parallel The nth pixel value to the pth pixel value.

Step (C): the processing unit receives the first parallel output and the second parallel output from the serial-to-parallel output unit, and convolves the first parallel output and the second parallel output with a mask Calculating to generate a convolution value, wherein the mask comprises two columns of coefficient columns, each column coefficient column has (p-n+1) coefficient weights, and the column of one of the two column coefficient columns is (p -n+1) coefficient weights respectively corresponding to the nth pixel value of the mth column pixel column of the first parallel output to the pth pixel value, and another column coefficient column of the two column coefficient column The (p-n+1) coefficient weights respectively correspond to the nth pixel value to the pth pixel value of the (m+1)th column pixel column of the second parallel output.

Step (D): the processing unit adds the b-th pixel value of the second parallel output and the convolution value to generate a b-th pixel of the (m+1)th column of the new image. Value, where n ≦ b ≦ p, and b is a positive integer.

Accordingly, a second object of the present invention is to provide an image processing apparatus capable of reducing a storage area of a hard body.

Therefore, the image processing apparatus of the present invention comprises an image processing module, the image processing module receives an image, the image includes M columns of pixel columns, and each column of pixels includes N pixel values, wherein 2 ≦M, 3≦N, and M and N are positive integers. The image processing module includes a buffer, a serial to parallel output unit, and a processing unit.

The buffer is configured to sequentially receive and store a real serial data from the image and convert it into a temporary serial data, where the real serial data comprises the nth pixel of the mth column of pixels arranged in series a value to a pth pixel value, and an nth pixel value of the (m+1)th column pixel column arranged in series to a pth pixel value, wherein the temporary string data includes a string Arranging the nth pixel value of the mth column of pixels to the pth pixel value, where 2≦pn, p≦N, 1≦m≦M-1, 1≦n≦N-2, And p, m, and n are positive integers.

The serial to parallel output unit is electrically connected to the buffer to receive the temporary serial data of the buffer, the temporary serial data comprising the nth pixel value of the mth column pixel column arranged in series Up to the pth pixel value, the live serial data from the image is further received, the live serial data comprising the nth pixel value of the (m+1)th column pixel column arranged in series The p-pixel values, the serial-to-parallel output unit converts the temporary serial data and the instantaneous serial data into a first parallel output and a second parallel output, respectively.

The processing unit is electrically connected to the serial-to-parallel output unit to receive the first parallel output and the second parallel output, and the first parallel output and the second parallel The output is subjected to a convolution operation with a mask to generate a convolution value, and then added according to the b-th pixel value of the second parallel output and the convolution value to generate the (m+1)th column of the new image. a b-th pixel value of the prime column, wherein the mask includes two columns of coefficient columns, each column coefficient column has (p-n+1) coefficient weights, and one of the column coefficient columns of the two column coefficient columns The (p-n+1) coefficient weights respectively correspond to the nth pixel value of the mth column pixel column of the first parallel output to the pth pixel value, and the other of the two column coefficient columns The (p-n+1) coefficient weights of a column of coefficient columns respectively correspond to the nth pixel value to the pth pixel value of the (m+1)th column pixel column of the second parallel output, wherein , n≦b≦p, b is a positive integer.

1‧‧‧Image processing device

11‧‧‧Image

L1~L36‧‧‧ L value of the pixel of the image

2‧‧‧Color gamut conversion unit

21‧‧‧ original image

O1~O36‧‧‧ primitive imagery

R1~R36‧‧‧ R value of the pixel of the original image

G1~G36‧‧‧G value of the pixel of the original image

B1~B36‧‧‧ B value of the pixel of the original image

3‧‧‧Image Processing Module

31‧‧‧ buffer

32‧‧‧Sequence to parallel output unit

33‧‧‧First positive and negative

34‧‧‧second flip-flop

35‧‧‧ third positive and negative

36‧‧‧fourth flip-flop

37‧‧‧Processing unit

38‧‧‧Operator

39‧‧‧Adder

4‧‧‧New imagery

△‧‧‧ convolution value

△1‧‧‧ another convolution value

The first phase of T1‧‧

Second phase of T2‧‧

T3‧‧‧ third stage

T4‧‧‧ fourth stage

A~P‧‧‧ steps

A0~A6‧‧‧ steps

Ck1‧‧‧first frequency signal

Ck2‧‧‧second frequency signal

Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a schematic diagram illustrating a 3×3 mask of a detection level boundary of a conventional image processing module; Is a schematic diagram illustrating a 3×3 mask for detecting vertical boundaries of an existing image processing module; FIG. 3 is a block diagram illustrating a first embodiment of the image processing method of the present invention; FIG. 4 is a schematic diagram illustrating An image processing module of the first embodiment of the image processing method; FIG. 5 is a flow chart illustrating a first embodiment of the image processing method of the present invention; FIG. 6 is a schematic diagram showing image conversion of the first embodiment of the image processing method of the present invention; FIG. The temporary storage serial data stored in the buffer of the first embodiment of the image processing method of the present invention is illustrated; FIG. 8 is a schematic diagram showing a first stage of the first embodiment of the image processing method of the present invention; 9 is a schematic diagram illustrating a second stage of the first embodiment of the image processing method of the present invention; FIG. 10 is a schematic diagram showing the first embodiment of the image processing method of the present invention adding 1 to the existing value of m as The next value, and the first stage is executed; FIG. 11 is a schematic diagram illustrating a new image of the first embodiment of the image processing method of the present invention; and FIG. 12 is a flowchart illustrating one of the image processing methods of the present invention. Steps (A1) to (A6) before the step (A) of the embodiment; FIG. 13 is a schematic view showing a third stage of the second embodiment of the image processing method of the present invention; FIG. 14 is a schematic view , explain this A fourth stage of the second embodiment of the image processing method of the invention; and Figure 15 is a schematic view showing a new image of the second embodiment of the image processing method of the present invention.

Referring to FIG. 3, a first embodiment of the image processing apparatus 1 of the present invention includes a color gamut converting unit 2 and an image processing module 3 electrically connected to the color gamut converting unit 2.

The image processing module 3 is electrically connected to the color gamut converting unit 2 and includes a buffer 31, a serial to parallel output unit 32, and a processing unit 37.

The buffer 31 is electrically connected between the color gamut converting unit 2 and the tandem to parallel output unit 32.

Referring to FIG. 4, the serial-to-parallel output unit 32 is electrically connected between the buffer 31, the color gamut converting unit 2, and the processing unit 37, and receives a first frequency signal Ck1 and a second frequency signal Ck2. The serial-to-parallel output unit 32 includes a first flip-flop 33, a second flip-flop 34, a third flip-flop 35, and a fourth flip-flop 36, wherein the first flip-flop 33. The second flip-flop 34, the third flip-flop 35 and the fourth flip-flop 36 are D-type flip-flops (FF).

The first flip-flop 33 has an input end electrically connected to the color gamut converting unit 2 for receiving an instant serial data, an output end, and a receiving the first frequency signal. At the frequency input end of Ck1, when the first frequency signal Ck1 is turned into a rising edge, the first flip-flop 33 samples the pixel value received at its input terminal and transmits it to its output terminal.

The second flip-flop 34 has an input terminal electrically connected to the buffer 31 for receiving a temporary serial data, an output terminal, and a frequency input terminal for receiving the second frequency signal Ck2, when the second frequency When the signal Ck2 is turned to the rising edge, the second flip-flop 34 samples the pixel value received at its input and transmits it to its output.

The third flip-flop 35 has an input terminal electrically connected to the output end of the second flip-flop 34, an output terminal electrically connected to the processing unit 37, and a frequency input terminal for receiving the second frequency signal Ck2. When the second frequency signal Ck2 is turned to the rising edge, the third flip-flop 35 samples the pixel value received at its input and transmits it to its output.

The fourth flip-flop 36 has an input terminal electrically connected to the output end of the first flip-flop 33, an output terminal electrically connected to the processing unit 37, and a frequency input end receiving the first frequency signal Ck1. When the first frequency signal Ck1 is turned to the rising edge, the fourth flip-flop 36 samples the pixel value received at its input and transmits it to its output.

The processing unit 37 is electrically coupled to the serial to parallel output unit 32 and includes an operator 38 and an adder 39.

The operator 38 stores a mask and electrically connects the first flip-flop 33 to the input of the fourth flip-flop 36 and the third flip-flop 35 and the fourth flip-flop 36 Wait for the output.

The adder 39 is electrically coupled to the operator 38 and the output of the first flip-flop 33.

Referring to FIG. 5, the image processing apparatus 1 performs an image processing method. The image processing method includes the following steps: Referring to FIG. 3 and FIG. 6 simultaneously, the step (A0): the color gamut converting unit 2 receives an original image 21, and The RGB values R1~R36, G1~G36, and B1~B36 of the plurality of pixels O1~O36 of the original image 21 are respectively converted into a plurality of pixel values L1~L36, wherein the pixel values L1~L36 are combined This image is 11.

More specifically, the color gamut conversion unit 2 receives an RGB color gamut of the original image 21 and converts the RGB color gamut into an HSL color gamut. The so-called RGB color gamut is in red, green, and The blue color is the main color element of the three primary colors, and the HSL color gamut is the color element mainly composed of Hue, Saturation and Lightness/Luminance.

That is, the color gamut converting unit 2 converts the RGB values R1 R R36, G1 G G36, and B1 B B36 of the plurality of pixels O1 to O36 of the original image 21 into a plurality of HSL values, and stores the HSLs. The image has a plurality of L values (brightness) L1~L36, and the image 11 includes M columns of pixels, and each column of pixels includes N pixels. a pixel, and each pixel has a pixel value (brightness), that is, the image includes M×N pixel values, wherein the M×N pixel values L1 to L36 are the M×N The brightness of the pixels, where 2 ≦ M, 3 ≦ N, and M and N are positive integers.

In addition, it should be noted that the values of the pixel values R1 R R36, G1 G G36, B1 B B36, and L1 L L36 of the original image 21 and the image 11 of FIG. 6 are only for convenience of description, and are not actual. The values of the pixels are, and in the embodiment, the image 11 is in six columns of pixels (M=6), and each column of pixels is exemplified by six pixel values (N=6).

Step (A1): the buffer 31 sequentially receives and stores the instant serial data from the image 11 and converts the instantaneous serial data into the temporary serial data, wherein the instant serial data includes a string The nth pixel value of the mth column of pixels arranged in the column to the pth pixel value, wherein 2≦pn, p≦N, 1≦m≦M-1, 1≦n≦N -2, and p, m, and n are positive integers.

The buffer 31 of the present embodiment is defined herein to have a storage space for storing seven pixel values, and the mask has six (2×3) coefficient numbers, but is not limited thereto, and can be set according to actual needs. In step (A1), the buffer 31 sequentially receives the real-time serial data including the pixel values L1 L L3, and temporarily stores the pixel values L1 L L3 of the real-time serial data in the buffer 31 as The temporary serial data.

It should be noted that, when performing the step (A1), the image processing apparatus 1 maintains the first frequency signal Ck1 at a low level before the buffer is filled with pixels. The first flip-flop 33 of the serial-to-parallel output unit 32 does not sample the instantaneous serial data including the pixel values L1 L L3, and the second frequency signal Ck2 is maintained at the low level. The second flip-flop 34 of the serial-to-parallel output unit 32 does not sample the temporary string from the buffer 31, and the operator 38 does not completely receive the six pixel values L1 to L6 before There is no convolution operation with the mask.

Referring to FIG. 7 , when the image processing apparatus 1 repeatedly performs the step (A1), the buffer 31 sequentially receives and stores the instant serial data from the image 11 and converts the real serial data into the temporary storage. The illustration of the serial data indicates that until the buffer 31 of the image processing apparatus 1 completes all the pixel values L1 L L6 of the first column of the real string data of the image 11 , the process proceeds to the step ( A).

Step (A): the serial-to-parallel output unit 32 receives the temporary serial data from the buffer 31, the temporary serial data including the n-th pixel of the m-th column of pixels arranged in series a value to a pth pixel value, the serial to parallel output unit 32 converting the temporary serial data into a first parallel output, the first parallel output comprising nth of the mth column of pixels arranged in parallel The pixel value to the pth pixel value.

Step (B): the serial-to-parallel output unit 32 receives the live serial data from the image 11, the live serial data comprising the nth of the (m+1)th column of pixel columns arranged in series The pixel value to the pth pixel value, the serial to parallel output unit 32 converts the immediate serial data into a second parallel output, the second parallel output including the (m+1)th column in parallel The nth pixel value of the prime column to the pth pixel value. Such as The temporary serial data includes pixel values L1~L3, and the real serial data includes pixel values L7~L9, and the first parallel output includes pixel values L1~L3, and the second parallel output includes drawing Prime value L7~L9.

Step (I): The buffer 31 sequentially receives and stores the nth pixel value of the m+1th column of the real string data to the pth pixel value. For example, if the real-time serial data is a pixel value L7~L9, the buffer 31 stores the pixel values L7~L9 of the real-time serial data.

Step (C): the processing unit 37 receives the first parallel output and the second parallel output from the serial-to-parallel output unit 32, and performs the first parallel output and the second parallel output with the mask The convolution operation produces the convolution value Δ.

Before the description of the more detailed steps (A) to (C), it should be noted that the operation of the serial-to-parallel output unit 32 described in the steps (A) and (B) is to simultaneously receive the sequence. The nth pixel value of the mth column pixel column of the temporary string data to the pth pixel value and the nth picture of the (m+1)th column pixel column of the instant string data Prime value to p-th pixel value.

Here, in the first stage T1 and the second stage T2, the steps (A) to (C) of the steps are explained in more detail:

<First stage T1>

Referring to FIG. 8, when the first frequency signal Ck1 is turned into a rising edge, the first flip-flop 33 samples the pixel value L7 of the instantaneous serial data and transmits it to the fourth flip-flop. At the input end of 36, when the first frequency signal Ck2 is turned into a rising edge, the second flip-flop 34 samples the pixel value L1 of the temporary serial data from the buffer and transmits to the third positive and negative At the input of the processor 35, the buffer 31 receives and stores the pixel value L7 of the instantaneous serial data.

At the same time, the pixel value L8 of the instant serial data is transmitted to the input end of the first flip-flop 33, and the pixel value L2 from the buffer is transmitted to the input end of the second flip-flop 34 to prepare The next rising edge of the first frequency signal Ck1 and the second frequency signal CK2 is sampled.

Therefore, in the first phase T1, the first parallel output and the second parallel output received by the operator 38 include only the two first pixel values L1, L7 and the two second paintings. The prime values L2, L8, therefore, the operator 38 is unable to perform a convolution operation with the mask such that the adder 39 can only receive the first pixel value from the output of the first flip-flop 33 L7 (b is equal to 1), so the first pixel value of the second column of pixels of the new image 4 output by the adder 39 is equivalent to the first pixel value L7 (see FIG. 11). .

<Second stage T2>

Referring to FIG. 9, when the first frequency signal Ck1 is turned into a rising edge, the fourth flip-flop 36 samples the pixel value L7 and transmits it to the operator 38, and the first flip-flop 33 pairs the real-time string. The pixel value L8 of the column data is sampled and transmitted to the input end of the fourth flip-flop 36. When the second frequency signal Ck2 is turned to the rising edge, the third flip-flop 35 is paired. The pixel value L1 of the temporary serial data is sampled and transmitted to the operator 38, and the second flip-flop 34 samples the pixel value L2 of the temporary serial data from the buffer and transmits to the pixel value L2. The input end of the third flip-flop 35 receives and stores the pixel value L8 of the instantaneous serial data.

At the same time, the pixel value L9 of the instantaneous serial data is transmitted to the input end of the first flip-flop 33, and the pixel value L3 from the buffer is transmitted to the input end of the second flip-flop 34 to prepare for The next rising edge of the first frequency signal Ck1 and the second frequency signal CK2 is sampled.

Therefore, in this second phase T2, the first parallel output and the second parallel output received by the operator 38 include pixel values L1, L2, L3 and pixel values L7, L8, L9, that is, The total number of the pixel values received by the operator 38 is equal to the number of coefficients of the mask (a is equal to 6), and therefore, it is possible to proceed to step (C).

The arithmetic unit 38 of the processing unit 37 generates a convolution value Δ by performing a convolution operation on the mask based on the six pixel values L1 to L3 and L7 to L9.

It should be noted that the operator 38 of the processing unit 37 obtains the convolution value Δ by the convolution operation formula of (Formula 1).

Wherein, the parameters X1 to X6 represent the pixel values received by the operator 38, and the parameter G is the coefficient weight of the mask corresponding to the bth pixel value, and the number of coefficients of the mask is equal to The number of the pixel values received by the operator 38, and the coefficient weight of the mask corresponding to the bth pixel value is higher. In addition, it should be noted that the coefficient weight of the mask is The design point is that the coefficient weights of all coefficients are added equal to zero. Therefore, the coefficient weight of G is {-[(-1)+(-1)+...+(-1)+(-1)+(-1)]} .

Referring to FIG. 9, in the second stage T2, the output end of the first flip-flop 33 outputs the second pixel value L8 of the second parallel output, so the second pixel value L8 is mainly Convert the pixel, that is, the value of the coefficient weight of the mask corresponding to the second pixel value L8 should be larger, in this case, G is 5 as an example (G={-[(- 1) + (-1) + (-1) + (-1) + (-1)]} = 5), therefore, the current value Δ of the present embodiment is as shown in (Formula 2).

In addition, the mask includes two columns of coefficient columns, each column coefficient column has three (p-n+1=3-1+1=3) coefficient weights, and one of the column coefficient columns of the two column coefficient columns The three coefficient weights ([-1, -1, -1]) respectively correspond to the first pixel value (n = 1) to the third picture of the first column of the first column of parallel output Prime value (p=3), and the three columns of the two column coefficient columns ([-1,5,-1]) The coefficient weights respectively correspond to the first pixel value (n=1) to the third pixel value (p=3) of the second column of pixel columns of the second parallel output.

Step (D): the processing unit 37 adds the b-th pixel value of the second parallel output and the convolution value Δ to generate the bth of the (m+1)th column of the new image 4 The pixel value, where n≦b≦p, b is a positive integer.

The adder 39 of the processing unit 37 adds the second pixel value L8 (b equal to 2) and the convolution value Δ of the second parallel output to generate a second column of pixels of the new image 4. The second pixel value is M8 (see Figure 11).

Step (E): The processing unit 37 determines whether the existing value of p is equal to N, and if so, completes the image processing of the (m+1)th column of the new image 4, and if not, proceeds to step (F) ).

The processor of the processing unit 37 determines that only the first pixel value of the first column of pixels column and the second column of pixel columns is received to the third pixel value, and therefore, the processing unit 37 It is judged that the existing value of p (p=3) is not equal to N (N=6), and the six pixel values of the second column of pixels are not yet completed, and the process proceeds to step (F).

Step (F): The processing unit 37 adds 1 to the existing value of n as the next value, and increments the existing value of p by 1 as the next value, and returns to step (A).

The processing unit 37 adds 1 (n=1+1) to the existing value of n, and adds 1 (P=3+1) to the existing value of p, and repeats steps (A) to (E) repeatedly, followed by actuation and The same as above, and will not be described again here, until the processing unit 37 of the step (E) judges the existing p When the value is equal to N (N=6), the image processing of the second column of pixels of the new image 4 is completed, and the process proceeds to step (G).

Step (G): The processing unit 37 determines whether the existing value of m is equal to (M-1), and if so, completes the image processing of the new image 4, and if not, proceeds to step (H).

Step (H): The processing unit 37 adds 1 to the existing value of m as the next value, and the next value of n is equal to 1, and returns to step (A).

The processor of the processing unit 37 determines that the existing value of m is only equal to 2, and is not equal to (M-1) (M=6), that is, the processing unit 37 only completes the third column of pixels of the new image 4. Image processing, the image processing of the six columns of pixels has not been completed, and the step (H) is added to the existing value of m by 1 (m=2+1) as the next value, and the next value of n is equal to 1 And returning to step (A), the serial-to-parallel output unit 32 continues to receive the temporary serial data from the buffer 31 (see FIG. 10), wherein the temporary serial data is the second column of pixels The first pixel value of the column (n=1) to the third pixel value (p=3) L7~L9, the subsequent actuation is the same as above, and will not be described here until the processor of step (G) If it is judged that the existing value of m is equal to M-1 (M=6), the image processing of the new image 4 is completed.

In addition, the coefficient weight of the mask of the above embodiment may also be This type is presented. At this time, the coefficient weight of G is 3 (G={-[(-1)+(-1)+(-1)]})), but it is not limited to this. design.

Referring to FIG. 12, a second embodiment of the image processing apparatus of the present invention is similar to the first embodiment, except that the step (A) of the image processing method performed by the second embodiment further includes a step (A1). Go to step (A6) and replace step (A1) of the first embodiment with steps (A1) through (A6), and the operator 38 of the processing unit 37 also stores another mask, the other The mask has three (1 x 3) coefficient numbers and is used to process the image processing of the first column of pixels (m equal to 1) of the image 11.

Step (A1): the serial-to-parallel output unit 32 receives the live serial data from the image 11, the live serial data including the n-th pixel value of the m-th column of pixels arranged in series to a qth pixel value, the serial to parallel output unit 32 converts the immediate serial data into a third parallel output, the third parallel output comprising nth pixels of the mth column of pixel columns arranged in parallel The value is to the qth pixel value, where 2+n≦q≦N, and q is a positive integer.

Step (A6): The buffer 31 sequentially receives and stores the nth pixel value of the mth column pixel column of the instant string data to the qth pixel value.

Step (A2): the processing unit 37 receives the third parallel output from the serial-to-parallel output unit 32, and performs a convolution operation on the third parallel output with another mask to generate another convolution value Δ 1, wherein the another mask comprises a column of coefficient columns, each column coefficient column has (q-n+1) coefficient weights, and the column coefficient column (q-n+1) coefficient weights respectively correspond to the nth pixel value to the qth pixel value of the mth column pixel column of the third parallel output.

Step (A3): the processing unit 37 adds the b-th pixel value of the third parallel output and the another convolution value Δ1 to generate the bth pixel of the m-th column of the new image 4. Pixel value.

Here, the third stage T3 and the fourth stage T4 are explained for the step (A1), the step (A6), the step (A2), and the step (A3).

<third stage T3>

Referring to FIG. 13, when the first frequency signal Ck1 is turned into a rising edge, the first flip-flop 33 includes the first pixel of the first column of pixels (m is equal to 1) included in the instantaneous serial data. The value L1 (n is equal to 1) is sampled and transmitted to the input terminal of the fourth flip-flop 36. At this time, the second frequency signal Ck2 remains at a low level without change, and therefore, the second flip-flop 34 The temporary serial data from the buffer 31 is not sampled, and the buffer 31 receives and stores the first pixel value L1 of the first column of pixels of the immediate serial data.

At the same time, the pixel value L2 of the instantaneous serial data is transmitted to the input terminal of the first flip-flop 33 to be sampled at the next rising edge of the first frequency signal Ck1.

Therefore, in this third stage T3, the operator 38 receives the third parallel output including only the first pixel value L1 and the first column of the instant string data. The second pixel value L2 of the prime column, so the operator 38 cannot perform a convolution operation with the other mask, such that the adder 39 can only receive the output from the output of the first flip-flop 33 The first pixel value L1 (b is equal to 1), so the first pixel value of the first column of pixels of the new image 4 output by the adder 39 is equivalent to the first of the image 11 The pixel value L1 (see Figure 15).

<Fourth stage T4>

Referring to FIG. 14, when the first frequency signal Ck1 is turned into a rising edge, the fourth flip-flop 36 samples the first pixel value L1 of the instantaneous serial data and transmits the result to the operator 38. A flip-flop 33 samples the second pixel value L2 of the first column of pixel columns of the instantaneous serial data and transmits the same to the input end of the fourth flip-flop 36, the second frequency signal at this time Ck2 still maintains a low level without change. Therefore, the second flip-flop 34 does not sample the temporary serial data from the buffer 31, and the buffer 31 receives and stores the instantaneous serial data. The second column of the first column is the second pixel value L2.

At the same time, the third pixel value L3 (p is equal to 3) of the first column of pixel columns of the instant string data is transmitted to the input end of the first flip-flop 33 to prepare for the first frequency signal. The next rising edge of Ck1 is sampled.

Therefore, in the fourth stage T4, the third parallel output received by the operator 38 is composed of the first pixel value L1, the second pixel value L2, and the third pixel value L3. That is, the total number of such pixel values received by the operator 38 The number (the first pixel value L1, the second pixel value L2, and the third pixel value L3) is equal to the number of coefficients of the other mask (a is equal to 3), and therefore, the processing unit The operator 38 of 37 can generate the other rotation according to the third parallel output (the first pixel value to the third pixel value L1~L3) and the other mask. The product value is △1.

It should be noted that the coefficient weight of the other mask of the second embodiment is [-1 G -1], respectively, and therefore, the coefficient weight of G is 2 (G={-[(-1)+(- 1)]}), so another convolution value Δ1 of this step (A2) is as shown in (Equation 3).

Step (A3): the processing unit 37 adds the b-th pixel value of the third parallel output and the another convolution value Δ1 to generate the bth pixel of the m-th column of the new image 4. Pixel value.

The adder 39 of the processing unit 37 adds the second pixel value L2 (b=2) of the third parallel output and the other convolution value Δ1 to generate the first column of the new image 4. The second pixel value of the prime M2 (see Figure 34).

Step (A4): the processing unit 37 determines whether the existing value of q is equal to N, and if so, completes the image processing of the mth column of the new image 4 and proceeds to step (A), and if not, proceeds to the step (A5).

The processing unit 37 judges that the existing value (q=3) of q is not equal to N (N=6), and has not completed the six pixel values of the first column of pixels, and proceeds to step (A5).

Step (A5): The processing unit 37 adds 1 to the existing value of n as the next value, and increments the existing value of q by 1 as the next value, and returns to step (A1).

The processing unit 37 adds 1 (n=1+1) to the existing value of n, and adds 1 (q=3+1) to the existing value of q, and returns to step (A1) to repeat the execution, and the subsequent operation is the same as above. Therefore, the processing unit 37 of the step (A4) determines that the existing value of q is equal to N (N=6), and the image processing of the first column of the new image 4 is completed, and the processing proceeds to the step. (A) The action of the first embodiment is continuously repeated.

In summary, the above embodiment has the following two advantages:

1. Only one buffer 31 is needed: the image processing module 3 only needs one buffer 31 to store the nth pixel value of the mth column pixel column of the image 11 to the pth pixel value, and then use the The serial-to-parallel output unit 32 sequentially receives the N pixel values of the m-th column of pixel columns stored in the buffer 31, and simultaneously receives the (m+1)th column of the image 11 in sequence. The nth pixel value of the prime column to the pth pixel value, and according to the received nth pixel value of the mth column of pixels, to the pth pixel value, (m+1) The nth pixel value to the pth pixel value of the column of the column is subjected to a convolution operation with the mask to generate the new image 4, thereby achieving the effect of simultaneously detecting the level boundary and the vertical boundary, and The new image 4 achieves a certain level of sharpening effect and is suitable for a driver or a touch IC.

2. The storage space of each buffer 31 is reduced: due to the technical means of color gamut conversion, the buffer 31 of the image processing apparatus 1 stores only the L value (brightness) of each pixel, and the existing image processing module Each of the buffers 31 of 3 stores R values (red), G values (green), and B values (blue) for each pixel. Obviously, the storage required for the buffer 31 of the image processing apparatus 1 of the present invention is required. The space is reduced by about two-thirds of the space of the existing image processing module.

Therefore, the image processing method of the present invention can realize the simultaneous detection of the level boundary and the vertical boundary in a manner of reducing the hardware storage area, and can achieve a certain level of sharpening effect, and indeed achieve the object of the present invention.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.

1‧‧‧Image processing device

2‧‧‧Color gamut conversion unit

3‧‧‧Image Processing Module

31‧‧‧ buffer

32‧‧‧Sequence to parallel output unit

37‧‧‧Processing unit

Ck1‧‧‧first frequency signal

Ck2‧‧‧second frequency signal

Claims (8)

An image processing method is executed by an image processing device. The image processing device includes an image processing module. The image processing module includes a buffer for receiving an image, and a serial array for receiving the image and electrically connecting the buffer. a parallel output unit, and a processing unit electrically connected to the serial to parallel output unit, wherein the image comprises M columns of pixel columns, each column of pixels includes N pixel values, and 2≦M, 3≦ N, and M and N are positive integers. The image processing method includes: (A) the serial-to-parallel output unit receives a temporary serial data from the buffer, the temporary serial data comprising a tandem array The mth column of the nth pixel value to the pth pixel value, the serial to parallel output unit converts the temporary serial data into a first parallel output, the first parallel output including parallel Arranging the nth pixel value of the mth column of pixels to the pth pixel value, where 2≦pn, p≦N, 1≦m≦M-1, 1≦n≦N-2, And p, m, n are positive integers; (B) the serial to parallel output unit receives a live serial data from the image, The instant serial data includes the nth pixel value to the pth pixel value of the (m+1)th column pixel column arranged in series, and the serial to parallel output unit converts the real serial data into one a second parallel output, the second parallel output comprising the nth pixel value of the (m+1)th column pixel column arranged in parallel to the pth pixel value; (C) the processing unit receives the string from the string And rotating the first parallel output and the second parallel output of the parallel output unit, and performing a convolution operation on the first parallel output and the second parallel output and a mask to generate a convolution a value, wherein the mask includes two columns of coefficient columns, each column coefficient column has (p-n+1) coefficient weights, and the (p-n+1) of one of the column coefficient columns of the two column coefficient columns The coefficient weights respectively correspond to the nth pixel value of the mth column pixel column of the first parallel output to the pth pixel value, and the other column coefficient column of the two column coefficient column (p-n +1) coefficient weights respectively corresponding to the nth pixel value of the (m+1)th column pixel column of the second parallel output to the pth pixel value; (D) the processing unit according to the second The b-th pixel value of the parallel output and the convolution value are added to generate a b-th pixel value of the (m+1)th column of the new image, where n≦b≦p; The processing unit determines whether the existing value of p is equal to N, and if so, completes image processing of the (m+1)th column of the new image, and if not, proceeds to step (F); and (F) The processing unit adds 1 to the existing value of n as the next value, and increments the existing value of p by 1 as the next value, and returns to step (A). The image processing method according to claim 1, wherein when the step (E) determines that the existing value of p is equal to N, the step (E) further comprises (G) the processing unit determining whether the existing value of m is equal to (M- 1), if yes, complete the image processing of the new image, if not, proceed to step (H), and (H) the processing unit increments the existing value of m as the next value, and the next value of n is equal to 1. Return to step (A). The image processing method of claim 1, wherein the step (B) and the step (C) further comprise (I) The buffer sequentially receives and stores the nth pixel value of the m+1th column of the real string data to the pth pixel value. The image processing method of claim 1, wherein the step (A) further comprises (A1) the buffer sequentially receiving and storing the instant serial data of the image, and converting the instant serial data into The temporary serial data includes the nth pixel value of the mth column pixel column of the tandem array to the pth pixel value. The image processing method of claim 1, wherein the step (A) further comprises (A1) the serial-to-parallel output unit receiving the live serial data from the image, the live serial data comprising a serial Arranging the nth pixel value of the mth column of pixels to the qth pixel value, the serial to parallel output unit converting the instantaneous serial data into the third parallel output, the third parallel output The nth pixel value of the mth column of pixel columns arranged in parallel to the qth pixel value, wherein 2+n≦q≦N, and q is a positive integer, (A2) the processing unit receives the The series is rotated to the third parallel output of the parallel output unit, and the third parallel output is subjected to a convolution operation with another mask to generate another convolution value, wherein the other mask is used for the image Performing sharpening processing and simultaneously detecting the level boundary, and including a column of coefficient columns, each column coefficient column has (q-n+1) coefficient weights, and the (q-n+1) of the column coefficient columns The coefficient weights respectively correspond to the nth pixel value to the qth pixel value of the mth column pixel column of the third parallel output. (A3) the processing unit adds the b-th pixel value of the third parallel output and the another convolution value to generate a b-th pixel value of the m-th column of the new image, (A4) The processing unit determines whether the existing value of q is equal to N, and if so, completes the image processing of the mth column of the new image and proceeds to step (A), and if not, proceeds to step (A5), and A5) The processing unit adds 1 to the existing value of n as the next value, and increments the existing value of q by 1 as the next value, and returns to step (A1). The image processing method of claim 5, wherein the step (A1) and the step (A2) further comprise (A6) the buffer sequentially receiving and storing the mth column of pixels of the instant serial data. The nth pixel value of the column to the qth pixel value. An image processing device includes an image processing module, the image processing module receives an image, the image includes M columns of pixels, and each column of pixels includes N pixel values, wherein 2≦M, 3≦ N, and M and N are positive integers. The image processing module includes a buffer for sequentially receiving and storing a real serial data from the image and converting it into a temporary serial data, the real serial data. The nth pixel value of the mth column pixel column arranged in a series arrangement to the pth pixel value, and the nth pixel value of the (m+1)th column pixel column arranged in the string arrangement Up to the pth pixel value, and the temporary string data includes the nth pixel value to the pth pixel value of the mth column pixel column arranged in series, wherein 2≦pn,p≦ N,1≦m≦M-1,1≦n≦N-2, and p, m, n are positive integers; a serial to parallel output unit electrically connected to the buffer to receive the temporary serial data of the buffer, the temporary serial data comprising the nth pixel of the mth column of pixels arranged in series Receiving, to the p-th pixel value, the live serial data from the image, the live serial data comprising the nth pixel value of the (m+1)th column of pixel columns arranged in series to a p-th pixel value, the serial-to-parallel output unit converts the temporary serial data and the instantaneous serial data into a first parallel output and a second parallel output, respectively; and a processing unit electrically connecting the string And rotating the parallel output unit to receive the first parallel output and the second parallel output, and performing a convolution operation on the first parallel output and the second parallel output and a mask to generate a convolution value, according to the Adding the bth pixel value of the second parallel output and the convolution value to generate a bth pixel value of the (m+1)th column of the new image, wherein the mask includes two columns Coefficient column, each column coefficient column has (p-n+1) coefficient weights, and one of the two column coefficient columns The (p-n+1) coefficient weights of the column respectively correspond to the nth pixel value to the pth pixel value of the mth column pixel column of the first parallel output, and the two column coefficient columns The (p-n+1) coefficient weights of the other column coefficient column respectively correspond to the nth pixel value to the pth pixel value of the (m+1)th column pixel column of the second parallel output. Wherein, n≦b≦p, b is a positive integer; wherein the serial to parallel output unit comprises a first flip-flop having an input end, an output end, and a frequency input end, the first positive The input end of the counter is configured to sequentially receive the instantaneous serial data from the image, and the frequency input end of the first flip-flop is configured to receive a first frequency signal, when the first frequency signal is converted to Rising edge The first flip-flop samples a pixel value received at its input end and transmits it to its output terminal. A second flip-flop has an input terminal, an output terminal, and a frequency input terminal. The input end of the second flip-flop is electrically connected to the buffer for receiving the temporary serial data, and the frequency input of the second flip-flop is configured to receive a second frequency signal, when the first When the two frequency signals are turned to the rising edge, the second flip-flop samples the pixel values received at the input end thereof and transmits them to the output end thereof, and a third flip-flop has an input end and an output end. And a frequency input end, the input end of the third flip-flop is electrically connected to the output end of the second flip-flop, the output end of the third flip-flop is electrically connected to the processing unit, and the third The frequency input end of the flip-flop is electrically connected to the frequency input end of the second flip-flop to receive the second frequency signal, and when the second frequency signal turns to a rising edge, the third flip-flop pair The pixel value received at the input is sampled and transmitted to its output, and a fourth flip-flop, An input end, an output end, and a frequency input end, the output end of the third flip-flop is electrically connected to the processing unit, the input end of the fourth flip-flop is electrically connected to the first flip-flop An output end, wherein the frequency input end of the fourth flip-flop is electrically connected to the frequency input end of the first flip-flop to receive the first frequency signal, when the first frequency signal is turned into a rising edge, The fourth flip-flop samples a pixel value received at its input and transmits it to its output. The image processing device of claim 7, wherein the processing unit comprises An operator storing a mask and electrically connecting the serial to parallel output unit to receive the first parallel output and the second parallel output, and according to the first parallel output, the second parallel output, and the mask Performing a convolution operation to generate a convolution value, wherein the mask is used to sharpen the image and simultaneously detect the level boundary and the vertical boundary, and includes two columns of coefficient columns, each column coefficient column having ( P-n+1) coefficient weights, and the (p-n+1) coefficient weights of one of the column coefficient columns of the two column coefficient columns respectively correspond to the first m-th column pixel sequence of the first parallel output n pixel values to the pth pixel value, and the (p-n+1) coefficient weights of the other column coefficient column of the two column coefficient columns respectively correspond to the first (m+) of the second parallel output 1) arranging the nth pixel value of the prime column to the pth pixel value, and an adder electrically connecting the serial to parallel output unit and the operator to respectively receive the bth of the second parallel output a pixel value and the convolution value, and adding according to the bth pixel value and the convolution value to generate a complex image of the new image Wherein the row pixel column wherein a plurality of pixel value of the pixel values of a, wherein, n ≦ b ≦ p.