TWI601152B - Semiconductor memory device - Google Patents

Description

Semiconductor memory device

Embodiments of the present invention relate to a semiconductor memory device.

Semiconductor memory devices such as NAND (Not AND) type flash memory are well known.

Embodiments of the present invention provide a semiconductor memory device that can accurately detect data.

The semiconductor memory device of this embodiment includes a memory cell array having a plurality of memory cells. A plurality of character line lines are connected to a plurality of memory cells. A plurality of bit lines are connected to one of the current paths of the plurality of memory cells. The sense amplifier section repeats the plurality of detection operations when detecting the data of the memory cell connected to the word line WLn (n is an integer) in the word line. The control unit selects any one of a plurality of detection results obtained by the plurality of detection operations based on the data of the memory cell connected to the word line WLn-1 and the data of the memory cell connected to the word line WLn+1.

1‧‧‧ memory cell array

2a‧‧‧ Column Decoder/Word Line Driver

2b‧‧‧ line decoder

3‧‧‧Page Buffer

4‧‧‧NAND unit unit

5a‧‧‧ column address register

5b‧‧‧ row address register

6‧‧‧Logic Controller

7‧‧‧Sequence control circuit

8‧‧‧Internal voltage generation circuit

9‧‧‧I/O buffer

10‧‧‧NAND chip

11‧‧‧ Controller

ALE‧‧‧ address latch activation signal

Bce‧‧‧ chip drive signal

bRE‧‧‧Read start signal

bWE‧‧‧Write start signal

BL‧‧‧ bit line

BL0‧‧‧ bit line

BL1‧‧‧ bit line

BLi-1‧‧‧ bit line

BLi-2‧‧‧ bit line

BLkm-1‧‧‧Unit Block

BLK1‧‧‧ unit block

BLK0‧‧‧ unit block

CELSRC‧‧‧Shared source line

CLE‧‧‧ command start signal

E1‧‧‧

E2‧‧‧

E3‧‧‧

E4‧‧‧

LM‧‧‧

LM1‧‧‧

LM2‧‧‧

LM3‧‧‧

MC0‧‧‧ memory cell

MC1‧‧‧ memory cell

MC2‧‧‧ memory cell

MC63‧‧‧ memory cell

MCn-1‧‧‧ memory cell

MCn+1‧‧‧ memory cell

S1‧‧‧O crystal

S2‧‧‧O crystal

SA‧‧‧Sense Amplifier Circuit

SGD‧‧‧Selected gate line

SGS‧‧‧Selected gate line

VA‧‧‧voltage level

VB‧‧‧ voltage level

VC‧‧‧ voltage level

VLM‧‧‧

VLM1‧‧‧

VLM2‧‧‧

VLM3‧‧‧

VREAD‧‧‧ high level voltage

WL0‧‧‧ character line

WL1‧‧‧ character line

WL2‧‧‧ character line

WL62‧‧‧ character line

WL63‧‧‧ character line

Fig. 1 is a block diagram showing the configuration of a NAND flash memory system according to the first embodiment.

Fig. 2 is a view showing a concrete configuration of the cell array 1.

Fig. 3 is a view showing a threshold distribution of memory cells MC when writing of 2-bit data is performed.

Fig. 4 is a view showing a page writing sequence in a memory block.

5(A) to 5(D) are diagrams showing the adjacent interference effects of the lower-order pages of the plurality of memory cells MCn connected to the word line WLn.

6(A) to 6(C) are timing charts showing the IDL operation of the memory of the first embodiment.

7(A) to 7(C) are timing charts showing the IDL operation of the memory of the first modification of the first embodiment.

8(A) to 8(C) are timing charts showing the IDL operation of the memory of the second modification of the first embodiment.

9(A) to 9(C) are timing charts showing the IDL operation of the memory of the second embodiment.

10(A) to 10(C) are timing charts showing the IDL operation of the memory of the third embodiment.

11(A) to 11(C) are timing charts showing the IDL operation of the memory of the fourth embodiment.

Fig. 12(A) is a table showing selection results of selection of three detection results from the memory cell MCn.

Fig. 12(B) is a table showing selection results of selection of two detection results from the memory cell MCn.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. For the sake of explanation, the common reference numerals are added to the shared portions for all the drawings. However, it should be noted that the drawing is a schematic diagram, the relationship between the thickness and the plane size, the thickness ratio of each layer, and the like are different from the actual ones.

Therefore, the specific thickness or size should be judged by considering the following instructions. Further, of course, the drawings also include mutually different dimensional relationships or ratios.

(First embodiment)

Fig. 1 is a block diagram showing an example of a configuration of a NAND flash memory according to the first embodiment. The NAND flash memory of the present embodiment includes a NAND wafer 10 and a controller 11 that controls the NAND wafer 10. The NAND wafer 10 and the controller 11 can be resin-sealed to one package as a multi-chip package (MCP).

The memory cell array 1 constituting the NAND wafer 10 is configured by two-dimensionally arranging a plurality of memory cells MC in a matrix. This memory cell MC has a charge accumulation layer. The memory cell MC is not limited to a FG (Floating Gate) type memory cell, and may be, for example, a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell. The column decoder/word line driver 2a, the row decoder 2b, the page buffer 3, and the internal voltage generating circuit 8 constitute data writing/reading of data writing and reading to the memory cell array 1 in units of pages. Circuit. The column decoder/word line driver 2a selectively drives the word lines of the memory cell array 1. The page buffer 3 has a one-page sense amplifier circuit and a data hold circuit, and reads and writes data to the memory cell array 1 in units of pages.

The read data of one page of the page buffer 3 is sequentially selected by the row decoder 2b, and output to the external I/O terminal via the I/O (Input/Out) buffer 9. The write data supplied from the I/O terminal is selected by the row decoder 2b and loaded into the page buffer 3. A page amount of write data is loaded to the page buffer 3. The column address signal and the row address signal are input via the I/O buffer 9, and are transmitted to the column decoder 2a and the row decoder 2b, respectively. The column address register 5a saves the deleted block address in the delete operation, and saves the page address in the write or read operation. Before the start of the write operation, the row address register 5b is input with a header row address for loading the write data or a header row address for the write operation. The row address register 5b will save the input row address before switching the write enable signal bWE or the read enable signal bRE under certain conditions.

The logic control circuit 6 is based on the wafer drive signal bCE, the command enable signal CLE, the bit Address latch enable signal ALE, write enable signal bWE, read enable signal bRE and other control signals, control commands or address input, and control data input and output. The read action or the write action is performed in accordance with the instruction. The sequence control circuit 7 receives an instruction to perform sequence control of reading, writing or deleting. The internal voltage generating circuit 8 receives the external power supply voltage VCC and is controlled by the control circuit 7 to generate a specific voltage required for various operations. The internal power supply voltage VDC for the sense amplifier described below is generated in the internal voltage generating circuit 8.

The controller 11 performs writing and reading control of data in a condition suitable for the current write state of the NAND wafer 10. Furthermore, it is of course also possible to perform a part of the read control on the NAND wafer 10 side.

FIG. 2 is a view showing an example of a specific configuration of the memory cell array 1. In this example, 64 memory cells MC0 to MC63 connected in series and selected gate transistors S1 and S2 connected to both ends thereof constitute a NAND unit cell (NAND string) 4. The source of the gate transistor S1 is connected to the common source line CELSRC, and the gate of the gate transistor S2 is connected to the bit line BL (BL0~BLi-1). That is, the bit line BL is connected to one end of the current path of the memory cell MC. The control gates of the memory cells MC0~MC63 are respectively connected to the word line WL (WL0~WL63), and the gates of the gate transistors S1 and S2 are connected to the selection gate lines SGS and SGD.

The range of a plurality of memory cells along a word line becomes a page for a unified unit of data reading and data writing. Further, the range of the plurality of NAND unit cells arranged along the direction of the word line constitutes a unit block BLK which is a unit for collectively deleting data. In FIG. 2, a plurality of unit blocks BLK0 to BLKm-1 sharing the bit line BL are arranged in the direction of the bit line BL to constitute the memory cell array 1. The word line WL and the selection gate lines SGS, SGD are driven by the column decoder 2a. The bit lines BL are connected to the sense amplifier circuit SA of the page buffer 3. The sense amplifier circuit SA detects the data of the memory cell MC selected by the bit line BL and the resource line WL.

Figure 3 is a diagram showing the threshold distribution of the memory cell MC when the data of 2 bits is written. Figure. In the present embodiment, the data of two bits is memorized in one memory cell MC. The threshold voltage Vt of all memory cells MC in the block becomes the lowest "E (deletion)" level due to block deletion. Thereafter, when the lower-level page is written, the writing of the threshold voltage to the "LM" level is performed for the memory cell of the lower-level page data "0". The "E" level and the "LM" level are subject to change due to the influence of the adjacent memory cells being written, and the threshold distribution amplitude is expanded. When the next upper page is written, the threshold distribution is further changed according to the upper page data, and four narrow threshold distributions corresponding to the data "11", "01", "00", and "10" are generated. "E", "A", "B", "C". In this case, the lowest deletion E level is used directly at the E level. The second lowest A level is produced by displacement from the E level. The B and C levels are generated by displacement from the LM level.

Figure 4 is a diagram showing the page writing sequence in a memory block. The "circle" is used to indicate that the lower level page is written as the "four corners" to indicate that the upper level page is different from the upper level page. The sub-pages and the upper-level pages of the character line WL which are different from each other are alternately written. The "circles" of the lower-level page and the numbers in the "four corners" of the parent page indicate the writing order. Furthermore, the number of word lines WL and the number of bit lines BL are not particularly limited.

For example, after the data is written to the lower level page of the word line WL0, the data is written to the lower level page of the word line WL1. Next, data is written to the upper page of the word line WL0. Then, data is written to the lower level page of the word line WL2, and data is written to the upper level page of the word line WL1. Thereafter, the writing of the lower-level page of the word line WLn (n is an integer of 3 or more) and the writing of the upper-level page of the word line WLn-1 are repeatedly performed.

Thus, the data is alternately written to the lower level page and the upper level page of the character line WL which are different from each other. Thereby, the writing of the upper cell page of the memory cell connected to the word line WLn is connected to the memory cell lower level page connected to the word line WLn+1 adjacent thereto and the memory cell connected to the word line WLn-1. Executed after the writing of the upper level page. Thereby, the threshold distribution of the memory cell can be suppressed to some extent due to the adjacent interference effect.

On the other hand, multi-level memory (MLC (Multi-Level Cell) In the case of a cell, the page below the word line WL is detected before the upper page of the word line WL is to be written. This action is called IDL (Internal Data Load). After referring to the status (E or LM) of the lower page by IDL, the data of the upper page can be written. However, the lower-level pages of the memory cell MC are sometimes affected by the writing of the upper-level pages of the memory cells adjacent to the two sides of the memory cell MC or the writing of the lower-level pages.

For example, attention is paid to the memory cell sub-level page connected to the word line WL1 shown in FIG. Between the writing of the lower-level page of the memory cell connected to the word line WL1 (the second action) and the writing of the upper-level page (the fifth action), the memory cell upper-level page connected to the word line WL0 is executed. The writing (the third action) and the writing of the lower-level page of the memory cell connected to the word line WL2 (the fourth action). Therefore, before the upper stage page of the memory cell connected to the word line WL1 is written, the lower level page of the memory cell connected to the word line WL1 is written by the upper page of the memory cell connected to the word line WL0 and The effect of writing to the lower level page of the memory cell connected to word line WL2.

In this case, the threshold distribution of the lower-level pages of the memory cells connected to the word line WL1 is expanded. As shown in Figure 3, the lower level page contains information on the E level and the LM level. Therefore, if the threshold distribution of the E level and the LM level is expanded, the sense amplifier circuit SA cannot accurately detect the E level and the LM level in the IDL.

5(A) to 5(D) are diagrams showing the adjacent interference effects of the lower-order pages of the plurality of memory cells MCn connected to the word line WLn. Before writing, the memory cell MCn is in the deleted state (E1) as shown in Fig. 5(A). That is, the data has not been written to the lower level page of the memory cell MCn. At this stage, data is written to the lower level page of the memory cell MCn-1 connected to the word line WLn-1 adjacent to the word line WLn. Therefore, the threshold distribution of the memory cell MCn is affected by the adjacent interference effect caused by the writing of the lower cell page of the memory cell MCn-1, and the state changes from the state of E1 to the state of E2. However, at this stage, since the lower level page of the memory cell MCn has not been written, the change of the threshold distribution of the memory cell MCn from E1 to E2 does not pose a problem.

Next, as shown in FIG. 5(B), the lower level page of the memory cell MCn is written. With this, memory The threshold distribution of the cell MCn is divided into the memory cell of the E2 level and the memory cell of the LM1 level. At this stage, the sub-pages (E2 and LM1) of the memory cell MCn are not affected by the adjacent interference.

Next, the upper page of the memory cell MCn-1 connected to the word line WLn-1 is written. As illustrated with reference to FIG. 3, the writing of the upper page includes writing from the E level to the E or A level, and writing from the LM level to the B or C level. In these write operations, the threshold voltage of the memory cell hardly changes when writing from the E level to the E level and writing from the LM level to the B level. On the other hand, when writing from the E level to the A level and writing from the LM level to the C level, the threshold voltage of the memory cell largely changes. Therefore, the memory cell MCn is subjected to the adjacent interference effect from the adjacent memory cells in which E is written to A in the plurality of memory cells MCn-1, and the adjacent memory cells written from C to C. Therefore, as shown in FIG. 5(C), the threshold distribution of the lower page of the memory cell MCn changes from E2 to E3, and from LM1 to LM2.

Next, the lower level page of the memory cell MCn+1 connected to the word line WLn+1 is written. The writing of the lower level page is written from the E level to the E or LM level. In the write operation, the threshold voltage of the memory cell hardly changes when writing from the E level to the E level. On the other hand, when writing from the E level to the LM level, the threshold voltage of the memory cell changes greatly. Therefore, the memory cell MCn is subjected to the adjacent interference effect from the contiguous memory cells of the plurality of memory cells MCn+1 written from the E level to the LM level. Therefore, as shown in FIG. 5(D), the threshold distribution of the lower page of the memory cell MCn changes from E3 to E4, and from LM2 to LM3. Thus, if the memory cell MCn is subjected to the adjacent interference effect from the adjacent memory cells MCn-1, MCn+1, the threshold distribution of the lower level page of the memory cell MCn is expanded as shown in FIG. 5(D).

Next, IDL is performed on the memory cell MCn. At this stage, as shown in FIG. 5(D), the threshold distribution of the memory cell MCn has been greatly expanded. The memory cell MC of the threshold voltage existence region Rvt can be a memory cell having a threshold voltage of the E level or a memory cell having a threshold voltage of the LM level according to the degree of the adjacent buffer effect received by the adjacent memory cell.

Thus, even if the IDL is executed in a state where the threshold distribution of the lower-level data has been expanded, there is a case where the sense amplifier circuit SA cannot accurately detect the lower-level data. Under the IDL The error of the data is different from the error in the normal data reading operation, and the correction using the ECC (Error Correcting Code) is not performed. Therefore, the error of the subordinate data in the IDL becomes a hard bit error, and there is a case where it is difficult to perform data correction. In this case, a read error is caused.

However, the inventors have determined that the displacement of the subordinate data of the memory cell MCn can also be written by the upper page of the memory cell MCn-1 (writing from E to A, writing from LM to C), and memory. The write of the lower level page of cell MCn+1 (generated from E to LM). Therefore, when the IDL of the memory cell MCn is used, the data of either or both of the memory cell MCn-1 and the memory cell MCn+1 can be detected, and the memory cell MCn-1 and/or the memory cell MCn+1 are detected. The data is corrected, and the detection data of the lower level page of the character line WLn is corrected.

For example, in IDL, by setting the voltage of the word line WLn to VLM1, the sense amplifier SA can identify the memory cell of the E2 level and the memory cell of the LM1~LM3 level. By setting the voltage of the word line WLn to VLM2, the sense amplifier SA can identify the memory cell of the E3 level and the memory cell of the LM2, LM3 level. Further, by setting the voltage of the word line WLn to VLM3, the sense amplifier SA can identify the memory cell of the E4 level and the memory cell of the LM3 level.

Therefore, in the memory of the present embodiment, the sense amplifier circuit SA repeats the plurality of detection operations when the data of the memory cell MCn connected to the word line WLn is detected in the IDL of the write operation, and the latch is plural. Test results. Further, the sequence control circuit 7 (see Fig. 1) as the control unit is based on the memory cells MCn-1, MCn+1 connected to the word lines WLn-1, WLn+1 adjacent to both sides of the word line WLn. Data, select any one of the plurality of test results.

Next, the data detecting operation of the memory cell MCn at the time of IDL will be described more specifically with reference to FIGS. 6(A) to 6(C).

6(A) to 6(C) are timing charts showing the IDL operation of the memory of the first embodiment. 6(A) to 6(C) show that it is performed immediately before the upper page of the word line WLn is written. Timing diagram of the IDL action.

(Detection of data connected to WLn-1 memory cell MCn-1)

At time t0~t1, the data of the plurality of memory cells MCn-1 connected to the word line WLn-1 is detected. The memory cell MCn-1 upper level page is also written before the upper stage page of the memory cell MCn is to be written. Therefore, the threshold voltage of the memory cell MCn-1 can obtain any of E, A, B, and C. In order to identify the E, A, B, and C levels, the data level of the memory cell MCn-1 is performed while changing the voltage level of the word line WLn-1 to VA, VB, and VC. As shown in Figure 3, the VA is at the voltage level between the E level and the A level, the VB is at the voltage level between the A level and the B level, and the VC is at the B level and the C level. The voltage level between them.

For example, when the voltage of the word line WLn-1 is VA, the memory cell MCn-1 of the E level is turned on, but the memory cell MCn-1 of the other A, B, and C levels remains disconnected. status. Therefore, when the voltage of the word line WLn-1 is VA, the memory cells of the E level in the plurality of memory cells MCn-1 can be distinguished from the memory cells of the A, B, and C levels. Similarly, when the voltage of the word line WLn-1 is VB, the memory cells of the A level in the memory cell MCn-1 of the A, B, and C levels and the memory cells of the B and C levels can be used. Make a distinction. Further, when the voltage of the word line WLn-1 is VC, the memory cells of the B level in the memory cell MCn-1 of the B and C levels can be distinguished from the memory cells of the C level.

Thereby, it is detected which threshold level of each of the memory cells MCn-1 is E, A, B, and C. That is, the sense amplifier SA can detect the respective 2-bit data of the plurality of memory cells MCn-1. The data of the memory cell MCn-1 is saved (latched) to the sense amplifier SA or the page buffer PB.

Furthermore, as described above, when the adjacent memory cell MCn-1 is at the A and C levels, and the adjacent memory cell MCn+1 is the LM level, the memory cell MCn is subjected to the adjacent interference effect. Therefore, as long as the adjacent memory cells MCn-1 and MCn+1 can be judged to be A and C levels Or which of the E and B levels is used to determine whether the memory cell MCn is subject to the adjacent interference effect. Therefore, in order to reduce the adjacent buffering effect, the sequence control circuit 7 can also compress it into a 1-bit data indicating which of the A, C, or E, B levels. Thereby, the data capacity that the sense amplifier SA or the page buffer PB should hold can be reduced.

Furthermore, at this time, since the other word lines WL0 to WLn-2 and WLn to WL63 are in the non-selected state, the high level voltage VREAD is maintained. Thereby, the memory cell MCn-1 is connected between the bit line BL and the cell source CELSRC with a low resistance.

(Detection of data connected to WLn+1 memory cell MCn+1)

At time points t1 to t2, data of a plurality of memory cells MCn+1 connected to the word line WLn+1 are detected. Before the upper stage page of the memory cell MCn is written, the memory cell MCn+1 lower level page is also written, and the memory cell MCn+1 upper level page has not been written. Therefore, the threshold voltage of the memory cell MCn+1 can obtain any of E and LM. To identify the threshold levels of E and LM, the data detection of the memory cell MCn+1 is performed by setting the voltage level of the word line WLn+1 to VLM. As shown in FIG. 3, the VLM is at a voltage level between the E level and the LM level, and is a read voltage between the E level and the LM level. Furthermore, VLM1~3 of FIG. 5 is an example of VLM.

For example, when the voltage of the word line WLn+1 is VLM, the memory cell MCn+1 of the E level is turned on, but the memory cell MCn+1 of the other LM level remains in the off state. Therefore, when the voltage of the word line WLn+1 is VLM, the memory cell of the E level in the memory cell MCn+1 is distinguished from the memory cell of the LM level.

Thereby, it is detected which threshold voltage of each memory cell MCn+1 is E and LM. That is, the sense amplifier SA can detect the data of the respective lower level pages of the plurality of memory cells MCn+1. The data of the memory cell MCn+1 is also saved (latched) to the sense amplifier SA or the page buffer PB.

Furthermore, at this time, since the other word lines WL0 to WLn and WLn+2 to WL63 are in the non-selected state, they are maintained at the high level voltage VREAD. Thereby, the memory cell is low in resistance MCn+1 is connected between the bit line BL and the cell source CELSRC.

(Data detection (IDL) of memory cell MCn connected to WLn)

At time t2 to t3, the data of the plurality of memory cells MCn connected to the word line WLn is detected. At this time, since the system is about to be written before the upper stage page of the memory cell MCn, the lower level page of the memory cell MCn is also written. Therefore, the threshold voltage of the memory cell MCn can obtain any of E and LM.

However, as described above, the lower level page of the memory cell MCn is written by the upper page of the memory cell MCn-1 (writing from E to A (hereinafter, also referred to as "WRITE (EA)"), from LM to C Write (hereinafter, also referred to as "WRITE (LM-C)"), and write of the lower-level page of the memory cell MCn+1 (write from E to LM (hereinafter, also referred to as "WRITE (E-) LM)") is subject to the adjacent interference effect. Therefore, as shown in Fig. 5(D), the threshold distribution spread of the lower level page of the memory cell MCn is estimated.

The memory of the present embodiment repeats the plurality of detection operations for detecting the lower level data of the memory cell MCn. At this time, the voltage of the word line WLn is maintained at the fixed voltage VLM. For example, at time t2-1, the sense amplifier SA detects the data of the memory cell MCn (first detection). Next, at time t2-2, the sense amplifier SA detects the data of the memory cell MCn again (second detection). Next, at time t2-3, the sense amplifier SA detects the data of the memory cell MCn again (third detection). The results of the first to third detections are stored in the sense amplifier SA or the page buffer PB.

In the NAND type flash memory, the sense amplifier SA detects the data of the memory cell MC by flowing a current (charge) from the sensing node to the memory cell MC via the bit line BL. The fixed unit current corresponding to the logic of the memory cell MCn and the fixed voltage VLM of the word line WLn. Therefore, the sense amplifier SA can recognize the logic of the data of the memory cell MC by detecting the voltage change of the sensing node.

As in the present embodiment, by detecting the data of the memory cell MCn at different timings (t2-1 to t2-3), the voltage of the sensing node becomes lower at the second detection time t2-2 than at the first detection time t2-1. ,to At the third detection, t2-3 is lower than t2-2 at the second detection. For example, during t2~t2-1, the self-sensing node releases the charge Id1. During t2~t2-2, the self-sensing node releases the charge Id2 (>Id1). During t2~t2-3, the self-sensing node releases the charge Id3 (>Id2). Therefore, the voltage of the sensing node is different at the first to third detections. This case is substantially equivalent to changing the voltage of the word line WLn to detect the data of the memory cell MCn. For example, the first detection may be associated with the detection using VLM1, the second detection may be associated with the detection using VLM2, and the third detection may be associated with the detection using VLM3. That is, in the present embodiment, the IDL in consideration of the adjacent interference effect is performed by changing the data detection timing instead of changing the set voltage of the word line WLn.

As described above, the adjacent interference effect of the lower level page of the memory cell MCn is due to the writing of the upper level data of the memory cell MCn-1 (WRITE (EA), WRITE (LM-C)), and the lower level of the memory cell MCn+1. The page is written (WRITE (E-LM). These adjacent interference effects are predictable to some extent, as explained with reference to FIG. 5(D), by changing the set voltage of the word line WLn to VLM1~VLM3 can recognize the memory cell of the E level and the memory cell of the LM level in consideration of the adjacent interference effect. Similarly, the detection timing of the sense amplifier SA is changed in a manner corresponding to VLM1 to VLM3 (t2- 1~t2-3), the memory cell of the E level and the memory cell of the LM level can be identified by considering the adjacent interference effect.

The sequence control circuit 7 selects one of the first and second detection results stored in the sense amplifier SA or the page buffer PB based on the data of the adjacent memory cells MCn-1 and MCn+1.

For example, in a bit line BL (row), when the memory cell MCn-1 stores the data of the A (or C) level, and the memory cell MCn+1 stores the data of the LM level, the memory cell MCn is self- Both of the memory cells MCn-1 and MCn+1 are subjected to the adjacent interference effect, and can be determined to belong to the threshold distribution of E4 or LM3 of FIG. 5(D). Therefore, the sequence control circuit 7 selects and adopts the first detection result corresponding to the VLM 3.

For example, in another bit line BL (row), the memory cell MCn-1 stores the A (or C) level. When the memory cell MCn+1 stores the E-level data, the memory cell MCn is subjected to the adjacent interference effect from the memory cell MCn-1, and can be determined as belonging to the threshold distribution of E3 or LM2 of FIG. 5(D). Therefore, the sequence control circuit 7 selects and adopts the second detection result corresponding to the VLM 2.

For example, in another bit line BL (row), when the memory cell MCn-1 stores the E (or B) level data, and the memory cell MCn+1 stores the LM level data, the memory cell MCn is self-contained. The memory cell MCn+1 is subjected to the adjacent interference effect and can be determined to belong to the threshold distribution of E3 or LM2 of FIG. 5(D). Therefore, the sequence control circuit 7 selects and adopts the second detection result corresponding to the VLM 2.

For example, in a further line BL (row), when the memory cell MCn-1 stores the E (or B) level data, and the memory cell MCn+1 stores the E level data, the memory cell MCn The memory cells MCn-1 and MCn+1 are not subjected to the adjacent interference effect, and can be determined as belonging to the threshold distribution of E2 or LM1 of FIG. 5(D). Therefore, the sequence control circuit 7 selects and adopts the third detection result corresponding to the VLM 1.

In NAND flash memory, a multi-value technique that uses data in a memory cell memory of more than two bits is widely used to reduce bit cost. Moreover, in order to reduce the size of the wafer, the miniaturization of the memory cells is progressing. Under such conditions, the extension of the threshold distribution caused by inter-cell interference (adjacent interference effects) can be ignored. The adjacent interference effect is a phenomenon in which the threshold voltage of the memory cell in which the data has been written is displaced due to the writing operation to the data of the adjacent memory cell. By the adjacent interference effect, the threshold voltage distribution of the memory cell is expanded, and the reliability of the data detected in the sense amplifier is reduced.

On the other hand, according to the present embodiment, in the IDL, the sense amplifier SA detects the data of the memory cell connected to the word lines WLn-1 and WLn+1 adjacent to both sides of the word line WLn which is the target of the IDL. Further, the data of the memory cell MCn connected to the word line WLn is repeatedly detected at different timings. Moreover, the sequence control circuit 7 selects a plurality of detection results of the memory cell MCn based on the data of the adjacent memory cells MCn-1, MCn+1. Any one. The sequence control circuit 7 performs this selection action for each line. Thereby, the sequence control circuit 7 can take the detection result in consideration of the adjacent interference effect from the adjacent memory cells MCn-1, MCn+1. Thereby, the memory of this embodiment can accurately detect data in the IDL.

In the present embodiment, the sense amplifier SA detects data of all adjacent memory cells MCn-1 and adjacent memory cells MCn+1. Therefore, the sequence control circuit 7 can select based on the adjacent interference effects (the adjacent interference effects of WRITE (EA), WRITE (LM-C), and WRITE (E-LM)) in the lower page of the memory cell MCn. The detection result of memory cell MCn.

Furthermore, in the present embodiment, the sense amplifier SA detects the data of the memory cell MCn three times at different timings. However, the sense amplifier SA can also detect the data of the memory cell MCn twice in different timings. In this case, the memory may select and employ the detection result in consideration of the adjacent interference effect of either or both of the memory cells MCn-1 or MCn+1.

For example, Fig. 12(A) shows a table of selection results of selection of three detection results from the memory cell MCn. Example 1 shown in Fig. 12(A) is an example in which the adjacent memory cell MCn-1 is at the E or B level and the adjacent memory cell MCn+1 is at the E level. In this case, the memory cell MCn is not subjected to the adjacent interference effect from the adjacent memory cells MCn-1, MCn+1. Therefore, the memory selects Sense1 detected at t2-1. Example 2 is an example in which the adjacent memory cell MCn-1 is at the E or B level, and the adjacent memory cell MCn+1 is the LM level. In this case, although the memory cell MCn is not subjected to the adjacent interference effect from the adjacent memory cell MCn-1, it is subject to the adjacent interference effect from the adjacent memory cell MCn+1. Therefore, the memory selects Sense2 detected at t2-2. Example 3 is an example in which the adjacent memory cell MCn-1 is at the A or C level and the adjacent memory cell MCn+1 is at the E level. In this case, although the memory cell MCn is not subjected to the adjacent interference effect from the adjacent memory cell MCn+1, the adjacent memory cell MCn-1 is subject to the adjacent interference effect. Therefore, the memory selects Sense2 detected at t2-2. Further, Example 4 is an example in which the adjacent memory cell MCn-1 is at the A or C level and the adjacent memory cell MCn+1 is the LM level. In this case, the memory cell MCn is self-contiguous Both memory cells MCn-1 and MCn+1 are subject to adjacent interference effects. Therefore, the memory selects Sense3 detected at t2-3.

Fig. 12(B) is a table showing selection results of selection of two detection results from the memory cell MCn. When the detection result is two (for example, in the case of Sense1 and Sense2), the memory selects either one of Sense1 and Sense2 depending on the adjacent interference effect.

In the example 11 shown in Fig. 12(B), as in the case of the example 1, the memory cell MCn is not subjected to the adjacent interference effect from the adjacent memory cells MCn-1, MCn+1. Therefore, the memory selects Sense1 detected at t2-1. Example 14 In the same manner as in Example 4, the memory cell MCn was subjected to the adjacent interference effect from both adjacent memory cells MCn-1 and MCn+1. Therefore, the memory selects Sense2 detected at t2-2.

Here, in the example 12, as in the case of the example 2, the memory cell MCn is not subjected to the adjacent interference effect from the adjacent memory cell MCn-1, but is subjected to the adjacent interference effect from the adjacent memory cell MCn+1. Example 13 In the same manner as in Example 3, although the memory cell MCn was not subjected to the adjacent interference effect from the adjacent memory cell MCn+1, the adjacent memory cell MCn-1 was subjected to the adjacent interference effect. Therefore, in Examples 2 and 3, the memory cell MCn is only subjected to a contiguous interference effect. Therefore, in this case, Sense1 can be selected without considering the adjacent interference effect as in the selection result Result1. Alternatively, Sense2 may be selected in consideration of the adjacent interference effect as in the selection Result2.

(Variation 1)

7(A) to 7(C) are timing charts showing the IDL operation of the memory of the first modification of the first embodiment. According to the first modification, the voltage of the word line WLn is step-up-up to VWLn1, VWLn2, and VWLn3 at each of the detection timings t2-1 to t2-3. The other operations of the first modification can be the same as the operations corresponding to the first embodiment.

In the first modification, the sense amplifier SA at the IDL detects the data of the memory cell connected to the word lines WLn-1 and WLn+1 adjacent to both sides of the word line WLn which is the target of the IDL, and further changes the word. The voltage of the WLn of the element line detects the memory cell MCn multiple times data. As long as the plurality of detections in t2-1 to t2-3 correspond to the detection obtained when the voltage of the word line WLn is set to VWLn1 to VWLn3, the voltage of the word line WLn can be detected and detected as in the first modification. The timing t2-1~t2-3 changes in a corresponding manner.

(Variation 2)

8(A) to 8(C) are timing charts showing the IDL operation of the memory of the second modification of the first embodiment. When the voltage of the word line WLn is changed, the voltages of the adjacent bit lines WLn+1 and WLn-1 may be changed as shown by t2 to t3 in FIGS. 8(A) to 8(C). When the adjacent interference effect is utilized, the voltage of the word line WLn fluctuates with the change of the voltage of the adjacent word lines WLn+1 and WLn-1. In this manner, even if the voltages of the adjacent word lines WLn+1 and WLn-1 are changed so as to correspond to the detection timings t2-1 to t2-3, the voltage of the word line WLn can be raised in the same manner as in the first modification. Up to VWLn1, VWLn2, VWLn3. Further, since t3 to t3, for example, VLM is applied to the word line WLn, the voltage of the word line WLn is fixedly displayed as VLM in t2 to t3 of FIG. However, in actuality, the voltage of the word line WLn is subjected to the adjacent interference effect from the voltages of the adjacent word lines WLn+1 and WLn-1, and operates in the same manner as the word line WLn of t2 to t3 of Fig. 7 .

Of course, the operation of the adjacent word line WLn+1 and the operation of the adjacent word line WLn-1 may be exchanged to change the voltage of the word line WLn.

(Second embodiment)

9(A) to 9(C) are timing charts showing the IDL operation of the memory of the second embodiment. In the second embodiment, at t0 to t1, the data detection of the memory cell MCn-1 is performed by setting the voltage level of the word line WLn-1 to VC. The data detection when the voltage level of the word line WLn-1 is VA and VB is not performed. Therefore, in the second embodiment, the memory cells at the E, A, and B levels in the memory cell MCn-1 are distinguished from the memory cells at the C level. That is, the memory cells at the E, A, and B levels in the memory cell MCn-1 are not distinguished. The other operations of the second embodiment can be the same as the operations corresponding to the first embodiment.

Thus, due to memory cell MCn-1, the memory cell is not in the E, A and B levels. Therefore, the memory cell MCn-1 in the upper level of the memory cell MCn is not considered to be affected by the adjacent interference effect (the adjacent interference effect caused by WRITE (EA), WRITE (LM-C) and WRITE (E-LM)). The adjacent interference effect caused by the WRITE (EA) of the page. That is, the sequence control circuit 7 selects the detection result of the memory cell MCn regardless of the adjacent interference effect caused by WRITE (E-A).

However, the sequence control circuit 7 can select the detection result of the memory cell MCn on the basis of the adjacent interference effects caused by other WRITE (LM-C) and WRITE (E-LM). Therefore, even if the threshold distribution of the memory cell MCn is repeated due to the adjacent interference effect, the memory of the second embodiment can detect the data to some extent accurately in the IDL.

(Third embodiment)

10(A) to 10(C) are timing charts showing the IDL operation of the memory of the third embodiment. In the third embodiment, data detection of the memory cell MCn-1 is not performed at t0 to t1. That is, the data of the memory cell MCn-1 is not distinguished.

Since the data of the memory cell MCn-1 is not distinguished, the adjacent interference effects (WRITE (EA), WRITE (LM-C) and WRITE (E-LM) caused by the adjacent pages of the memory cell MCn are not considered. The adjacent interference effects caused by WRITE (EA) and WRITE (LM-C) of the memory cell MCn-1 upper page. That is, the sequence control circuit 7 selects the detection result of the memory cell MCn regardless of the adjacent interference effect caused by WRITE (E-A) and WRITE (LM-C).

As described above, in the third embodiment, since the adjacent interference effect caused by the writing of the upper page of the memory cell MCn-1 is not considered, the detection operation of t2 to t3 can be performed twice by t2-1 and t2-2. By setting the detection action twice, the verification read time can be shortened. The other operations of the third embodiment can be basically the same as the operations corresponding to the first embodiment.

In the third embodiment, the sequence control circuit 7 can select the detection result of the memory cell MCn in consideration of the adjacent interference effect caused by the WRITE (E-LM) of the memory cell MCn+1. Therefore, even if the threshold distribution of the memory cell MCn is repeated due to the adjacent interference effect, The memory of the third embodiment can also detect data to some extent accurately in the IDL.

(Fourth embodiment)

11(A) to 11(C) are timing charts showing the IDL operation of the memory of the fourth embodiment. In the fourth embodiment, data detection of the memory cell MCn+1 is not performed at t1 to t2. That is, the data of the memory cell MCn+1 is not detected.

Since the data of the memory cell MCn+1 is not detected, the adjacent interference effects (WRITE (EA), WRITE (LM-C) and WRITE (E-LM) caused by the adjacent pages of the memory cell MCn are not considered. The adjacent interference effect caused by WRITE (E-LM) of the memory cell MCn+1 lower level page. That is, the sequence control circuit 7 selects the detection result of the memory cell MCn regardless of the adjacent interference effect caused by WRITE (E-LM).

As described above, in the fourth embodiment, since the adjacent interference effect caused by the writing of the upper page of the memory cell MCn+1 is not considered, the detection operation of t2 to t3 can be performed twice by t2-1 and t2-2. By setting the detection action twice, the verification read time can be shortened. The other operations of the fourth embodiment can be basically the same as the operations corresponding to the first embodiment.

In the fourth embodiment, the sequence control circuit 7 can select the detection result of the memory cell MCn in consideration of the adjacent interference effect caused by the WRITE (E-A) and the WRITE (LM-C) of the memory cell MCn-1. Therefore, even if the threshold distribution of the memory cell MCn is repeated due to the adjacent interference effect, the memory of the fourth embodiment can detect the data to some extent accurately in the IDL.

The third and fourth embodiments can be combined with the above-described modification 1 or modification 2.

The configuration of the memory cell array 111 is described in, for example, U.S. Patent Application Serial No. 12/407,403, filed on Jan. 19, 2009. In addition, U.S. Patent Application Serial No. 12/406,524, filed on Mar. U.S. Patent Application Serial No. 12/679,991, filed on Jan. 23, 2009, and U.S. Patent Application Serial No. Application No. 12/532,030. The entire contents of these patent applications are hereby incorporated by reference.

The embodiments of the present invention have been described, but are not intended to limit the scope of the present invention. The embodiments may be embodied in a variety of other forms, and various omissions, substitutions and changes may be made without departing from the scope of the invention. The scope of the invention and the scope of the invention are intended to be included within the scope of the invention and the scope of the invention.

VA‧‧‧voltage level

VB‧‧‧ voltage level

VC‧‧‧ voltage level

VLM‧‧‧ voltage level

VREAD‧‧‧ high level voltage

Claims (10)

A semiconductor memory device comprising: a memory cell array having a plurality of memory cells, wherein the memory cells can memorize data having a plurality of bits of a lower page and a higher page; and a plurality of word lines connected to the plurality of bits a memory cell; a plurality of bit lines connected to one end of the current path of the plurality of memory cells; and a sense amplifier portion detecting the pair of word lines WLn-1 connected to the plurality of word lines (n is an integer) the data of the upper page of the memory cell is written, and then after detecting the data of the lower-level page written to the memory cell connected to the word line WLn+1, the detection pair is connected to the character The memory of the line WLn is written to the data of the lower-level page; and when the data of the memory cell connected to the word line WLn is detected, the plurality of detections are repeated to obtain a plurality of detection results. The semiconductor memory device of claim 1, further comprising a sequence control circuit that detects the data of the memory cells connected to the word line WLn at a plurality of times and selects any one of the plurality of detection results. The semiconductor memory device of claim 2, wherein the selection of any one of the plurality of detection results of the data of the memory cell connected to the word line WLn by the sequence control circuit is based on the connection to the character The detection data of the adjacent memory cells of the line WLn-1 and the above WLn+1 are performed. The semiconductor memory device of claim 3, wherein the selection of any one of the plurality of detection results of the data by the sequence control circuit is performed on each of the bit lines. The semiconductor memory device of claim 1, wherein the plurality of detections are different timings The first detection (t2-1), the second detection (t2-2>t2-1), and the third detection (t2-3>t2-2) are performed by the first, second, and third detections, respectively. Detecting the voltage change of the sense node of the sense amplifier. The semiconductor memory device of claim 1, wherein when the data of the lower-level page of the memory cell connected to the word line WLn is detected, the voltage of the word line WLn is set to be fixed. The semiconductor memory device of claim 6, wherein the voltage applied to the word line WLn+1 is detected when detecting data of the lower-level page written to the memory cell connected to the word line WLn+1, and then The voltage applied to the word line WLn is the same when the data of the lower-level page written to the memory cell of the word line WLn is detected. The semiconductor memory device of claim 1, wherein when the lower page of the memory cell connected to the word line WLn is detected, the voltage of the word line WLn is changed to a voltage corresponding to each of the plurality of detection operations. The semiconductor memory device of claim 1, wherein when detecting the lower-level page of the memory cell connected to the word line WLn, the voltage of the word line WLn+1 or WLn-1 is set to a plurality of detection operations. The voltage corresponding to each. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells, wherein the memory cells can memorize data having a plurality of bits of a lower page and a higher page; and a plurality of word lines connected to the plurality of bits a memory cell; a plurality of bit lines connected to one of the current paths of the plurality of memory cells; and a sense amplifier portion for detecting the pair of word lines WLn+ connected to the plurality of word lines After the data of the above-mentioned lower page is written by the memory cell, the data of the lower-level page written to the memory cell connected to the word line WLn is detected; And detecting a plurality of times of detecting the data of the memory cell connected to the word line WLn; detecting a voltage of the lower page connected to the memory cell of the word line WLn, and subsequently detecting the pair connected to the word The voltage of the data of the above-mentioned lower page written by the memory cell of the source line WLn is set to the same fixed voltage.