TWI601014B - Computer system capable of controlling conflict during accessing memory - Google Patents

Description

Computer system for memory access conflict control

The present invention relates to a computer system, and more particularly to a computer system having memory access conflict control.

In a computer system, the Baseboard Management Controller (BMC) manages the operational status of the entire server system, such as temperature, voltage, fans, power supplies, and chassis intrusions. The baseboard management controller provides functions such as server system autonomous monitoring, event recording, and error recovery, and is a very important management component in the server system.

Based on the cost control and performance optimization design concept, the newly developed workstation platform is gradually no longer adopting the substrate management controller as the control signal communication, but gradually using the Platform Controller Hub. Instead of the baseboard management controller, it controls the function of signal communication. However, in order to allow a limited number of transmission path or transmission path of the platform path controller, it can be efficiently provided to the central processing unit for transmission communication with other components, and often there are multiple components sharing one transmission part or transmission path. Settings, which in turn make the platform path controller vulnerable to access violations.

The present invention provides a computer system with memory access conflict control whereby a platform path controller has an access violation problem.

The computer system with memory access conflict control disclosed in the present invention has a first system control bus main controller (first SMBUS main controller) and a second system control bus main controller (second SMBUS main controller) ), controller and selector. The first SMBUS master controller is used for communication between the input and output busses. The second SMBUS host controller is used to monitor the system hardware program. The controller is coupled to the first SMBUS main controller, and when the first SMBUS main controller and the second SMBUS main controller both require reading and writing of the memory, the controller outputs a control signal. The selector is coupled to the controller, the first SMBUS master controller, and the second SMBUS master controller. The selector receives the control signal and selectively switches the first SMBUS main controller or the second SMBUS main controller to read and write the memory via the transmission interface according to the control signal. When the control signal indicates that the selector selects to read and write the memory by the first SMBUS main controller, and the first SMBUS main controller reads and writes the memory, the controller receives the end signal output by the first SMBUS main controller, and at least According to the end signal, a control signal is output to instruct the selector to switch the second SMBUS main controller to read and write the memory via the transmission interface.

According to the computer system with memory access conflict control disclosed in the above, the controller generates a control signal to the selector when the first SMBUS main controller and the second SMBUS main controller have an access conflict, so that the selector According to the control signal, the first SMBUS main controller is turned on to the transmission interface, or the second SMBUS main controller is turned on to the transmission interface, thereby solving the problem of the access conflict between the first SMBUS main controller and the second SMBUS main controller. .

The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a functional block diagram of a computer system according to an embodiment of the invention. As shown in FIG. 1 , the computer system 10 has a first system control bus (SMBUS) main controller 11 , a second system control bus (SMBUS) main controller 12 , and a controller 13 . The selector 14, the transmission interface 15, and the memory 16.

The first system controls the bus master controller 11, hereinafter referred to as the first SMBUS master controller 11, such as a Platform Controller Hub, a Southbridge wafer, a Northbridge wafer, or other suitable components within the computer system 10. The first SMBUS main controller 11 is used for communication between the input and output bus bars. In other words, the first SMBUS main controller 11 is electrically connected to a central processing unit (CPU) on the computer system 10 for controlling The central processor communicates signals to other components.

The second system controls the bus master controller 12, hereinafter referred to as the second SMBUS master controller 12, such as a hardware monitor or other suitable component. The second SMBUS main controller 12 is used for monitoring the system hardware program, such as monitoring the temperature of the fan, the display card, the temperature of the hard disk, the clock, the power or other hardware in the computer system 10.

The controller 13 is, for example, a Complex Programmable Logic Device (CPLD). The controller 13 is coupled to the first SMBUS main controller 11, the selector 14, and the transmission interface 15. In one embodiment, the first SMBUS main controller 11 has a general purpose input/output (General Purpose I/O) terminal, and the controller 13 is coupled to the general purpose input and output of the first SMBUS main controller 11.

The selector 14 has, for example, a first input, a second input, a control and an output. The first input end of the selector 14 is electrically connected to the first SMBUS main controller 11, and the second input end of the selector 14 is electrically connected to the second SMBUS main controller 12. The first SMBUS main controller 11 and the second SMBUS main controller 12 are electrically connected to the transmission interface 15 via the selector 14. In one embodiment, the first SMBUS main controller 11 and the second SMBUS main controller 12 have terminals with a system control bus (SMBUS) as a transmission specification, a selector 14 and a first SMBUS main controller. 11 is controlled by the system to control the busbar electrical connection, and the selector 14 and the second SMBUS main controller 12 are similarly connected by the system control bus. The control terminal of the selector 14 is electrically connected to the controller 13, and the output terminal is electrically connected to the transmission interface 15. In one embodiment, the transmission interface 15 is the transmission interface of the output of the selector 14, and the selector 14 is electrically coupled to the memory 16 via the transmission interface 15.

In a state in which the computer system 10 is in operation, when both the first SMBUS main controller 11 and the second SMBUS main controller 12 require reading and writing of the memory 16 through the transmission interface 15, the controller 13 outputs a control signal to the selector 14. In one embodiment, the controller 13 detects the SMBUS connected to the first SMBUS main controller 11 and the second SMBUS main controller 12 and the selector 14 to determine the first SMBUS main controller 11 and the second SMBUS main controller 12 Whether to read and write memory 16 is required. In another embodiment, the controller 13 can also notify the selector 14 that the first SMBUS main controller 11 and the second SMBUS main controller 12 are required to read and write the memory 16 . In other words, the controller 13 generates a control signal when an access violation occurs in the first SMBUS main controller 11 and the second SMBUS main controller 12.

The selector 14 receives the control signal output by the controller 13 and selectively switches one of the first SMBUS main controller 11 and the second SMBUS main controller 12 according to the control signal to read and write the memory 16 via the transmission interface 15. That is, the selector 14 determines whether the first SMBUS main controller 11 reads and writes the memory 16 or the second SMBUS main controller 12 reads and writes the memory 16 according to the control signal output from the controller 13.

When the control signal indicates that the selector 14 selects to read and write the memory 16 by the first SMBUS main controller 11, the first SMBUS main controller 11 is turned on to the memory 16 through the transmission interface 15 to read and write the memory 16. When the first SMBUS main controller 11 reads and writes the memory 16, the first SMBUS main controller 11 outputs an end signal to the controller 13 with a general-purpose input/output terminal (General Purpose I/O) to inform the controller 13 to read. Write the completed message. The controller 13 outputs a control signal according to the end signal output by the first SMBUS main controller 11 to instruct the selector 14 to switch the second SMBUS main controller 12 to read and write the memory 16 via the transmission interface 15.

In one embodiment, when the controller 13 receives the end signal output by the first SMBUS main controller, the controller 13 reads the signal on the transmission interface 15 to detect whether the transmission interface 15 is idle. When the controller 13 judges that the transmission interface 15 is idle, the control signal is output, and the control signal is output, so that the selector 14 switches to the second SMBUS main controller 12 to read and write the memory 16. In other words, the controller 13 outputs a control signal according to whether the transmission interface 15 is idle or not, according to the end signal output by the first SMBUS main controller 11.

In a practical example, the transmission interface 15 has at least a data transmission line and a clock signal line. The data transmission line is used to transmit a data signal, such as the data of the memory 16 to the first SMBUS main controller 11. The clock signal line is used to transmit the clock signal, so that the data transmission line transmits the data according to the clock signal. In this embodiment, the controller 13 can determine whether the transmission interface 15 is idle according to the voltage level of the data signal and the clock signal.

Next, please refer to FIG. 2. FIG. 2 is a functional block diagram of a computer system according to another embodiment of the present invention. As shown in FIG. 2, the computer system 20 has a first SMBUS main controller 21, a second SMBUS main controller 22, a controller 23, a selector 24, a transmission interface 25, and a memory 26. The first SMBUS host controller 21 is, for example, a Platform Controller Hub, a South Bridge chip, a North Bridge chip, or other suitable component within the computer system 20 for controlling communication between the input and output busses of the central processing unit. The second SMBUS host controller 22 is, for example, a hardware monitor or other suitable component for monitoring hardware or hardware information within the computer system 20.

The controller 23 is, for example, a complex programmable logic device electrically connected to the first SMBUS main controller 21, the selector 24, and the transmission interface 25. The selector 24 has a first switch 241 and a second switch 242. The first switch 241 is disposed on the transmission path of the first SMBUS main controller 21 and the memory 26, and the second switch 242 is disposed on the transmission path of the second SMBUS main controller 22 and the memory 26. The first switch 241 and the second switch 242 are turned on according to the control of the controller 23, so that the first SMBUS main controller 21 is electrically connected to the memory 26 through the transmission interface 25, or the second SMBUS main controller 22 is transmitted through the transmission interface 25. The memory 26 is turned on to read and write the memory 26.

In one embodiment, the first SMBUS main controller 21 and the second SMBUS main controller 22 have terminals with a system control bus (SMBUS) as a transmission specification, a first switch 241 and a first SMBUS main control. The controller 21 is electrically connected by a system control bus, and the second switch 242 and the second SMBUS main controller 22 are similarly connected by a system control bus. In one embodiment, the transmission interface 25 is the transmission interface of the output of the selector 24, and the selector 24 is electrically coupled to the memory 26 via the transmission interface 25.

In one embodiment, the first switch 241 is preset to be conductive and the second switch 242 is preset to be non-conductive. In other words, in the operation of the computer system 20, when the second SMBUS main controller 22 does not require the read/write memory 26, the first SMBUS main controller 21 can read and write the memory 26 through the transmission interface 25 at any time. When the second SMBUS main controller 22 requests to read and write the memory 26, the first SMBUS main controller 21 also requests the read/write memory 26. At this time, the first SMBUS main controller 21 and the second SMBUS main controller 22 have an access violation. The controller 23 outputs a control signal to the first switch 241 and the second switch 242 to control whether the first switch 241 and the second switch 242 are turned on or off to disassemble the first SMBUS main controller 21 and the second SMBUS main controller 22 The requirement to read and write memory 26.

In this embodiment, the controller 23 outputs a control signal to indicate that the first switch 241 is switched to be on, and controls the second switch 242 to switch to non-conduction, so that the first SMBUS main controller 21 reads and writes the memory through the transmission interface. . When the first SMBUS main controller 21 reads and writes the memory 26, the controller 23 receives the end signal from the general-purpose input/output terminal that the first SMBUS main controller 21 notifies the completion of reading and writing. The controller 23 reads the data transmission line and the pulse signal line on the transmission interface 25 according to the end signal output by the first SMBUS main controller 21, and determines whether the transmission interface 25 is idle according to the voltage level of the data signal and the clock signal.

When the controller 23 judges that the transmission interface 25 is idle, the controller 23 outputs a control signal to control the first switch 241 to switch to non-conduction, and to control the second switch 242 to switch to conduction. When the second switch 242 is turned on, the second SMBUS main controller 22 can read and write the memory 26 through the transmission interface 25.

In summary, the embodiment of the present invention provides a computer system with memory access conflict control. The controller controls the selection by using a control signal when an access conflict occurs between the first SMBUS main controller and the second SMBUS main controller. The first SMBUS main controller and the second SMBUS main controller can be read and written to the memory through the selector and the transmission interface to read and write data, thereby solving the first SMBUS main controller and the second SMBUS main control. An issue with an access violation.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

10, 20‧‧‧ computer system
11, 21‧‧‧ First SMBUS main controller
12, 22‧‧‧Second SMBUS master controller
13, 23‧‧ ‧ controller
14, 24‧‧‧Selector
15, 25‧‧‧Transport interface
16, 26‧‧‧ memory
241‧‧‧First switch
242‧‧‧Second switch

1 is a functional block diagram of a computer system according to an embodiment of the invention. 2 is a functional block diagram of a computer system according to another embodiment of the present invention.

10‧‧‧ computer system

11‧‧‧First SMBUS master controller

12‧‧‧Second SMBUS master controller

13‧‧‧ Controller

14‧‧‧Selector

15‧‧‧Transport interface

16‧‧‧ memory

Claims (7)

A computer system with memory access conflict control, the computer system comprising: a first system control bus master controller (first SMBUS master controller) for communication between input and output busbars; a second system Control bus master controller (second SMBUS master controller) for monitoring system hardware programs; a controller coupled to the first SMBUS master controller, the first SMBUS master controller and the second When the SMBUS main controller is required to read and write a memory, the controller outputs a control signal; and a selector coupled to the controller, the first SMBUS main controller and the second SMBUS main controller, the selection Receiving the control signal, and selectively switching the first SMBUS main controller or the second SMBUS main controller to read and write the memory via a transmission interface according to the control signal. When the control signal indicates that the selector selects to read and write the memory by the first SMBUS main controller, and the first SMBUS main controller reads and writes the memory, the controller receives the first SMBUS main control. An end signal output by the device, and at least according to the end signal, outputting the control signal to instruct the selector to switch the second SMBUS main controller to read and write the memory via the transmission interface; wherein the controller receives the first When the SMBUS main controller outputs the end signal, the controller further determines whether the transmission interface is idle, and determines the transmission medium by the controller. When the surface is idle, the control signal is output to instruct the selector to switch the second SMBUS main controller to read and write the memory via the transmission interface. The computer system of claim 1, wherein the transmission interface comprises at least one data transmission line and a clock signal line, wherein the data transmission line is configured to transmit a data signal, and the clock signal line is used for transmitting A clock signal, the controller determines whether the transmission interface is idle according to the data signal and the voltage level of the clock signal. The computer system as claimed in claim 1, wherein the selector has a first switch and a second switch, and the first switch is disposed on the transmission interface and the first SMBUS main controller. In the path, the second switch is disposed on the transmission path of the transmission interface and the second SMBUS main controller. When the second SMBUS main controller does not read or write the memory, the selector presets to turn on the first Switch and disconnect the second switch. The computer system of claim 1, wherein the first SMBUS host controller is a Platform Controller Hub. The computer system of claim 1, wherein the second SMBUS main controller is a hardware monitor. The computer system of claim 1, wherein the transmission interface is a system management bus. The computer system with memory access conflict control according to claim 1, wherein the first SMBUS main controller has a general purpose input/output (General Purpose I/O), and the first SMBUS main controller is The input and output terminals of the type are coupled to the controller.