TWI599953B - Method and apparatus for performing big-integer arithmetic operations - Google Patents

Description

Method and apparatus for performing large integer arithmetic operations

The present invention generally relates to the field of computer processors. More particularly, the present invention relates to methods and apparatus for performing large integer arithmetic operations.

An instruction set, or an instruction set architecture (ISA), is part of a computer architecture. Part of the computer architecture is related to stylization, including ontology data types, instructions, scratchpad architecture, addressing mode, and memory. Architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction generally refers to a macro instruction, which is an instruction provided to the processor for execution. The macro instruction is opposite to the micro instruction or micro-op (micro-op), and the micro-instruction or micro-job is The result of the decoder of the processor that decodes the macro instruction. A microinstruction or microjob may be configured to execute an operation on an execution unit on an instruction processor to implement logic associated with the macro instruction.

The ISA differs from the microarchitecture of the processor design technology set of the processor used to implement the instruction set. Processors with different microarchitectures share a common instruction set. For example, almost the same version of the Intel ^® Pentium 4 processor embodiment processor, Intel ^® Core ^TM processors, and Advanced Micro Devices Inc. of Sun Valley, California from the x86 instruction set (updated version increased to some extent), but Has a different internal design. For example, in different microarchitectures using conventional techniques, the same ISA scratchpad architecture is implemented in different ways, including a dedicated physical scratchpad, using a scratchpad renaming mechanism (eg, using a scratchpad alias) Table (RAT), reorder buffer (ROB), and exit register file. Unless otherwise specified, the scratchpad architecture, scratchpad file, and scratchpad statements are used here to represent software/programmers. The way the viewer can be seen and the instructions indicate the scratchpad. In cases where clarity is required, the adjectives "logical", "architectural", or "software visible" will be used to represent the scratchpad architecture. A scratchpad/file, and different adjectives are used to indicate the destination scratchpad in a given microarchitecture (eg, physical scratchpad, reorder buffer, exit scratchpad, scratchpad pool) .

The instruction set contains one or more instruction formats. A given instruction format defines different fields (number of bits, bit positions) to specify the job (job code) to be executed and the operand on which the job is to be executed. Some instruction formats can be further decomposed by the definition of the instruction template (or the sub-context format). For example, a command template for a given instruction format can be defined as an instruction format field with a different subset (the multiple fields included are typically in the same order, but because there are fewer fields to include So, at least some of the fields have different bit positions) and/or are defined as having a given field that is interpreted differently. Use the given instruction format (and, if specified, in one of a given number of instruction templates in the instruction format) to represent the given instruction, and to specify the job and operation yuan. An instruction string is a specific sequence of instructions in which each instruction in the sequence is an instruction in the instruction format (and, if defined, one of a given number of instruction templates in the instruction format).

300‧‧‧Scratchpad Architecture

310‧‧‧Vector register

315‧‧‧Write mask register

325‧‧‧General Purpose Register

345‧‧‧Simplified floating point stack register file

350‧‧‧MMX Compact Integer Flat Register File

400‧‧‧ pipeline

490‧‧‧ core

600‧‧‧ processor

700‧‧‧ system

800‧‧‧ system

900‧‧‧ system

1000‧‧‧System Chip

1200‧‧‧ main memory

1231‧‧‧256-bit multiplication instruction decoding logic

1241‧‧‧256-bit multiplication instruction execution logic

1255‧‧‧ processor

1300‧‧‧256 bit multiplication logic

1303‧‧‧ Destination Register

The invention will be better understood from the following detailed description of the drawings.

1A and 1B are block diagrams showing a generic vector friendly instruction format and a command template thereof in accordance with an embodiment of the present invention; and FIGS. 2A-D are block diagrams showing specific vector friendly instructions exemplified in accordance with an embodiment of the present invention; FIG. 3 is a block diagram of a scratchpad architecture in accordance with an embodiment of the present invention; FIG. 4A is a block diagram showing an ordered extraction, decoding, exit pipeline, and illustrations, exemplified in accordance with an embodiment of the present invention. a register rename, an out-of-order issue/execution pipeline; FIG. 4B is a block diagram showing an in-order extraction, decoding, exit core, and an exemplary register rename, mess, included in the processor in accordance with an embodiment of the present invention FIG. 5A is a block diagram showing a single core connected to the interconnect network on the die; FIG. 5B is an enlarged view of a portion of the processor core of FIG. 5A in accordance with an embodiment of the present invention; 6 is a block diagram showing a single core at an embodiment in accordance with the present invention A multi-core processor with integrated graphics and memory controller; FIG. 7 shows a block diagram of a system in accordance with an embodiment of the present invention; and FIG. 8 shows a block diagram of a second system in accordance with an embodiment of the present invention. Figure 9 shows a block diagram of a third system in accordance with an embodiment of the present invention; Figure 10 shows a block diagram of a system wafer in accordance with an embodiment of the present invention; and Figure 11 is a block diagram comparing sources in accordance with an embodiment of the present invention The use of a binary instruction in the instruction set to convert to a software instruction converter of a binary instruction in the target instruction set; FIG. 12 shows an exemplary processor on which embodiments of the present invention are implemented; FIG. 13 shows a 256-bit multiplication An embodiment of the invention of logic; Figure 14 shows another embodiment of the invention comprising 256-bit multiplication logic; Figure 15 shows another embodiment of the invention comprising 256-bit multiplication logic utilizing immediate values to identify source operands An embodiment; Figure 16 shows a multiplier and adder set for implementing an embodiment of the present invention; and Figure 17 shows a method in accordance with an embodiment of the present invention.

SUMMARY OF THE INVENTION AND EMBODIMENT

In the following description, for the purposes of illustration However, I am in this It will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are not shown in detail to avoid obscuring the basic principles of the embodiments of the invention.

Illustrated processor architecture and data type

The instruction set contains one or more instruction formats. A given instruction format defines different fields (number of bits, bit position) to specify the job (job code) to be executed and the operand for which the job is to be executed. Some instruction formats can be further decomposed by the definition of the instruction template (or the sub-context format). For example, a command template for a given instruction format can be defined as an instruction format field with a different subset (the multiple fields included are typically in the same order, but because there are fewer fields to include So, at least some of the fields have different bit positions) and/or are defined as having a given field that is interpreted differently. Thus, a given instruction format (and, if defined, in a given one of a plurality of instruction templates of the instruction format) is used to represent the instructions of the ISA, and includes instructions for specifying jobs and operands. For example, the illustrated ADD instruction has a specific job code and an instruction format, and the instruction format includes a job code field to specify the job code and the operation element field to select an operation element of the operation element (source 1 / destination and source 2 And; the presence of this ADD instruction in the instruction string will have specific content in the operand field of the particular operand selected. SIMD extensions called Advanced Vector Extension (AVX) (AVX1 and AVX2) and vector extension (VEX) coded designs have been released and/or published (for example, please refer to ^Intel® 64 and October 2011). IA-32 Architecture Software Developer's Manual; and, June 2011, ^Intel® Advanced Vector Extensions Reference).

Illustrated instruction format

The instruction embodiments described herein may be embodied in different formats. In addition, the systems, architectures, and pipelines illustrated are detailed below. Embodiments of the instructions are executed on these systems, architectures, and pipelines, but are not limited to the detailed embodiments.

A. Generic vector friendly instruction format

The vector friendly instruction format is an instruction format suitable for vector instructions (for example, some fields are specific to vector operations). While an embodiment of vector and scalar operations is supported via a vector friendly instruction format, alternative embodiments may use only vector friendly instruction format vector operations.

1A-1B are block diagrams showing a generic vector friendly instruction format and its instruction templates in accordance with an embodiment of the present invention. 1A is a block diagram showing a generic vector friendly instruction format and its level A instruction template according to an embodiment of the present invention; and FIG. 1B is a block diagram showing a generic vector friendly instruction format and an embodiment thereof according to an embodiment of the present invention; Level B instruction template. Specifically, the level A and level B command templates are defined for the generic vector friendly instruction format 100, and the level A and level B command templates do not include the memory access 105 command template and the memory access 120 command template. The term generic in the content of the vector friendly instruction format means that the instruction format is not tied to any particular instruction set.

An embodiment of the present invention will be described in which the vector friendly instruction format supports the following: 64-bit with 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) Group vector operation element length (or size) (hence, 64-bit tuple vector consists of 16 double word size elements or alternatively 8 quad-word size elements); has 16 bits (2 bytes) Or 8-bit (1-byte) data element width (or size) of 64-bit vector operation element length (or size); with 32-bit (4-byte), 64-bit (8-bit) Group), 16-bit (2-byte) or 8-bit (1-byte) data element width (or size) 32-bit vector operation element length (or size); and, with 32 bits 16-bit vector of (4 bytes), 64-bit (8-bit), 16-bit (2-byte), or 8-bit (1-byte) data element width (or size) The length (or size) of the operand; alternative embodiments support more, less, and/or with more, less, or different data element widths (eg, 128-bit (16-byte) data element width) Different vector operand sizes (for example, 256 octet vector operands).

The level A command template in FIG. 1A includes: 1) display no memory access, full round control type operation command instruction template, no memory access, data conversion in the no memory access 105 command template. The type operation 115 command template; and 2) within the memory access 120 command template, there are display memory access, temporary 125 command template and memory access, non-transitory 130 command template. The level B command template in FIG. 1B includes: 1) display no memory access, write mask control, partial round control type operation 112 command sample in the no memory access 105 command template. Board and memoryless access, write mask control, vector length type operation 117 command template; and 2) memory access, write mask control 127 displayed within the memory access 120 command template Command template.

The generic vector friendly instruction format 100 contains the following fields listed in the order shown in Figures 1A-1B.

Format field 140 - A particular value (instruction format identifier value) in this field uniquely identifies the vector friendly instruction format and thus identifies an instruction in the vector friendly instruction format in the instruction string. Rather, this field is optional for the view that this field is not required for an instruction set that only has a generic vector friendly instruction format.

The basic job field 142 - the basic job whose content is different.

Register index field 144 - its content is directly or via address generation indicating the location of the source and destination operands in the scratchpad or in memory. These contain a sufficient number of bits to select N scratchpads from PxQ (eg, 32x512, 16x128, 32x1024, 64x1024) scratchpad files. Although in one embodiment, N can be as high as three sources and one destination register, alternative embodiments can support more or fewer source and destination registers (eg, can support up to two The source, in which one of these sources also serves as a destination, can support up to three sources, one of which also serves as a destination, and can support up to two sources and one destination).

Modifier field 146 - its content distinction specifies (as indicated by 146B) and unspecified (as indicated by 146A) the occurrence of instructions in the generic vector instruction format of memory access; that is, in memoryless access 105 The command template is distinguished from the memory access 120 command template. Memory access operations read and/or write to the memory hierarchy (in some cases, use source values in the scratchpad to specify source and/or destination addresses), rather than memory access operations. (for example, the source and destination are scratchpads). Although in one embodiment, this field is also selected between three different modes to perform memory address calculations, alternative embodiments may support more, less, or different ways to perform memory address calculations. .

Augmentation Work Field 150 - The content distinguishes which of the many different jobs to be added plus the base job is executed. This field is content specific. In an embodiment of the invention, the field is divided into a rank field 168, an alpha field 152, and a beta field 154. Augmentation job field 150 allows a common job group to be executed with a single instruction instead of 2, 3, or 4 instructions.

The proportion of which field content is allowed 160- index field for a ratio of generating memory addresses (e.g., using base 2 ^scale * index + the address generation).

Displacement field 162A - its content is generated as part of the memory address (eg, for use with 2 ^scale * index + base + displacement address).

Displacement factor field 162B (note that displacement field 162A directly above the displacement factor field 162B indicates that one or the other is used) - its content is part of the address generation; it indicates that it depends on the memory A displacement factor that is scaled by the size of (N), where N is the number of bytes in the memory access (eg, for address generation using 2 ^scale * index + base + scaled displacement). Redundant low-order bits are ignored, so the content of the displacement factor column is multiplied by the full size (N) of the memory operand to produce the last displacement used to calculate the valid address. Based on the full job code field 174 (described later) and the data manipulation field 154C, the value of N is determined by the processor hardware at runtime. In the case where the displacement field 162A and the displacement factor field 162B are not used for the no-memory access 105 command template and/or the different embodiments only implement either or both, they are optional.

The data element width field 164 - whose content differs from the width of some of the data element widths is to be used (in some embodiments for all instructions; in other embodiments only for certain instructions). This field is optional if some fields of the job code are used and only one data element width is supported and/or the data element width is supported.

Write mask field 170 - its content controls whether the data element position in the destination vector operand reflects the result of the base job and the augmentation operation based on each data element position. The Level A command template supports merged write masks, while the Level B command template supports merge and zero write masks. When merging, the vector mask allows elements of any group in the destination to be protected (as indicated by the underlying job and the augmentation job) from being updated during execution of any job; in other embodiments, the corresponding mask is retained The mask bit has the old value of each element of the destination of 0. Conversely, when the vectorization mask is zeroed, the elements of any group in the destination are allowed to be zeroed during execution of any job (specified by the base job and the augmentation job); in an embodiment, when the corresponding mask bit is When the element has a value of 0, the element of the destination is set to 0. A subset of this function is the ability to control the vector length of the executed job (i.e., the spread of the modified element, from first to last); however, the modified elements need not be contiguous. As such, the write mask field 170 allows for partial vector jobs, including load, store, arithmetic, logic, and the like. Although an embodiment of the invention is illustrated in which the contents of the write mask field 170 are selected to be one of the write mask registers containing the write mask to be used (hence, the write mask field is written) The content of 170 indirectly identifies the mask to be executed), however, an alternate embodiment instead or additionally allows the content of the mask write field 170 to directly specify the mask to be executed.

Immediate field 172 - its content allows for immediate specifications. This field is optional if this field does not appear in a generic vector friendly format implementation that does not support immediateity and if it does not appear in an instruction that does not use immediateness.

Level field 168 - instructions whose content distinguishes different levels. Referring to Figures 1A-B, the contents of this field are selected between Level A and Level B instructions. In Figures 1A-B, a squared square is used to indicate that a particular value is present in the field (e.g., level A 168A and level B 168B for level field 168, respectively, in Figures 1A-B).

Level A command template

In the case of the non-memory access 105 command template of level A, the Alpha field 152 is interpreted as the RS field 152A, and the type of the different augmentation operation type is to be executed (for example, Rounding 152A.1 and data conversion 152A.2 are designated for memoryless access, rounding type operation 110 and no memory access, data conversion type operation 115 command template), while the beta field 154 difference Specified type The job in the job is to be executed. In the no-memory access 105 command template, the proportional field 160, the displacement ratio field 162A, and the displacement ratio field 162B do not appear.

No memory access command template - fully rounded control type

In the No Memory Access Full Round Control Type Job 110 command template, the beta field 154 is interpreted as a rounding control field 154A whose content provides static rounding. Although in the above described embodiment of the invention, rounding control field 154A includes suppression of all floating point exception (SAE) field 156 and rounding job control field 158, alternative embodiments may support encoding the two concepts to be the same The field may have only one or the other of these concepts/fields (eg, may have only rounded job control field 158).

SAE field 156 - whether the content difference disables the exception event report; when the 156 content flag suppression of the SAE field is enabled, the given instruction does not report any kind of floating point exception flag and does not evoke any floating point Exception processor.

The rounding job control field 158 - its content distinguishes which of the rounded job groups are to be executed (eg rounding, rounding, rounding to zero, and rounding to the nearest). Thus, the rounding job control field 158 allows for a change in the rounding mode based on each instruction. In an embodiment of the invention in which the processor includes a control register for indicating a rounding mode, the contents of the round job control field 158 replace the register value.

No memory access instruction template - data conversion type operation

In the no-memory access data conversion type job 115 instruction template, the beta field 154 is interpreted as a data conversion field 154B, the content of which distinguishes between the multiple data conversions to be performed (eg, no data conversion, reconciliation ,broadcast).

In the case of the memory access 120 command template of level A, the Alpha field 152 is interpreted as a eviction hint field 152B whose content difference eviction suggestion that one is to be used (in Figure 1A) Temporary 152B.1 and non-transient 152B.2 are designated for memory access, temporary 125 command templates and memory access, non-transitory 130 command templates, respectively, while the beta field 154 is interpreted as data manipulation. Field 154C, whose content distinguishes between which of a plurality of data manipulation jobs (also referred to as primitives) is to be executed (eg, no manipulation; broadcast; source up; and destination down). The memory access 120 instruction template includes a scale field 160 and optionally includes a displacement field 162A or a displacement ratio field 162B.

With conversion support, the vector memory instruction performs vector loading and vector storage on the memory. Like a normal vector instruction, a vector memory instruction transfers data to the memory in the form of a data element, and the actually transmitted element is specified by the content of the vector mask selected as the write mask.

Memory access command template - temporary

Temporary information is information that is likely to be used quickly enough to be profitable from the cache. However, this is a hint, as well, that different processors can implement it in different ways, including completely ignoring hints.

Memory access command template - not temporary

Non-transitory data is material that is unlikely to be used quickly enough to be profitable from the cache in the first layer of cache memory and should be granted eviction priority. However, this is a hint, as well, that different processors can implement it in different ways, including completely ignoring hints.

Level B command template

In the case of the level B command template, the Alpha field 152 is interpreted as a write mask control (Z) field 152C whose content distinguishes whether the write mask controlled by the write mask field 170 should be For merging or zeroing.

In the case of the non-memory access 105 command template of level B, the portion of the beta field 154 is interpreted as the RL field 157A, and the job type in the augmentation operation type in which the content is different is Executed (for example, Pickup 157A.1 and Vector Length (VSIZE) 157A.2 are specified for memoryless access, write mask control, partial rounding control type job 112 command template, and no memory, respectively. The access, write mask control, VSIZE type job 117 command template), while the rest of the beta field 154 distinguishes which of the specified types of jobs are to be executed. In the no memory access 105 command template, the proportional field 160, the displacement field 162A, and the displacement ratio field 162B do not exist.

In the no-memory access, the write mask control, the partial rounding control type job instruction template, and the other portions of the beta field 154 are interpreted as the rounding job field 159A and the exception event report is banned. Can (the given instruction does not report any kind of floating point exception flag and does not evoke any floating point exceptions Processor).

Rounding job control field 159A - just like the rounding job control field 158, the content of which is different from the rounding job group (for example, rounding, rounding, rounding to zero, and rounding to the nearest of). Thus, rounding job control field 159A allows for a change in the rounding mode based on each instruction. In an embodiment of the invention in which the processor includes a control register for indicating a rounding mode, the contents of the round job control field 159A replace the register value.

In the no-memory access, write mask control, VSIZE type job 117 command template, the rest of the beta field 154 is interpreted as a vector length field 159B, the content of which is different for multiple data vector lengths. The data vector length in the execution (for example, 128, 256, or 512 bytes).

In the case of the level B memory access 120 command template, a portion of the beta field 154 is interpreted as a broadcast field 157B, the content of which distinguishes whether the broadcast type data manipulation job is to be executed, and the beta column The other portion of bit 154 is interpreted as vector length field 159B. The memory access 120 command template includes a scale field 160 and, optionally, a displacement field 162A or a displacement scale field 162B.

Regarding the generic vector friendly instruction format 100, the full job code field 174 is displayed to include the format field 140, the base job field 142, and the data element width field 164. Although the display full job code field 174 includes an embodiment of all of these fields, in embodiments where none of them are supported, the full job code field 174 contains columns that are smaller than all of these fields. Bit. The full job code field 174 provides an opcode.

The augmentation work field 150, the data element width field 164, and the write mask field 170 allow these features to be specified based on instructions in the generic vector friendly instruction format.

The combination of the write mask field and the data element width field produces a typed instruction in which they allow masks to be applied according to different material element widths.

The various command templates found within Level A and Level B are advantageous in different situations. In some embodiments of the invention, different processors or different cores within the processor may only support level A, only level B, or support the two levels. For example, the out-of-order core for high performance purposes for general purpose calculations only supports level B, and the core for graphics and/or scientific (flux) calculations only supports level A and is used to support level two. The core can support two levels (of course, with some mix of templates and instructions from the second level, but not all templates and instructions from the second level are within the scope of the present invention). Moreover, a single processor contains multiple cores, all of which support the same level, or where different cores support different levels. For example, in a processor with separate graphics and general purpose cores, one of the plurality of graphics cores primarily used for graphics and/or scientific computing supports only level A, while one or more general purpose cores are available. A high-performance general-purpose core with out-of-order execution and register renaming for general purpose computing that only supports Level B. Another processor that does not have a separate graphics core may include one or more general purpose ordered or out-of-order cores that support Level A and Level B. Of course, in the present invention In different embodiments, features from one level may also be implemented in other levels. Programs written in higher-level languages will be placed (for example, only compiled or statically compiled into a variety of different executable forms), including: 1) only for execution The form of the instruction supported by the target processor; or, 2) an alternative routine written with a different combination of instructions of all levels and a form having a control flow code based on the currently executing code The routine to be executed is selected by the instructions supported by the processor.

B. Example specific vector friendly instruction format

2 is a block diagram showing a particular vector friendly instruction format exemplified in accordance with an embodiment of the present invention. 2 shows a particular vector friendly instruction format 200 that is specific in the context of the location, size, interpretation, and order of the specified fields, as well as the values for certain fields in those fields. The particular vector friendly instruction format 200 can be used to augment the x86 instruction set, and thus certain fields are similar or identical to the fields used in existing x86 instruction sets and their extensions (eg, AVX). This format maintains the precoding field, the real opcode byte field, the MOD R/M field, the SIB field, the displacement field, and the immediate field with the extended existing x86 instruction set. The fields from Figure 2 are shown mapped to the fields from Figure 1.

It should be appreciated that although a particular vector friendly instruction format 200 is referenced in the context of the generic vector friendly instruction format 100 for purposes of illustration to illustrate embodiments of the present invention, the invention is not limited to particular vector friendly instructions unless specifically stated otherwise. Format 200. For example, generic vector friendly The instruction format 100 allows for various possible sizes for various fields, while the particular vector friendly instruction format 200 is displayed as a field of a particular size. For example, although the data element width field 164 is displayed as a one-digit field in the specific vector friendly instruction format 200, the present invention is not limited thereto (that is, the generic vector friendly instruction format 100 takes into account the data element. The other size of the width field 164).

The generic vector friendly instruction format 100 contains the following fields listed below in the order shown in Figure 2A.

The EVEX preamble (bytes 0-3) 202 is encoded in a four-byte form.

Format field 140 (EVEX byte 0, bit [7:0]) - first byte (EVEX byte 0) is format field 140 and contains 0x62 (an embodiment for distinguishing inventions) The unique value of the vector friendly instruction format).

The second-fourth byte (EVEX bytes 1-3) contains some bit fields that provide specific capabilities.

REX field 205 (EVEX byte 1, bit [7-5]) consists of EVEX.R bit field (EVEX byte 1, bit [7]-R), EVEX.X bit field (EVEX byte 1, bit [6]-X), and 157BEX byte 1, bit [5]-B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit field and are encoded using a 1s complementary form, ie, ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. As is known in the art, the other fields of the instruction encode the lower three bits of the scratchpad index. The codes (rrr, xxx, and bbb) are such that Rrrr, Xxxx, and Bbbb can be formed by adding EVEX.R, EVEX.X, and EVEX.B.

REX' field 210 - This is the first part of the REX' field 210 and is the EVEX.R' bit field (EVEX bit) used to encode the upper 16 or lower 16 of the extended 32 register set. Group 1, bit [4]-R'). In an embodiment of the invention, the bit is stored in a bit-reversed format with other bits as indicated below to distinguish it from the BOUND instruction (in the known x86 32-bit mode), the real operation of the BOUND instruction The code byte is 62, however, the value of 11 in the MOD field is not accepted in the MOD R/M field (described below); an alternative embodiment of the present invention does not store this bit in an inverted format and other The marked bit. A value of 1 is used to encode the lower 16 registers. In other words, R'Rrrr is formed by combining EVEX.R', EVEX.R, and other RRRs from other fields.

The job code mapping field 215 (EVEX byte 1, bit [3:0]-mmmm) - its content encodes the implied leading job code byte (0F, 0F38, or 0F3).

The data element width field 164 (EVEX byte 2, bit [7]-W) - is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the data type (32-bit data element or 64-bit data element).

EVEX.vvvv 220 (EVEX byte 2, bit [6:3]-vvvv) - The role of EVEX.vvvv can include the following: 1) EVEX.vvvv will be specified in reverse (1s complementary) form first Source register operand encoding, and is valid for instructions with 2 or more source operands; 2) EVEX.vvvv will specify some vector offsets in 1s complementary form The local register operand encoding; or 3) EVEX.vvvv does not encode any operands, the field is reserved and should contain 1111b. Thus, the EVEX.vvvv field 220 will encode the 4th order bits of the first source register identifier stored in inverted (1s complementary) form. Depending on the instruction, additional different EVEX bit fields are used to extend the specifier size to the 32 scratchpad.

EVEX.U 168 level field (EVEX byte 2, bit [2]-U) - if EVEX.U=0, it indicates level A or EVEX.U0; if EVEX.U=1, it is marked Level B or EVEX.U1.

The precoding field 225 (EVEX byte 2, bit [1:0]-pp) - provides the added bit for the base job field. In addition to providing legacy SSE instructions that support the EVEX pre-format, this also has the advantage of making the SIMD pre-small (rather than requiring a byte to represent the SIMD preamble and the EVEX preamble only requiring 2 bits). In an embodiment, in order to support legacy SSE instructions using SIMD pre- (66H, F2H, F3H) in both legacy format and EVEX pre-format, these legacy SIMD preambles are encoded into SIMD preambles. Encoding field; and, before being served to the PLA of the decoder (so that the PLA can execute the legacy of these legacy instructions and the EVEX et al. without modification), it is expanded to the old SIMD preamble at runtime . While newer instructions may directly use the contents of the EVEX precoding field as an opcode extension, some embodiments extend in a similar manner for consistency but allow different meanings to be specified by these legacy SIMD preambles. Alternate embodiments may redesign the PLA to support 2-bit SIMD preamble and thus do not require extension.

Alfa Field 152 (EVEX byte 3, bit [7]-EH; also known as Write mask control for EVEX.EH, EXEX.rs, EVEX.RL, EVEX., and EVEX.N; also shown as a) - as described previously, this field is content specific.

Beta field 154 (EVEX byte 3, bit [6:4]-SSS; also known as EVEX.s _2-0 , EVEX.r _2-0 , EVEX.rr1, EVEX.LL0, EVEX.LLB ; also shown as β β β) - as described previously, this field is content specific.

REX' field 210 - This is the remainder of the REX' field and is the EVEX.V' bit field (EVEX byte 3) that can be used to encode the upper 16 or lower 16 of the extended 32 register set. , bit [3]-V'). This bit is stored in a bit reverse format. A value of 1 is used to encode the lower 16 registers. In other words, V'VVVV is formed by combining EVEX.V', EVEX.vvvv.

Write mask field 170 (EVEX byte 3, bit [2:0]-kkk) - as previously described, its contents specify the scratchpad index written into the hood register. In an embodiment of the invention, the specific value EVEX.kkk=000 has a special representation, implying that there is no write mask for a particular instruction (this can be implemented in various ways, including using physical wiring to all or hardware) Write to the mask, the hardware is bypassing the mask hardware).

The real job code field 230 (bytes 4) is also referred to as a job code byte. Specify a part of the job code in this field.

The MOD R/M field 240 (byte 5) contains the MOD field 242, the Reg field 244, and the R/M field 246. As previously described, the contents of MOD field 242 distinguish between memory access and non-memory access operations. The role of Reg field 244 can be summed up in two cases: the destination is temporarily The register operand or source register operand code is either processed as a job code extension and is not used to encode any instruction operands. The role of the R/M field 246 may include the following: encoding the instruction operand of the reference memory address, or encoding the destination register operand or source register operand.

Proportional, Index, Base (SIB) Bytes (Bytes 6) - As previously described, the content of the proportional field 250, including the ss field 252, is used for memory address generation. SIB.xxx 254 and SIB.bbb 256 - The contents of these fields have been previously described in relation to the scratchpad indices Xxxx and Bbbb.

Displacement field 162A (bytes 7-10) - When MOD field 242 contains 10, byte 7-10 is displacement field 162A, and it works the same as the old 32 bit displacement (disp32) and The byte size works.

Displacement Factor Field 162B (Bytes 7) - When MOD field 242 contains 01, byte 7 is the displacement factor field 162B. The location of this field is the same as the position of the old x86 instruction set 8-bit displacement (disp8) that works at byte granularity. Since disp8 is a sign extension, it can only be addressed between the -128 and 127 byte gaps; from the point of view of the 64-bit cache line, disp8 usage can be set to only four really useful The values are -128, -64, 0, and 64 octets; since a larger range is usually required, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 162B is a reinterpretation of disp8; when the displacement factor field 162B is used, the true displacement is determined by multiplying the content of the displacement factor field by the memory operand access (N). . This type of displacement is called disp8*N. This lowers the average instruction Length (a single byte for displacement but with a larger range). This compressed displacement is based on the assumption that the effective displacement is a multiple of the granularity of memory access, so redundant low-order bits of the address gap need not be encoded. In other words, the displacement factor field 162B replaces the old x86 instruction set 8-bit displacement. Thus, the displacement factor field 162B is encoded in the same manner as the x86 instruction set 8-bit displacement (so that the ModRM/SIM encoding rules are unchanged), with the only exception that disp8 is overloaded to disp8*N. In other words, there is no change in the encoding rule or the length of the code, but only the interpretation of the displacement value by the hardware has changed (this requires the displacement to be scaled according to the size of the memory operand to obtain the bit gap of the byte mode).

The immediate field 172 as shown by IMM 8 operates as previously described.

Full job code field

2B is a block diagram showing the fields of a particular vector friendly instruction format 200 that constitutes a full job code field 174, in accordance with an embodiment of the present invention. Specifically, the full job code field 174 includes a format field 140, a base job field 142, and a data element width (W) field 164. The base job field 142 includes a pre-coded field 225, a job code mapping field 215, and a real job code field 230.

Scratchpad index field

2C is a block diagram showing the fields of a particular vector friendly instruction format 200 that constitutes the scratchpad index field 144 in accordance with an embodiment of the present invention. Specifically, the register index field 144 includes the REX field 205, REX' field 210, REG field 244, R/M field 246, VVVV field 220, xxx field 254, and bbb field 256.

Augmentation work field

2D is a block diagram showing the fields of a particular vector friendly instruction format 200 that constitutes an augmentation work field 150, in accordance with an embodiment of the present invention. When level (U) field 168 contains 0, it means EVEX.U0 (level A 168A); when it contains 1, it represents EVEX.U1 (level B 168B). When U=0 and MOD field 242 contain 11 (indicating no memory access operation), Alfa field 152 (EVEX byte 3, bit [7]-EH) is interpreted as rs field 152A . When rs field 152A contains 1 (rounded 152A.1), beta field 154 (EVEX byte 3, bit [6:4]-SSS) is interpreted as rounding control field 154A. The rounding control field 154A includes a one-bit SAE field 156 and a two-bit rounding job field 158. When rs field 152A contains 0 (data conversion 152A.2), beta field 154 (EVEX byte 3, bit [6:4]-SSS) is interpreted as three-bit data conversion field 154B . When U=0 and MOD field 242 contain 00, 01, or 10 (representing a memory access job), Alfa field 152 (EVEX byte 3, bit [7]-EH) is interpreted as The eviction hint (EH) field 152B and the beta field 154 (EVEX byte 3, bit [6:4]-SSS) are interpreted as a three-bit data manipulation field 154C.

When U = 1, Alpha field 152 (EVEX byte 3, bit [7] - EH) is interpreted as write mask control (Z) field 152C. When U=1 and MOD field 242 contain 11 (indicating no memory access operation), a portion of the beta field 154 (EVEX byte 3, bit [4]-S ₀ ) is interpreted. Is the RL field 157A; when it contains 1 (rounded 157A.1), the rest of the beta field 154 (EVEX byte 3, bit [6-5]-S _2-1 ) is solved Translated as rounding field 159A, and when RL field 157A contains 0 (VSIZE 157.A2), the rest of the beta field 154 (EVEX byte 3, bit [6-5]-S _2-1 ) is interpreted as vector length field 159B (EVEX byte 3, bit [6-5]-L _1-0 ). When U=1 and MOD field 242 contain 00, 01 or 10 (representing a memory access job), the beta field 154 (EVEX byte 3, bit [6:4]-SSS) is interpreted. It is a vector length field 159B (EVEX byte 3, bit [6-5]-L _1-0 ) and a broadcast field 157B (EVEX byte 3, bit [4]-B).

C. An example of a scratchpad architecture

FIG. 3 is a block diagram of a scratchpad architecture 300 in accordance with an embodiment of the present invention. In the illustrated embodiment, there are 32 vector scratchpads 310 of 512 bit width; these registers are referred to as zmm0 to zmm31. The lower order 256 bits of the lower 16zmm register are overlaid on the scratchpad ymm0-15. The lower order 128 bits of the lower 16-zmm scratchpad (the lower order 128 bits of the ymm register) are overlaid on the scratchpad xmm0-15. As shown in the table below, a particular vector friendly instruction format 200 operates on these overwritten scratchpad files.

In other words, the vector length field 159B is selected between a maximum length and one or more other shorter lengths, wherein each such shorter length is one-half the length of the previous length; and an instruction without the vector length field 159B The template works for the maximum vector length. Moreover, in one embodiment, the level B command template of the particular vector friendly instruction format 200 is for compact or scalar single/double precision floating point data and compact or scalar integer data jobs. A scalar job is a job performed on the lowest order data element position in the zmm/ymm/xmm register; higher order data element positions are left as they are or zeroed before the instruction, depending on the embodiment.

Write hood register 315 - In the illustrated embodiment, there are eight write mask registers (k0 through k7) of size 64 bits. In an alternate embodiment, the write hood register 315 is 16 bits in size. As previously described, in an embodiment of the invention, the vector mask register k0 cannot be used as a write mask; when the code normally labeled k0 is used to write a mask, it selects the write of the physical wiring of 0xFFFF. Into the mask, effectively used in the instruction The write mask is disabled.

General Purpose Register 325 - In the illustrated embodiment, there are sixteen 64-bit general purpose registers that are used with existing x86 addressing modes to address memory operands. These registers are represented by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 to R15.

A scalar floating point stack register file (x87 stack) 345, MMX packed integer flat register file 350 is stacked thereon - in the illustrated embodiment, the x87 stack is an octal stack for use with the x87 instruction set Extends, performs scalar floating point operations on 32/64/80-bit floating-point data; the MMX register is used to perform operations on 64-bit compacted scratchpad data, and for some temporary storage in MMX and XMM The operand is held by the job executed between the devices.

Alternative embodiments of the invention may use a wider or narrower register. Moreover, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

D. An illustration of the core architecture, processor, and computer architecture

The processor core is implemented in different ways and in different processors for different purposes. For example, the implementation of these cores includes: 1) a general-purpose ordered core to be used for general-purpose computing; 2) a high-performance general-purpose out-of-order core to be used for general-purpose computing; and 3) mainly for graphics and/or Or the core of a specific use of scientific (transportation) calculations. Implementations of different processors include: 1) CPU, containing one to be used for general purpose computing Or more general-purpose ordered cores and/or one or more general purpose out-of-order cores to be used for general-purpose computing; and 2) secondary processors, including primarily for graphical and/or scientific (transport) calculations One or more specific use cores. These different processors lead to different computer system architectures, including: 1) a sub-processor on a separate wafer from the CPU; 2) a sub-processor on separate dies in the same package as the CPU; 3) A sub-processor on the same die as the CPU (in this case, this sub-processor is sometimes referred to as a special-purpose logic, such as integrated graphics and/or science (transmission) logic, or as specific Use core); and 4) system chips containing the CPU (sometimes referred to as an application core or application processor), the aforementioned sub-processors, and other functions on the same die. The core architecture illustrated by the following is illustrated below, followed by an illustration of the illustrated processor and computer architecture.

4A is a block diagram showing an ordered pipeline and an exemplary scratchpad rename, out of order issue/execution pipeline, exemplified in accordance with an embodiment of the present invention. 4B is a block diagram showing an exemplary embodiment of an exemplary register renaming, out-of-order issue/execution architecture core, and an ordered architecture core to be included in a processor in accordance with an embodiment of the present invention. The solid lines in Figures 4A-B show the ordered pipeline and the ordered core, while the selected dashed squares show the register rename, the out-of-order issue/execution pipeline, and the core. Under the assumption that the ordered pattern is a sub-set of disordered states, the disordered state is explained.

In FIG. 4A, processor pipeline 400 includes an extraction stage 402, a length decoding stage 404, a decoding stage 406, an allocation stage 408, a rename stage 410, and a row. The process (also referred to as dispatch or issue) stage 412, scratchpad read/memory read stage 414, execution stage 416, write back/memory write stage 418, exception processing stage 422, and commit stage 424.

4B shows a processor core 490 that includes a front end unit 430 coupled to an execution engine unit 450, both of which are coupled to a memory unit 470. The core 490 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core pattern. With respect to yet another option, core 490 can be a core for special purposes, such as, for example, a network or communication core, a compression engine, a secondary processor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

The front end unit 430 includes a branch prediction unit 432 coupled to an instruction cache unit 434, the instruction cache unit 434 is coupled to an instruction translation lookaside buffer (TLB) 436, and the instruction translation lookaside buffer (TLB) 436 is coupled. To instruction fetch unit 438, instruction fetch unit 438 is coupled to decode unit 440. Decoding unit 440 (or decoder) decodes the instructions and generates microcode entry points, microinstructions, other instructions, or decodes from the original instructions, or otherwise reacts from the original instructions, or other derived from the original instructions. Control the signal to one or more micro-jobs as an output. A variety of different mechanisms are used to implement decoding unit 440. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memory (ROM), and the like. In an embodiment, core 490 includes microcode for storing certain macro instructions (eg, For example, in the decoding unit 440 or in the front end unit 430, the microcode ROM or other media. Decoding unit 440 is coupled to renaming/allocator unit 452 in execution engine unit 450.

Execution engine unit 450 includes a rename/allocator unit 452 that is coupled to a collection of exit unit 454 and one or more scheduler units 456. Scheduler unit 456 represents any number of different schedulers, including reservation stations, central command windows, and the like. Scheduler unit 456 is coupled to physical register file unit 458. Each physical register file unit 458 represents one or more physical register files, and different physical register files store, for example, scalar integers, scalar floating points, compact integers, compact floating points, vector integers, vector floating points. , etc. One or more different data types, states (eg, instruction indicators, instruction indicators are the addresses of the next instruction to be executed), and so on. In one embodiment, the physical scratchpad file unit 458 includes a vector register unit, a write hood register unit, and a scalar register unit. These register units provide an architectural vector register, a vector mask register, and a general purpose register. The physical scratchpad file unit 458 is overlapped by the exit unit 454 to display various ways of implementing register rename and out-of-order execution (eg, using a reorder buffer and exiting the scratchpad file; using future files, history buffers, and Exit the scratchpad file; use the scratchpad map and the scratchpad pool, etc.). Exit unit 454 and physical register file unit 458 are coupled to execution cluster 460. Execution cluster 460 includes a collection of one or more execution units 462 and a collection of one or more memory access units 464. Execution unit 462 performs different jobs (eg, offset, addition, subtraction, multiplication) as well as information on different types (eg, Scalar floating point, compact integer, compact floating point, vector integer, vector floating point) execute the job. While some embodiments include some execution units that are specific to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that perform all functions. Since some embodiments generate separate pipelines for certain types of data/jobs, scheduler unit 456, physical register file 458, and execution cluster 460 are shown as likely to be plural (eg, both have Their own scheduler unit, physical register file unit, and/or scalar integer pipeline that performs clustering, scalar floating/compact integer/tight floating point/vector integer/vector floating point pipeline and/or memory Access management, and in the case of separate memory access pipelines, implements certain embodiments in which only the execution cluster of this pipeline has a memory access unit 464). It should also be appreciated that when separate pipelines are used, one or more of these pipelines may be out of order issue/execution, while others are ordered.

The set of memory access units 464 are coupled to a memory unit 470 that includes a data TLB unit 472 coupled to a data cache unit 474 that is coupled to a level 2 (L2) cache unit 476. In an illustrative embodiment, memory access unit 464 includes a load unit, a store address unit, and a store data unit, each unit being coupled to a data TLB unit 472 in memory unit 470. Instruction cache unit 434 is in turn coupled to level 2 (L2) cache unit 476 in memory unit 470. L2 cache unit 476 is coupled to one or more other levels of cache memory and finally to the main memory.

For example, an example of register renaming, out-of-order issuing/executing The row core architecture implements pipeline 400 as follows: 1) instruction fetch 438 performs fetch and length decode stages 402 and 404; 2) decode unit 440 performs decode stage 406; 3) rename/allocator unit 452 performs allocation stage 408 and Renaming stage 410; 4) scheduler unit 456 performs scheduling stage 412; 5) physical register file unit 458 and memory unit 470 executing register read/memory read stage 414; execution cluster 460 execution Execution stage 416; 6) memory unit 470 and physical register file unit 458 perform write back/memory write stage 418; 7) various units involve exception processing stage 422; and, 8) exit unit 454 and entity temporary storage The file archive unit 458 executes the commit stage 424.

Core 490 supports one or more instruction sets (for example, the x86 instruction set (which adds some extensions to newer versions); MIPS Technologies' MIPS instruction set from California Sun Valley; ARM Holdings' ARM instruction set from Sun Valley, California (plus Optional additions such as NEON add extensions)), including the instructions described herein. In one embodiment, core 490 includes logic to support a compact data instruction set extension (eg, AVX1, AVX2) to allow jobs used by many multimedia applications to be executed using compacted material.

It should be understood that the core support is multi-threaded (executing two or more parallel jobs or groups), and is performed in various ways, including time-cutting and multi-threading (where a single entity core is provided for the entity) The core is a logical core of multiple threads that are simultaneously multi-threaded, or a combination thereof (for example, time-cut extraction and decoding, and subsequent multi-threading, such as shown in Intel ^® Hyperthreading technology).

Although register renaming is described in an out-of-order execution environment, it should be understood that register renaming can be used in an ordered architecture. Although the illustrated embodiment of the processor also includes separate instruction and data cache units 434/474 and a shared L2 cache unit 476, alternative embodiments have a single internal cache for instructions and data, such as a hierarchy. 1 (L1) internal cache, or multi-level internal cache. In some embodiments, the system includes a combination of internal caches and external caches, the external cache being external to the core and/or processor. Alternatively, all caches may be external to the core and/or processor.

5A-B show block diagrams of a more specific illustrated ordered core architecture in which the core is one of several logical blocks (including other cores of the same type and/or different types) in the wafer. These logic blocks are communicated depending on the application via a high frequency wide interconnect network (eg, a ring network), a memory I/O interface, and other required I/O logic with certain fixed function logic.

5A is a diagram of a single processor core, and its connection to its intra-die interconnect network 502 and its local subset of class 2 (L2) caches 504, in accordance with an embodiment of the present invention. Block diagram. In one embodiment, the instruction decoder 500 supports an x86 instruction set with an expansion of the compact data instruction set. The L1 cache memory 506 allows access to scalar and vector units for cache memory low latency. Although in one embodiment (to simplify the design), scalar unit 508 and vector unit 510 use separate sets of registers (both scalar registers 512 and vector registers 514, respectively) and are transferred between them. Data is written to memory and then from level 1 (L1) The cache memory 506 is read back, however, alternative embodiments of the present invention may use different methods (eg, using a single scratchpad set or containing a communication path, allowing data to be transferred between the two scratchpad files without writing Enter and read back).

The local subset of L2 cache memory 504 is the portion of the general L2 cache that is partitioned into a plurality of respective local subsets, each processor core having a separate local subset. Each processor core has a direct access path to its own local subset of L2 cache memory 504. Parallel to the other processor cores accessing their own local L2 cache memory subset, the data read by the processor core is stored in the L2 cache subset 504 and can be accessed quickly. The data written by the processor core is stored in its own L2 cache sub-set 504 and flooded from other subsets if needed. The ring network ensures the homology of shared data. The ring network is bidirectional to allow, for example, processor cores, L2 caches, and other logic blocks to communicate with each other within the wafer. Each ring data path is 1012 bits wide in each direction.

Figure 5B is an enlarged view of a portion of the processor core of Figure 5A, in accordance with an embodiment of the present invention. FIG. 5B includes the L1 data cache 506A portion of L1 cache 506, and more details regarding vector unit 510 and vector register 514. In particular, vector unit 510 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 528) that performs one of integer, single precision floating point, and double precision floating point instructions or more many. The VPU supports the buffer register input by the blending unit 520, the digital conversion by the digital conversion unit 522A-B, and the copying by the copy unit 524 on the memory input. Write mask register 526 Allows vector writes caused by predictions.

6 is a block diagram of a processor 600 having more than one core, having an integrated memory controller, and having integrated graphics, in accordance with an embodiment of the present invention. The thick lined box in FIG. 6 shows processor 600 having a single core 602A, system agent 610, one or more bus controller unit 616, and the selected dashed box shows multi-core 602A-N, A set of one or more integrated memory controller elements 614 in system agent unit 610, and an alternate processor 600 of special purpose logic 608.

Thus, different implementations of processor 600 include: 1) a CPU with special purpose logic 608 and cores 602A-N, and application specific logic 608 is integrated graphics and/or scientific (flux) logic (including one or more cores) Core 602A-N is one or more general purpose cores (eg, general purpose ordered core, general purpose out-of-order core, a combination of the two); 2) secondary processor with core 602A-N, core 602A -N is a large number of specific use cores primarily for graphics and/or science (flux); and, 3) a sub-processor with cores 602A-N, core 602A-N is a large number of general purpose ordered cores. Therefore, the processor 600 can be a general-purpose processor, a sub-processor, or a specific purpose processing, for example, a network or communication processor, a compression engine, a graphics processor GPGPU (general purpose graphics processing unit), and a high throughput. Integrated core (MIC) sub-processor (including 30 or more cores), embedded processor, and more. The processor can be implemented on one or more wafers. Processor 600 can be implemented on one or more substrates and/or portions thereof using a variety of process technologies such as BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache memory within the core, a set or one or more shared cache units 606, and external memory coupled to the integrated memory controller unit 614 group ( Not shown). The shared cache unit 606 group may include one or more intermediate caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other hierarchical cache memory, and the last level cache memory ( LLC), and/or combinations thereof. Although in an embodiment, the ring basic interconnect unit 612 interconnects the integrated graphics logic 608, the set of shared cache units 606, and the system agent unit 610 / integrated memory controller unit 614, alternative implementations Examples Any number of known techniques can be used to interconnect these units. In an embodiment, one or more cache units 606 maintain coherence between cores 602-A-N.

In some embodiments, one or more of the cores 602A-N can be multi-threaded. System agent 610 includes those components that coordinate and operate cores 602A-N. System agent unit 610 can include, for example, a power control unit (PCU) and a display unit. The PCU can be or contain the logic and components needed to adjust the power states of cores 602A-N and integrated graphics logic 608. The display unit is a display for driving one or more external connections.

From the perspective of the architectural instruction set, cores 602A-N may be homogeneous or heterogeneous; that is, two or more of cores 602A-N can execute the same set of instructions, while other cores can execute only the set of instructions. Subsets or different instruction sets.

7-10 are block diagrams of an exemplary computer architecture. For laptops, desktops, handheld PCs, personal digital assistants, engineering workers Stations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, mobile phones, portable Other system designs and configurations well known in the art for media players, handheld devices, and a wide variety of other electronic devices are also suitable. In general, a wide variety of systems or electronic devices capable of having the processors and/or other execution logic disclosed herein are generally suitable.

Referring now to Figure 7, a block diagram of a system 700 in accordance with an embodiment of the present invention is shown. System 700 can include one or more processors 710, 715 coupled to controller hub 720. In one embodiment, controller hub 720 includes a graphics memory controller hub (GMCH) 790 and an input/output hub (IOH) 750 (which may be on separate wafers); GMCH 790 includes memory and graphics controllers, memory Body 740 and sub-processor 745 are coupled to a memory and graphics controller; IOR 750 couples input/output (I/O) device 760 to GMCH 790. Alternatively, one or both of the memory and graphics controller are integrated within the processor (as described above), the memory 740 and the secondary processor 745 are directly coupled to the processor 710, and the single chip with the IOH 750 Controller hub 720.

The added nature of the added processor 715 is indicated by dashed lines in FIG. Each processor 710, 715 includes one or more processing cores as described herein and may be a processor 600 of some versions.

For example, the memory 740 can be a dynamic random access memory (DRAM), phase change memory (PCM), or a combination of both. For at least one embodiment, the controller hub 720 is connected via multiple contacts The bus is in communication with the processors 710, 715, and the plurality of busses are, for example, a front side bus (FSB), a point-to-point interface such as a fast path interconnect (QPI), or the like.

In an embodiment, the secondary processor 745 is a special purpose processor, such as a high throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like. In an embodiment, controller hub 720 includes an integrated graphics accelerator.

There are various differences between physical resources 710, 715 from the perspective of measuring spectra including architecture, microarchitecture, thermal, power consuming characteristics, and the like.

In one embodiment, processor 710 executes instructions that control a general type of data processing job. Processor instructions can be embedded within the instructions. Processor 710 treats these sub-processor instructions as a pattern that should be executed by additional sub-processor 745. Accordingly, processor 710 issues these sub-processor instructions (or control signals representing sub-processor instructions) to sub-processor 745 on the secondary processor bus or other interconnect. The secondary processor 745 accepts and executes the received processor instructions.

Referring now to Figure 8, a block diagram of a system 800 in accordance with a first more specific illustration of an embodiment of the present invention is shown. As shown in FIG. 8, multiprocessor system 800 is a point-to-point interconnect system and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850. Each processor 870 and 880 can be a version of processor 600. In an embodiment of the invention, processors 870 and 880 are processors 710 and 715, respectively, and secondary processor 838 is a secondary processor 745. In another embodiment, processors 870 and 880 are processor 710 and secondary processor, respectively. 745.

Processors 870 and 880 are shown as including integrated memory controller (IMC) units 872 and 882, respectively. Processor 870 also includes point-to-point (P-P) interfaces 876 and 878 as part of its bus controller unit; similarly, second processor 880 includes P-P interfaces 886 and 888. Processors 870, 880 can exchange information via point-to-point (P-P) interface 850 using P-P interface circuits 878, 888. As shown in Figure 8, IMCs 872 and 882 couple the processors to respective memories, namely memory 832 and memory 834, which may be part of the main memory locally attached to the respective processors.

The processors 870, 880 can exchange information with the chipset 890 via the individual P-P interfaces 852, 854 using point-to-point interface circuits 876, 894, 886, 898. Chipset 890 selectively exchanges information with secondary processor 838 via high performance interface 839. In an embodiment, the secondary processor 838 is a special purpose processor, such as a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like.

The shared cache memory (not shown) may be included in either or both of the processors and not connected to the processor via the PP interconnect, such that if the processor is placed in a low power mode, either Or the local cache information of the second processor can be stored in the shared cache memory.

Wafer set 890 can be coupled to first bus bar 816 via interface 896. In an embodiment, the first bus bar 816 can be a peripheral component interconnect (PCI) bus, or, for example, a PCI bus or other third. A bus bar such as an I/O mutual bus bar is used, but the scope of the present invention is not limited thereto.

As shown in FIG. 8, a wide variety of I/O devices 814 and bus bar bridges 818 are coupled to a first bus bar 816 that couples a first bus bar 816 to a second bus bar 820. In one embodiment, for example, a sub-processor, a high-throughput MIC processor, a GPGPU, an accelerator (eg, a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor, etc. One or more additional processors 815 are coupled to the first bus 816. In an embodiment, the second bus bar 820 can be a low pin count (LPC) bus bar. In an embodiment, various devices may be coupled to the second bus 820, for example, including a keyboard and/or mouse 822, a communication device 827, and, for example, a disc drive containing instructions/codes and data 830 or other mass storage. A storage unit 828 of the device. Additionally, audio I/O 824 can be coupled to second bus 820. Note that other architectures are possible. For example, instead of the point-to-point architecture of Figure 8, the system can implement a multi-contact bus or other such architecture.

Referring now to Figure 9, a block diagram of a second more specific illustrated system 900 in accordance with an embodiment of the present invention is shown. Similar elements in Figures 8 and 9 bear similar reference numerals, and certain aspects of Figure 8 are omitted in Figure 9 to avoid obscuring the other aspects of Figure 9.

FIG. 9 shows that processors 870, 880 include integrated memory and I/O control logic (CL) 872 and 882, respectively. Therefore, CL 872, 882 includes an integrated memory controller unit and contains I/O control logic. Figure 9 shows that not only memory 832, 834 is coupled to CL 872, 882, I/O device 914 It is also coupled to control logic 872, 882. The legacy I/O device 915 is coupled to the chip set 890.

Referring now to Figure 10, there is shown a block diagram of a system wafer (SoC) 1000 in accordance with an embodiment of the present invention. Similar elements in Figure 6 have similar designations. Moreover, the dashed box is about the selection features of more advanced SoCs. In FIG. 10, the interconnection unit 1002 is coupled to: an application processor 1010, a set including one or more cores 202A-N and a shared cache unit 606; a system agent unit 610; a bus controller unit 616; integrated memory Body controller unit 614; one or more sub-processors 1020, including integrated graphics logic, image processor, audio processor, and video processor; static random access memory (SRAM) unit 1030; direct A memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays. In an embodiment, the secondary processor 1020 includes a special purpose processor, such as, for example, a network or communications processor, a compression engine, a GPGPU, a high throughput MIC processor, an embedded processor, and the like.

The mechanism embodiments disclosed herein can be implemented in hardware, software, firmware, or a combination of these embodiments. Embodiments of the invention may be implemented as a computer program or code executed on a programmable system, the programmable system including at least one processor, a storage system (including electrical and non-electrical memory and/or storage elements) At least one input device and at least one output device.

For example, the code 830 shown in Figure 8 can be applied to input instructions to perform the functions described herein and to generate output information. Output information can be The knowledge mode is applied to one or more output devices. For this application, the processing system includes any system having a processor such as a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

The code can be implemented in a high-level program or object-oriented programming language to communicate with the processing system. The code can also be implemented in a combination or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language can be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented by a representative instruction stored on a machine readable medium, the representative instructions representing various logic within the processor, and causing the machine manufacturing logic to perform this when the instructions are read by the machine The technology described. These representatives, referred to as "IP cores", can be stored in physical, machine-readable media and supplied to a wide variety of customers or manufacturing facilities, to the manufacturing machines or processors that actually generate the logic.

The machine readable medium includes, but is not limited to, non-transitory, physical configurations of articles manufactured or formed by the machine or device, including storage media such as a hard disk, including floppy disks, optical disks, and optical disk read-only memory (CD-ROM). ), any other type of disc, such as a CD-RW, and a magneto-optical disc, such as a read-only memory (ROM), such as a dynamic random access memory (DRAM), static random access memory. Semiconductor devices such as random access memory (RAM) such as SRAM, erasable programmable read-only memory (EPROM), flash memory, and electrically erasable programmable read-only memory (EEPROM), phase Change memory (PCM), Magnetic or optical card, or any other type of media suitable for storing electronic instructions.

Thus, embodiments of the invention also include non-transitory, physical machine readable media containing instructions or design data, such as hardware description language (HDL), which defines the structures described herein. , circuit, device, processor and/or system features. These embodiments also mean a program product.

In some cases, an instruction converter can be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter can translate the instructions (eg, using static binary translation, dynamic binary translation including dynamic compilation), variants, impersonation, or otherwise convert to one or more other processes handled by the core instruction. The command converter can be implemented in software, hardware, firmware, or a combination thereof. The instruction converter can be on the processor, not on the processor, or partially on the processor and partially off the processor.

11 is a block diagram showing the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set for comparison in accordance with an embodiment of the present invention. In the embodiment shown, the command converter is a software command converter, however, the command converter can alternatively be implemented in software, firmware, hardware, or various combinations thereof. 11 shows a program of higher order language 1102 that can be compiled by x86 compiler 1104 to produce x86 binary code 1106, which can be executed in-place by a processor having at least one x86 instruction set core 1116. A processor having at least one x86 instruction set core 1116 is represented by co-processing or other parties Any of the following, capable of performing substantially the same functions as an Intel processor having at least one x86 instruction set core: (1) a substantial portion of the instruction set of the Intel x86 instruction set core, or (2) An object code version of an application or other software targeted for execution on an Intel processor having at least one x86 instruction set core to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The x86 compiler 1104 represents a compiler operable to generate an x86 binary code 1106 (eg, an object code), and the x86 binary code 1106 may have at least one x86 instruction set with or without added link processing. Executed on the processor of core 1116. Similarly, Figure 11 shows a higher level language 1102 program that can be compiled to generate an alternate instruction set binary code 1110 using an alternate instruction set compiler 1108, which can have no at least one x86 instruction set. The processor of core 1114 (eg, with a processor executing the MIPS instruction set of MIPS Technologies, Inc., Sunnyvale, Calif., and/or the core of the ARM instruction set of ARM Holdings, Inc. of Sunnyvale, Calif.) is performed in place. The instruction converter 1112 is operative to convert the x86 binary bit code 1106 into a code that can be executed in-situ by a processor that does not have the x86 instruction set core 1114. Since the instruction converter that can be executed in this way is difficult to fabricate, the converted code is not as identical as the alternate instruction set binary carry code 1110; however, the converted code will complete the normal operation and consist of instructions from the alternate instruction set. Thus, the instruction converter 1112 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have an x86 instruction set processor or core via emulation, emulation, or any other processing. The x86 binary code 1106 is executed.

Method and device for performing large integer arithmetic operation

Large integer arithmetic (especially multiplication) is widely used for public key cryptography in protocols such as Transport Layer Security (TLS). A list of deductive methods relying on large integer arithmetic includes, but is not limited to, elliptic curve (EC) cryptography, which is used for elliptic curve Diffie-Hellman (ECDH) key exchange and elliptic curve digital signature deduction ( ECDSA) signature design; and module arithmetic deductive methods such as Asymmetric cryptography (Revest-Shamir-Adleman (RSA), Diffie-Hellman (DH), and digital security deduction ( DSA).

Due to the high efficiency of these deductive methods, elliptic curve cryptography (ECC) is now being extensively extended to implement perfect forward cryptography TSL communication. Currently, most EC-style signatures and key exchange deductions are performed on a 256 (or 255)-bit quality field. These EC-style techniques benefit greatly from fast 256-bit multiplication, such as the following.

An embodiment of the invention includes a new instruction that performs a multiplication of two 256-bit integers, produces a 512-bit result, and also performs a square of a 256-bit integer, yielding a 512-bit result. In addition, an embodiment of the present invention includes a limited addition of hardware to the existing 52 x 52->104 bit multiplier used in current architecture designs. For example, these multipliers can be found in a floating point multiply-add (FMA) unit in the existing x86 architecture currently used by the vpmadd52luq and vpmadd52huq instructions. Currently, the CNL/ICL server processor contains FMA hardware (埠1/5, with 4 cycles) Execution, with 1 cycle flux). Effectively, 16 multipliers and adders are available, but they are not exposed by the architecture.

As illustrated in FIG. 12, the illustrated processor 1255 is provided with a plurality of cores 0-N, and embodiments of the present invention can be implemented on the illustrated process 1255. In particular, each core includes a decode stage 1230 having 256-bit multiply instruction decode logic 1231 for decoding 256-bit multiply instructions into a number of micro-jobs executed by execution logic 1240. In particular, the illustrated processor 1255 also includes 256-bit multiply instruction execution logic 1241 for performing a 256-bit multiplication operation in accordance with an embodiment of the invention described below (e.g., using the multiplication described below with reference to Figure 16). And adder).

Further, each core 0-N includes a group of general purpose registers (GRP) 1205, a group of vector registers 1206, and a group of mask registers 1207. In one embodiment, a plurality of vector data elements are compacted in each vector register 1206, having a 512-bit width for storing two 256-bit values, four 128-bit values, and eight 64-bit elements. Value, sixteen 32-bit values, and so on. However, the basic principles of the invention are not limited to vector data of any particular size/type. In one embodiment, the mask register 1207 includes eight 64-bit operand mask registers for storing in the vector register 1206 (eg, implemented as the mask register k0-k7) The value in ) performs a bit mask job. However, the basic principles of the invention are not limited to any particular mask size/pattern.

For the sake of brevity, the details of a single processor core ("core 0") are shown in FIG. However, it will be understood that the one shown in Figure 12 Each core can have the same logical set as core 0. For example, each core also includes a dedicated level 1 (L1) cache memory 1212 and a level 2 (L2) cache memory 1211 for fetching instructions and data in accordance with a specified cache management policy. The L1 cache memory 1212 includes separate instruction cache memory 1220 for storing instructions, and a separate data cache memory 1221 for storing data. Commands and data stored in a wide variety of processor cache memories are managed at a granularity of cache lines that can be of fixed size (eg, lengths of 64, 128, and 512 bytes). Each core of the illustrated embodiment has an instruction extraction unit 1210 for extracting instructions from the main memory 1200 and/or the shared level 3 (L3) cache memory 1216, and a decoding unit 1220 for decoding the instructions ( For example, the program instructions are decoded into micro-jobs or "μop"; an execution unit 1240 for executing the instructions; and a write-back unit 1250 for exiting the instructions and writing back the results.

The instruction extraction unit 1210 includes various conventional components, and includes: a next instruction indicator 1203 for storing an address of a next instruction to be extracted from the memory 1200 (or one of the cache memories) An instruction translation look-aside buffer (ITLB) 1204 for storing a recently used virtual-to-physical instruction address mapping to enhance address translation speed; a branch prediction unit 1202 for speculatively predicting an instruction branch address; A branch identifier buffer (BTB) 1201 for storing the branch address and the target address. Once extracted, the instructions are then streamed to the remaining stages of the instruction pipeline including decode unit 1230, execution unit 1240, and write back unit 1250. The structure and function of each of these units is generally in the art. It is well known to those skilled in the art and will not be described in detail herein so as not to obscure the various aspects of the various embodiments of the invention.

In one embodiment, the following set of instructions is decoded and executed by 256-bit multiply instruction decode logic 1231 and 256-bit multiply instruction execution logic 1241.

1. VMUL256TO512 ZMM1, YMM2, YMM3: An embodiment of the present instruction multiplies the number of 256 bits in the source register ymm2 and ymm3 and stores the result of 512 bits in the destination vector register zmm1 ( All of these registers can be scratchpads within the group of vector registers 1206).

2. VMUL256TO512 ZMM1, ZMM2, ZMM3: An embodiment of the present instruction multiplies the source vector register zmm2 and the number of 256 bits in the lower half of zmm3 and stores the result of 512 bits in the destination vector. In zmm1.

3. VMUL256TO512 ZMM1, ZMM2, ZMM3, IMM8: An embodiment of the present instruction multiplies the number of 256 bits from the source vector register zmm2 and zmm3 and stores the result of 512 bits in the destination vector register. In zmm1. Using the immediate value, the multiplication is implemented according to the following definition: imm8=0x00->res=zmm2[255:0]*zmm3[255:0], imm8=0x10->res=zmm2[511:256]*zmm3[255 :0],imm8=0x01->res=zmm2[255:0]*zmm3[511:256],imm8=0x11->res=zmm2[511:256]*zmm3[511:256].

In other words, for an immediate value of 0x00, a 256-bit value is selected from the source vector register zmm2 and the bit 255:0 of zmm3. For 0x10 stand That is, the 256-bit value is selected from bits 511:256 of the source vector register zmm2 and the 256-bit value is selected from the bit 255:0 of the source vector register zmm3. For an immediate value of 0x01, a 256-bit value is selected from bits 511:256 of the source vector register zmm3 and a 256-bit value is selected from bits 255:0 of the source vector register zmm2. Finally, for an immediate value of 0x11, a 256-bit value is selected from the source vector register zmm2 and the bit 511:256 of zmm3.

13 shows an embodiment of the present invention for implementing a first variation of instructions in which 256-bit multiply logic 1300 stores a first 256-bit integer stored in a first 256-bit source register 1301 (eg, In one embodiment, YMM2) is multiplied by a second 256-bit integer (e.g., YMM3 in one embodiment) stored in a second 256-bit source register 1302. The multiplied result is stored in a 512-bit destination register 1303 (e.g., ZMM1 in one embodiment).

14 shows an embodiment of the present invention for implementing a second variation of instructions in which 256-bit multiply logic 1300 stores the first 256 in the lower half of the first 512-bit source vector register 1401. A bit integer (eg, encoded with bits 255:0 of ZMM2) and a second 256-bit integer stored in the second 512-bit source vector register 1402 (eg, encoded with bits 255:0 of ZMM3) ) Multiply. The multiplied result is stored in a 512-bit destination register 1303 (e.g., ZMM1 in one embodiment).

Figure 15 shows another embodiment of the invention for implementing a third variation of the instructions. In this embodiment, from the first source register 1401 and the second source In the lower or upper half of the register 1402, a 256-bit source operand is selected. In one embodiment, the 256-bit multiply logic selects 256-bit source operands from the lower or upper half of the registers 1401-1402 based on the immediate value 1500 (eg, imm8) provided with the instruction. As described above, if the immediate value is 0, the source operand is selected from the lower half of the two registers 1401-1402 (i.e., 255:0). If the immediate value is 1, the first source operand is selected from the upper half of the first source register 1401 (ie, 511:256) and the lower half of the second source register 1402 (ie, 255:0) Select the second source operand. If the immediate value is 2, the first source operand is selected from the lower half of the first source register 1401 (ie, 255:0) and the lower half of the second source register 1402 (ie, 511: 256) Select the second source operand. Finally, if the immediate value is 3, the source operand is selected from the upper half of the two registers 1401-1402 (i.e., 511:256).

Figure 16 shows an embodiment of 256-bit multiplication logic 1300 to perform the above-described operations. The following description assumes that the multiplication element is two 256-bit numbers A' and B'. Instead of treating the number as 4 digits in the base 264, they can be treated as 5 digits in the base 252. This allows multiplication to be performed in floating point execution units 1600, 1610, which in one embodiment can operate on the number of 52 bits (double the mantissa). In one embodiment, the same floating point unit is implemented, these same floating point units are currently used for integer operations for vpmadd52luq and vpmadd52huq x86 instructions. With this hardware, A' and B' can be determined as follows: A`=A4*2 ^52*4 +A3*2 ^52*3 +A2*2 ^52*2 +A1*2 ^52*1 +A0

B`=B4*2 ^52*4 +B3*2 ^52*3 +B2*2 ^52*2 +B1*2 ^52*1 +B0

In the present embodiment, A0, A1, A2, A3, and B0, B1, B2, and B3 are exactly 52 bits long, and A4 and B4 are 48-bit integers. Multiplying the above values for A' and B' results in the following: R = A4 * B4 * 2 ^{52 * 8} + (A4 * B3 + A3 * B4) * 2 ^{52 * 7} + (A4 * B2 + A3 * B3 + A2 * B4) * 2 52 * 6 + (A4 * B1 + A3 * B2 + A2 * B3 + A1 * B4) * 2 52 * 5 + (A4 * B0 + A3 * B1 + A2 * B2 + A1 *B3+A0*B4)*2 ^52*4 +(A3*B0+A2*B1+A1*B2+A0*B3)*2 ^52*3 +(A2*B0+A1*B1+A0*B2)* 2 ^52*2 +(A1*B0+A0*B1)*2 ^52*1 +A0*B0

Among them, each coefficient can reach 107 bits long.

The purpose of the instructions is thus to calculate the coefficients and then sum them correctly to produce R'=R expressed in 512 bits (number base 264). For this purpose, an embodiment of the present invention introduces four new micro-ops (μops): mulassist1, mulassist2, mulassist3, and mulassist4: mulassist1/2/3/4 tmpzmm, a256, b256

In operation, each mulassist* μops first converts the input operand a256/b256 into a base 252 representation (eg, using routing and selection logic). Each mulassist* μops then calculates a 4 x 105 bit value. Each of the four values is stored in the 128-bit track of the resulting scratchpad as described below.

Mulussist1:(A0B3+A1B2)∥(A0B2+A1B1)∥(A0B1+A1B0)∥(A0B0)

Mulassist2:(A2B3+A1B4)∥(A1B3+A0B4)∥(A3B0+A2B1)∥(A2B0)

Mulassist3:(A3B1+A2B2)∥(A4B1+A3B2)∥(A4B1+A3B2)∥(A4B3+A3B4)

Mulassist4: (A4B0) ∥ (A2B4) ∥ (A4B4) ∥ 0

In the above representation, each 128-bit track is separated by a ∥ identifier. Lane 0 is the rightmost lane, lane 3 is the leftmost lane, and lanes 2 and 1 are arranged in sequence. Between us.

In one embodiment, multiplication and addition uses floating point multiply-add (FMA) units available on execution 埠0 and 5 in execution unit 1240. Of course, the basic principles of the invention are not limited to any particular set of executions. In some implementations, for example, the FMA unit can be taken on other ports.

Figure 16 shows a particular manner of performing a job for mulassist1 using a set of multiplying units 1600 and adders 1610. Although only the details for mulassist1 are shown, the same basic principles can be applied to mulassist2, mulassist3, and mulassist4.

As shown in FIG. 16, A1 and B2 are multiplied using the A and B values provided above, 52x52 bit multiplier 1601; multiplier 1602 multiplies A0 and B3; multiplier 1603 multiplies A1 and B1; multiplier 1604 multiplies A0 and B2; multiplier 1605 multiplies A1 and B0; multiplier 1606 multiplies A0 and B1; and multiplier 1607 multiplies A0 and B0.

Then, the 104 x 104 adder 1611 determines the sum of A1B2 and A0B3 and outputs the result to 128-bit track 3; the adder 1612 then determines the sum of A1B1 and A0B2 and outputs the result to 128-bit track 2; adder 1613 determines the sum of A1B0 and A0B1 and outputs the result to 128-bit track 1; adder 1614 determines the sum of the values of A0B0 and 0 to output the result A0B0 to 128-bit track 0.

In one embodiment, the four results are then summed and converted into regular representations via added hardware and micro-jobs. Note that it can be designed according to Consider and modify the true order of the operands.

Figure 17 shows a method in accordance with an embodiment of the present invention. The method can be implemented within the above architecture, but is not limited to any particular architecture.

At 1701, a 256-bit multiply instruction is fetched from the memory or read from the cache memory (for example, vmul256to512 zmm1, zmm2, zmm3, imm8, or one of the other instructions highlighted above). At 1702, the first and second 256-bit integer operands are stored in the first and second source registers, respectively. For example, if the source operand register is a 512-bit vector register (eg, ZMM2), the first and second 256-bit integer source operands can be stored in the upper or lower half of the scratchpad ( For example, according to the value of imm8 in the above embodiment).

At 1703, the first and second source operands are converted from the first base representation to the second base representation based on the size of the multiplier and adder hardware. For example, as described above, for implementations using a 52-bit multiplier, instead of treating the number as 4 digits in the number base 264, treat them as 5 digits in the base 252. At 1704, a series of multiplications and additions are performed using the second base representation to achieve the result (see, for example, Figure 16 and related description). Finally, at 1705, the result is converted back to the first base representation (eg, and stored in a 512-bit destination register).

In the foregoing specification, embodiments of the invention are described with reference However, it is apparent that various modifications and changes can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded as

Embodiments of the invention include the various steps described above. The steps may be embodied in machine-executable instructions that may be used to cause a general purpose or special purpose processor to perform the steps. Alternatively, these steps can be performed by a particular hardware component containing logic for performing physical wiring of the steps, or any combination of stylized computer components and customized hardware components.

As described herein, an instruction means a specific configuration of a hardware such as an application specific integrated circuit (ASIC), which is configured to execute certain jobs having a predetermined function or software instructions stored in a memory, a memory system The implementation of non-transitory computer readable media. Thus, the techniques shown in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., terminal stations, network elements, etc.). These electronic devices use computer readable media to store and communicate (internal and/or via a network to communicate with other electronic devices) code and data. The computer readable media can be, for example, a non-transitory computer machine - Read storage media (eg disk; CD; random access memory; read-only memory; flash memory device; phase change memory) and temporary computer readable communication media (eg electrical, optical) , audible or other forms of propagation signals - such as carrier waves, infrared signals, digital signals, etc.). Moreover, these electronic devices typically include one or more processors coupled to one or more other components, one or more other components can be, for example, one or more storage devices (non-transitory machine readable storage media) ), user input/output devices (such as keyboards, touch screens, and/or displays), and network connections. The coupling of the processor bank and other components is typically via one or more Multiple busbars and bridges (also known as busbar controllers). The storage devices and signals carrying the network traffic represent one or more machine readable storage media and machine readable communication media, respectively. Thus, a storage device of a given electronic device typically stores code and/or data for execution on a group of one or more processors of the electronic device. Of course, one or more of the embodiments of the invention may be practiced using different combinations of software, firmware, and/or hardware. In the detailed description, for the purposes of illustration However, it will be apparent to those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well-known structures and functions are not described in detail to avoid obscuring the subject matter of the invention. Therefore, the scope and spirit of the invention should be judged from the point of view of the appended claims.

300‧‧‧Scratchpad Architecture

310‧‧‧Vector register

315‧‧‧Write mask register

325‧‧‧General Purpose Register

345‧‧‧Simplified floating point stack register file

350‧‧‧MMX Compact Integer Flat Register File

Claims (23)

A processor for performing a large integer arithmetic operation, comprising: a first source register for storing a first 256-bit integer operation element; and a second source register for storing a second 256-bit integer operation And the first and second source registers include a 512-bit vector register, and wherein the first and second 256-bit integer operands are stored in the 512-bit vector register And the multiplication logic includes: a multiplier and an adder group for performing multiplication of the first and second 256-bit integer operands to generate a result of 512 bits in response to 256 bits a multiplication instruction, the multiplication logic, based on the size of the multipliers and adders used to perform the multiplication and the generation, the first and second 256-bit integer operands are represented from the first The number base representation is converted to the selected second number base representation, and the result is then converted back to the first number base representation. The processor of claim 1, wherein the first number base representation of each of the 256-bit integer operands comprises four digits represented in the number base ⁶⁴ . The processor of claim 2, wherein the second number base comprises five digits represented by the number base ⁵² . The processor of claim 3, wherein each of the multipliers comprises a 52x52 multiplier. The processor of claim 4, wherein each of the multipliers multiplies one of the five digits from the first 256-bit integer operand by the second 256-bit integer operand Among the five digits One. The processor of claim 5, wherein the bits A0, A1, A2, A3, and A4 from the first 256-bit integer operand and the bits from the second 256-bit integer operand are Number B0, B1, B2, B3, and B4: the first multiplier is used to multiply A1 and B2 to produce a product A1B2; the second multiplier is used to multiply A0 and B3 to produce a product A0B3; the third multiplier is used to A1 and B1 are multiplied to produce a product A1B1; a fourth multiplier is used to multiply A0 and B2 to produce a product A0B2; a fifth multiplier is used to multiply A1 and B0 to produce a product A1B0; a sixth multiplier is used to A0 and B1 is multiplied to produce a product A0B1; and a seventh multiplier is used to multiply A0 and B0 to produce a product A0B0. The processor of claim 6, wherein each of the adders adds at least two of the results output by the multipliers. The processor of claim 7, further comprising: a first adder for determining a first sum of A1B2 and A0B3; and a second adder for determining a second sum of A1B1 and A1B2; An adder for determining a third sum of A1B0 and A1B1; and a fourth adder for determining a fourth sum of A0B0 and 0. For example, the processor of claim 8 wherein each of the four sums is output to each of four different 128-bit channels. The processor of claim 9, wherein the four summaries in each of the 128 bit channels are summed and converted into a number base 2 ⁶⁴ . A processor as claimed in claim 1, wherein the multiplication logic comprises decoding logic to decode the 256-bit multiplication instruction into a plurality of micro-jobs, the plurality of micro-jobs using the second base representation to perform a plurality of multiplications and summing The result is a 512-bit result. The processor of claim 1, wherein the immediate value of the 256-bit multiply instruction indicates whether the first and second 256-bit integer operands are respectively stored in the first and second 512-bit vectors. In the upper or lower half of the register. A method for performing a large integer arithmetic operation includes: storing a first 256-bit integer operation element in a first source register; and storing a second 256-bit integer operation element in a second source register The first and second source registers include a 512-bit vector register, and wherein the first and second 256-bit integer operands are stored in the 512-bit vector register In the upper or lower region; and using the multiplier and the adder group, the number bases of the first and second 256-bit integer operands are based on the sizes of the multipliers and adders used to perform the multiplication and the result of the generation Representing conversion from a first number base representation to a second number base representation, performing multiplication of the first and second 256-bit integer operands, and then converting the result back to the first base representation. The method of claim 13, wherein the first number base representation of each of the 256-bit integer operands comprises four digits represented in the number base ⁶⁴ . The processor of claim 14, wherein the second number base comprises five digits represented by the number base ⁵² . The method of claim 15, wherein each of the multipliers comprises a 52x52 multiplier. The method of claim 16, wherein each of the multipliers multiplies one of the five digits from the first 256-bit integer operand by the second 256-bit integer operand. One of five digits. The method of claim 17, wherein the number of bits A0, A1, A2, A3, and A4 from the first 256-bit integer operand and the number of bits from the second 256-bit integer operand B0, B1, B2, B3, and B4, the method further comprises: multiplying A1 and B2 to produce a product A1B2; multiplying A0 and B3 to produce a product A0B3; multiplying A1 and B1 to produce a product A1B1; A0 and B2 are multiplied to produce a product A0B2; A1 and B0 are multiplied to produce a product A1B0; A0 and B1 are multiplied to produce a product A0B1; and A0 and B0 are multiplied to produce a product A0B0. The method of claim 18, wherein each of the adders adds at least two of the results output by the multipliers. The processor of claim 19, further comprising: determining a first sum of A1B2 and A0B3; determining a second sum of A1B1 and A1B2; Determine the third sum of A1B0 and A1B1; and determine the fourth sum of A0B0 and 0. The method of claim 20, wherein each of the four sums is output to each of four different 128-bit channels. The method of claim 21, wherein the four summaries in each of the 128 bit channels are summed and converted into a number base 2 ⁶⁴ . As in the method of claim 13, the 256-bit multiply instruction is decoded into a plurality of micro-jobs for generating a 512-bit result using a second number base representation to perform a plurality of multiplication and summation operations.