TWI599163B - A semiconductor chip - Google Patents

Description

Semiconductor wafer

The present invention relates to a tuner module wafer, and more particularly to a semiconductor wafer having a tuner and a transimpedance amplifier (TIA).

Today's fiber-optic communication networks have become the trend of developing broadband communications. For example, fiber-to-the-home or fiber-to-building fiber-to-point development is the goal of fiber-optic communication networks to gradually replace the original copper transmission.

At present, optical cable TV (Optical CATV) has become one of the transmission media of mainstream media, but now that TV information transmission volume is getting larger and users are more demanding on the network, the transmission data of optical fiber The amount has gradually disappeared. In order to solve the problem of insufficient data transmission, in addition to improving the fiber transmission speed, the receiving and transmitting of the fiber ends are also very important, especially the volume and manufacturing cost of the receiving device are more important points to be improved.

The main object of the present invention is to provide a semiconductor wafer in which a transimpedance amplifier and a tuner are integrated on a semiconductor wafer, and the circuit can be modularly designed to avoid poor matching between the two. In turn, the circuit design difficulty and cost are reduced, and the integration of the two on one wafer can reduce the production cost and reduce the volume of the optical transmission component.

In order to achieve the above object, the present invention provides a semiconductor wafer including a transimpedance amplifier having a first input adapted to be coupled to a first output of an optical receiver, wherein the transimpedance amplifier is The input generates a signal outputted by the second output of the transimpedance amplifier; and a tuner having a second input coupled to the second output for modulating the signal, wherein the transimpedance amplifier and the tuning The device is disposed on a single semiconductor wafer, and the transimpedance amplifier and the tuner are integrated circuits on a single semiconductor wafer.

These and other components, steps, features, advantages and advantages of the present invention will become apparent from the description of the appended claims.

The drawings disclose illustrative embodiments of the invention. It does not describe all of the embodiments. Other embodiments may be used in addition or instead. In order to save space or more effectively explain, obvious or unnecessary details may be omitted. Instead, some embodiments may be implemented without revealing all the details. When the same number or label appears in a different figure, it refers to the same or similar components or steps. The invention will be more fully understood from the following description, taken in conjunction with the accompanying drawings.

Referring to FIG. 1a, the tuner module chip 100 of the present invention can receive a signal transmitted by a light receiving component 200. The tuner module wafer 100 is a semiconductor wafer, and the light receiving component 200 is a semiconductor. One of a wafer or a SiGe semiconductor wafer, and the light receiving element 200 is, for example, a light-receiving diode, a high-frequency diode, an avalanche photodiode, a photosensitive coupling unit, or a complementary metal oxide semiconductor unit. One of the preferred embodiments of the light receiving element 200 of the present invention is a light collecting diode. The tuner module chip 100 includes an amplifier 10 and a tuner 30, wherein the amplifier is, for example, a transimpedance amplifier (TIA). The preferred embodiment of the amplifier 10 of the present invention is a transimpedance amplifier. Additionally, the amplifier 10 can include a differential input amplifier or a single-ended input amplifier. The preferred embodiment of the amplifier 10 of the present invention is a differential input amplifier.

The light receiving component 200 includes a light receiver 20 (for example, a light-receiving diode). One positive terminal and one negative terminal of the optical receiver 20 are respectively coupled to a ground terminal (Vss) and a power voltage terminal (Vdd). And an inductive component 22 is coupled between the positive terminal and the ground terminal (Vss) and between the negative terminal and the power supply voltage terminal (Vdd), and the first input terminal 102 and a second input of the amplifier 10 are respectively The terminals 104 are respectively coupled to the positive terminal and the negative terminal of the optical receiver 20 in the light receiving component 200. The inductive component 22 can be regarded as a low pass filter for eliminating noise. When the optical receiver 20 (for example, the light-receiving diode) receives an optical signal, the depletion region in the wafer generates an electron hole pair, and the reverse biased electric field drives the electron holes to move toward the N and P poles. thus generates a current signal, and the amplifier 10 converts the current signal arising from the light receiver 20 to a voltage difference value, the amplifier 10 generates an output signal V _o is transmitted to the tuner (tuner) according to one of the voltage difference 30 The signal receiving end 30a, the tuner 30 can change the output signal _Vo and output an output signal to an external component.

The above-mentioned optical receiver 20 of the present invention is differentially outputted into the amplifier 10. However, the optical receiver 20 can also be outputted to the amplifier 10 at a single end. Please refer to FIG. 1b and FIG. 1c, and FIG. 1b. The output of the photoreceiver 20 is between the negative terminal and the supply voltage terminal (Vdd), and the output of the photoreceiver 20 in Fig. 1c is between the positive terminal and the ground terminal (Vss).

A circuit diagram of the amplifier 10 is shown in FIG. 2. A first input terminal (Inp) 10a and a second input terminal (Inn) 10b of the amplifier 10 are respectively coupled to a capacitor unit 106a and a capacitor unit 106b. The capacitor unit 106a is coupled to a capacitor unit 106a. The first switch unit 118a is coupled to a channel of a first switch unit 118a and an inductor unit 110a. The first switch unit 118a is, for example, an N-type MOSFET or a P-type MOSFET. The first switching unit 118a of the present invention is described by an N-type metal oxide half field effect transistor (NMOS), so the capacitor unit 106a is coupled to the source channel of the N-type metal oxide half field effect transistor (NMOS). The other end of the inductor unit 110a is coupled to the ground terminal (Vss), and the capacitor unit 106b is coupled to the channel of a second switch unit 118b and an inductor unit 110b, wherein the second switch unit 118b is an N-type gold-oxygen half field. The effect transistor (NMOS) is described. Therefore, the capacitor unit 106b is coupled to the source channel of the N-type metal oxide half field effect transistor (NMOS), and the other end of the inductor unit 110b is coupled to the ground terminal (Vss). An output terminal (Outp) 10c of the amplifier 10 is coupled to the channel of the first switching unit 118a and a resistor unit 116a. For example, the output terminal 10c is coupled to the drain of the N-type metal oxide half field effect transistor (NMOS). The channel and the resistor unit 116a, and the other end of the resistor unit 116a is coupled to the power supply voltage terminal (Vdd), that is, the resistor unit 116a is coupled between the power supply voltage terminal (Vdd) and the first output terminal 10c, and is located at the power supply voltage. A resistor unit 116b is coupled between the terminal (Vdd) and the channel of the second switch unit 118b. The resistor unit 116b is coupled to the drain channel of the second switch unit 118b. In this embodiment, the capacitor units 106a, 106b, the inductive units 110a, 110b and the resistor units 116a, 116b are a load, wherein the capacitor units 106a, 106b and the inductive units 110a, 110b can be regarded as low-pass filters for being responsible for Eliminate noise.

As shown in FIG. 2 and FIG. 3, the tuner module chip 100 further includes an automatic gain control (AGC) circuit 40. The first switching unit 118a of the amplifier 10 of FIG. 2 is coupled to The automatic gain control circuit 40, that is, the gate channel of the first switching unit 118a (N-type metal oxide half field effect transistor) is coupled to one of the output terminals 40a of the automatic gain control circuit 40, and the automatic gain control circuit The input terminal 40b is coupled to the output terminal 10c of the amplifier 10. The automatic gain control circuit 40 adjusts the voltage of the output terminal 40a according to the output signal of the input terminal 40b. The automatic gain control circuit 40 is operative to automatically adjust the gain of the amplifier 10 automatically with the input signal strength of the automatic gain control circuit 40.

Please refer to FIG. 4, which is a circuit diagram of the tuner 30. The tuner 30 includes: a. a low noise amplifier (LNA) 302 bit signal at the tuner 30. The downstream end of the receiving end 30a, wherein the low noise amplifier amplifier comprises a single-ended to differential amplifier or a differential to differential amplifier, and the low noise amplifier 302 can receive the output signal V received by the tuner 30. _o amplifying; b. a first filter 304 is located at the downstream end of the low noise amplifier 302, wherein the first filter 304 is, for example, a band-pass filter, and the first filter 304 can The low noise amplifier 302 amplifies the signal filtering to remove the noise, for example, to remove the image signal; c. The second mixers 306a, 306b are located at the downstream end of the filter 304, wherein the second mixer 306a 306b is, for example, a frequency-down converters, and the mixers 306a, 306b can be used to convert a radio frequency collected signal into an intermediate frequency collected signal; d. Modulation 314 bits in the second mixer 306a, 306b The upstream end is coupled to a local oscillator 316, wherein the modulator 314 is, for example, an in-phase/quadrature modulator, and the first output of the modulator 314 is coupled to the hybrid The second output of the modulator 314 is coupled to the mixer 306b, wherein the first output and the second output of the modulator 314 have a phase difference of 90 degrees and the frequency is the same. The mixer 306a mixes the signal according to the first output of the modulator 314 to generate a first mixed signal, and the mixer 306b mixes the signal according to the second output of the modulator 314 to generate a second The mixed signal, wherein the first mixed signal and the second mixed signal are two orthogonal signals, that is, the phase difference between the first mixed signal and the second mixed signal is 90 degrees; e. Gain-amplifiers (VGA) 308a, 308b are respectively located at the downstream of the two mixers 306a, 306b, wherein the first variable gain amplifiers 308a, 308b comprise a single-ended to differential amplifier or a differential To one of the differential amplifiers, the first variable gain amplifiers 308a, 308b can adjust the first mixed The signal and the second mixed signal are voltage amplified; f. a second filter 310a is located at a downstream end of the first variable gain amplifier 308a, 308b, wherein the second filter 310a is, for example, an image suppression filter (Image Rejection Filter), the second filter 310a receives the output signals of the first variable gain amplifiers 308a, 308b and solves the problem of the image signal, and removes the noise; g. an input end of the third filter 310b is coupled An output of the second filter 310a, the third filter 310b may perform filtering on the input of the third filter 310b (eg, the signal output by the second filter 310a) to generate an output (eg, a predetermined channel or The signal in the frequency). The third filter 310b may be a channel selection filter that filters out or selects a signal carried in a predetermined channel or frequency; h. a second variable gain amplifier (VGA) 312a bit At a downstream end of the third filter 310b, wherein the second variable gain amplifier 312a includes one of a single-ended to differential amplifier or a differential to differential amplifier, and the second variable gain amplifier 312a can be third The filtered signal of the filter 310b is amplified and transmitted to the output terminal Vo of the tuner 30, whereby the output terminal Vo outputs the modulated signal to an external component; i. The Power Detector 318 is coupled respectively. An output of the first variable gain amplifier 308a, 308b and an output coupled to the first filter 304; a DC offset canceller 320 coupled to the output of the second variable gain amplifier 312a, and coupled The input end of the third filter 310b, wherein the DC offset canceller 320 is configured to cancel the DC offset voltage component generated by the signal path of the second filter 310a to the second variable gain amplifier 312a; k. Frequency synthesizer 322 coupler An oscillator 324 other than the tuner module chip 100, the oscillator 324 may have a quartz crystal for generating a reference clock signal to the frequency synthesizer 322, or the oscillator 324 may be The RLC circuit replaces the quartz crystal to generate a reference clock signal to the frequency synthesizer 322. The RLC circuit is composed of a plurality of resistive elements, a plurality of inductive elements, and a plurality of capacitors, and the RLC circuit is built in the tuner module chip 100; A frequency synthesizer 322 is coupled to the modulator 314 via a coupled local oscillator 316, wherein the frequency synthesizer 322 is, for example, a non-integer phase-locked loop (fractional-N PLL) for generating a The clock signal is synthesized, wherein the frequency of the synthesized clock signal is an integer multiple of the reference clock signal frequency generated by the oscillator 324, wherein the frequency of the synthesized clock signal can be controlled by the voltage or current of the input end of the frequency synthesizer 322. The local oscillator 316 generates another clock signal according to the synthesized clock signal generated by the frequency synthesizer 322 to the modulator 314. The modulator 314 combines the second signal according to the pulse signal at this time. The signals processed by the 306a, 306b are modulated into two orthogonal first mixed signals and second mixed signals.

In addition, a plurality of inductive components 50 can be coupled between the power supply voltage terminal Vdd and the first filter 304 for reducing background noise, wherein the inductive component 50 is built into the tuner module chip 100, or is tuned. An inductive component other than the module die 100. In addition, the tuner module chip 100 further includes a serial communication bus unit 326 for providing an inter-chip synchronous serial communication interface to couple other chips (or systems) for each chip. An additional clock line can be used to synchronize the clocks of the respective chips (or systems), wherein the serial communication bus unit 326 is, for example, an inter integrated chip (I2C), a string. One of the Serial Peripheral Interface Bus (SPI) or microwire interface, the preferred embodiment of the serial communication bus unit 326 of the present invention is illustrated by an internal integrated circuit (I2C). In addition, the tuner module chip 100 further includes a loop-through amplifier 328 coupled between the signal receiving end 30a and the low noise amplifier 302 for using the amplifier 10 (for example, a transimpedance amplifier (TIA). The transmitted signal is further amplified and output to other receiving devices, wherein the loop-through amplifier 328 includes a single-ended to differential amplifier or a differential to differential amplifier. In addition, the tuner module chip 100 further includes a voltage regulator 330 for providing a constant voltage of the tuner module chip 100 during operation, for example, providing a stable voltage to one of the amplifiers 10. The voltage terminal (Vdd) and one of the power supply voltage terminals (Vdd) of the tuner module chip 100, wherein the voltage regulator 330 is, for example, a low dropout regulator (LDO).

Referring to FIG. 5, the tuner module chip 100 can be disposed on a circuit substrate 600. The tuner module chip 100 has a metal pad 101, which can be wired. The metal wire 60 is electrically connected to one of the metal pads 62 of the circuit substrate 600. The metal wire 60 is made of one of gold, copper or silver and formed on the circuit substrate 600 and the tuner module chip 100. A polymer layer 64 covers and protects the tuner module wafer 100 and the metal wires 60. The circuit substrate 600 is, for example, a ceramic substrate, a metal substrate, a lead frame substrate or a printed circuit board, wherein the ceramic substrate comprises alumina. One of (Al ₂ O ₃ ) substrate, aluminum nitride (AlN) substrate or beryllium oxide (BeO) substrate, and one or more passive components (not shown) may be disposed on the circuit substrate 600 and electrically The metal pad 62 is connected to the circuit substrate 600. The passive component is, for example, a resistive component, a variable resistive component, a thermistor component, a capacitive component or an inductive component or a combination thereof.

FIG. 6 illustrates a pin configuration diagram of the tuner module wafer 100 of the present invention. The tuner module chip 100 package includes two pins RFinp and pins RFinn respectively coupled to the two input terminals 10a, 10b of the amplifier 10, wherein the pin GND is between the pin RFinp and the pin RFinn. The pin RFinp and the pin RFinn are separated, wherein the pin GND is a ground (Ground), and the pin RFinp and the pin RFinn bit are on the same side (the same side) of the tuner module chip 100, and The pin GND between the pin RFinp and the pin RFinn can also be replaced with a pin PWR (power) or replaced with an empty pin (inactive pin); the tuner module chip 100 further includes two leads The pins Vo1 and Vo2 are respectively coupled to the two output terminals Vo1 Vo2 of the tuner 30, wherein the pin GND is between the pins Vo1 and Vo2, and the pins Vo1 and Vo2 are separated, and the pins Vo1 and Vo2 are located at The tuner module chip 100 is packaged on the same side (the same side), and the pin GND between the pins Vo1 and Vo2 can also be replaced with a pin PWR (power) or replaced with an empty pin (no effect) The tuner module chip 100 may further include a plurality of pins GND coupled to the ground contact of the amplifier 10, the automatic gain control circuit 40, and the tuner 30, or Coupled to a ground reference of the tuner module chip 100, the pin GND can provide a ground voltage to the amplifier 10, the automatic gain control circuit 40 and the tuner 30; the tuner module chip 100 can further include The pin VDD5V is used to input a 5V power supply and is converted to a 3.7V voltage to be output from the pin LDO. The 3.7V voltage of the pin LDO output is directly supplied to the complex pin VIN and coupled to the amplifier 10 and the automatic gain control circuit 40. And a power contact of the tuner 30 for supplying the amplifier 10, the automatic gain control circuit 40 and the tuner 30 power supply; the tuner module chip 100 further includes a pin AVDDRX as an internal alternating current (internal alternate-current (internal alternate-current (internal alternate-current (internal alternate-current (internal alternate-current (internal alternate-current AC) ground).

After receiving the optical signal through the light receiving component 200, the present invention generates a current signal, and then converts the current signal into a voltage signal input to the tuner module chip 100 via the amplifier 10 (transimpedance amplifier), and then passes through the tuner module chip 100. The limiting amplifier 328 and the low noise amplifier 320 further amplify the voltage signal transmitted by the amplifier 10, remove the noise through the first filter 304, and then the mixers 306a, 306b via the modulator 314. The processed signal is modulated into two orthogonal first mixed signal and second mixed signal (phase difference is 90 degrees), and then the signal is amplified by the first variable gain amplifiers 308a, 308b, and the second filter is used. 310a filters, removes the noise, filters out or selects a signal carried in a predetermined channel or frequency by the third filter 310b, and finally amplifies the signal by the second variable gain amplifier 312a, 312b and outputs the signal to the tuning. The output of the device 30 is Vo.

The invention integrates the tuner 30 and the amplifier 10 (for example, a transimpedance amplifier) on a chip, and can modularly design the circuit to avoid the poor matching between the two, thereby making the circuit design difficult and cost lower. In addition, the integration of the two on one wafer can reduce the production cost and reduce the volume of the optical transmission component.

The above description of the embodiments of the present invention is intended to be understood by those skilled in the art, and the invention may be practiced without departing from the scope of the invention. Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the claims described below.

100‧‧‧ Tuner Module Wafer
200‧‧‧Light receiving components
10‧‧‧Amplifier
30‧‧‧ Tuner
20‧‧‧Optical Receiver
102‧‧‧ first input
104‧‧‧second input
30a‧‧‧Signal Receiver
10a‧‧‧ first input
10b‧‧‧second input
106a‧‧‧Capacitor unit
106b‧‧‧Capacitor unit
118a‧‧‧First switch unit
118b‧‧‧Second switch unit
110b‧‧‧Inductance unit
10c‧‧‧output
116a‧‧‧Resistance unit
110a‧‧‧Inductance unit
116b‧‧‧Resistance unit
40‧‧‧Automatic gain control circuit
40a‧‧‧output
40b‧‧‧ input
302‧‧‧Low noise amplifier
304‧‧‧First filter
306a‧‧‧Mixer
306b‧‧‧Mixer
314‧‧‧Transformer
316‧‧‧Local Oscillator
308a‧‧‧First Variable Gain Amplifier
308b‧‧‧First Variable Gain Amplifier
310a‧‧‧second filter
310b‧‧‧ third filter
312a‧‧‧Second variable gain amplifier
312b‧‧‧Second variable gain amplifier
318‧‧‧Power Detector
320‧‧‧DC offset canceller
322‧‧‧ frequency synthesizer
324‧‧‧Oscillator
50‧‧‧Inductive components
326‧‧‧Serial communication bus unit
328‧‧‧Circuit amplifier
330‧‧‧Voltage regulator
600‧‧‧ circuit substrate
101‧‧‧Metal pads
60‧‧‧Metal wire
62‧‧‧Metal pads
64‧‧‧ polymer layer

Figure 1a is a circuit diagram of the tuner module wafer of the present invention and the first type of light receiving wafer. Figure 1b is a circuit diagram of the tuner module wafer and the second light receiving wafer of the present invention. Figure 1c is a circuit diagram of the tuner module wafer and the third light receiving wafer of the present invention. Figure 2 is a circuit diagram of the transimpedance amplifier of the present invention. Figure 3 is a circuit diagram of another tuner module chip and a light receiving wafer of the present invention. Figure 4 is a circuit diagram of the tuner of the present invention. FIG. 5 is a schematic view showing the package structure of the tuner module chip of the present invention. Figure 6 is a diagram showing the pin configuration of the tuner module chip of the present invention.

While certain embodiments have been illustrated in the drawings, the embodiments of the invention And other embodiments described herein.

20‧‧‧Optical Receiver

100‧‧‧ Tuner Module Wafer

200‧‧‧Light receiving components

30a‧‧‧Signal Receiver

102‧‧‧ first input

104‧‧‧second input

10‧‧‧Amplifier

40‧‧‧Automatic gain control circuit

30‧‧‧ Tuner

40a‧‧‧output

40b‧‧‧ input

Claims (10)

A semiconductor wafer comprising: a transimpedance amplifier having a first input adapted to be coupled to a first output of an optical receiver, the first output outputting a current signal to the first input, wherein the transimpedance amplifier Generating a first signal according to the current signal converted to a voltage difference, and outputting a second output of the transimpedance amplifier; and a tuner having a second input coupled to the second output, including a first a mixer, a second mixer, a variable gain amplifier, a first filter and a second filter, the first mixer having a third input and a fourth input, the third input Related to the second input, the second mixer has a fifth input and a sixth input, the fifth input is related to the second input, and the first mixer and the second mixer modulate the first The first filter generates a first mixed signal and a second mixed signal, the first filter receives the first mixed signal and the second mixed signal and removes noise, and the second filter receives the first The signal transmitted by the filter is filtered and generated a variable gain amplifier of a predetermined signal or a second signal to a downstream end, the variable gain amplifier amplifying the received signal to an external component, wherein the transimpedance amplifier and the tuner are disposed in a single semiconductor On the wafer, the transimpedance amplifier and the tuner are integrated circuits on a single semiconductor wafer. The semiconductor wafer of claim 1, wherein the tuner includes an amplifier coupled to the second input for amplifying the signal. The semiconductor wafer of claim 1, wherein the tuner further includes a modulator, wherein the first signal is modulated by the fourth input and the sixth input respectively to generate the first mixed signal and the second mixed Wave signal. The semiconductor wafer of claim 1, wherein the tuner further comprises a loop-through (LT) amplifier having a third input coupled to the second output for amplifying the signal. The semiconductor wafer of claim 1, wherein the first output is a differential output and the first input is a differential input. The semiconductor chip of claim 1 may be disposed in a package module. One side of the package module includes a first input pin and a second input pin, and the first input pin is connected to the first input pin. There is a third pin between the foot and the second input pin, and the third pin is one of a ground pin, a power pin or an empty pin. A semiconductor wafer comprising: a transimpedance amplifier having a first differential input adapted to be coupled to a first differential output of an optical receiver, the first differential output outputting a current signal to the first difference a translating amplifier, wherein the transimpedance amplifier generates a first signal according to the current signal converted to a voltage difference, and outputs a second output of the transimpedance amplifier; and a tuner having a second input coupled to the The second output includes a first mixer, a second mixer, a variable gain amplifier, a first filter and a second filter, the first mixer having a third input and a first a fourth input, the third input is related to the second input, the second mixer has a fifth input and a sixth input, the fifth input is related to the second input, the first mixer and the first The second mixer modulates the first signal to generate a first mixed signal and a second mixed signal, and the first filter receives the first mixed signal and the second mixed signal and removes noise, The second filter receives the signal transmitted by the first filter Filter, generates a predetermined frequency channel or in a second signal to the downstream end of the variable gain amplifier, the variable gain amplifier receiving the input signal amplifier An external component is disposed, wherein the transimpedance amplifier and the tuner are disposed on a single semiconductor wafer, and the transimpedance amplifier and the tuner are integrated circuits on a single semiconductor wafer. The semiconductor chip of claim 7 may be disposed in a package module. One side of the package module includes a first input pin and a second input pin, and the first input pin is connected to the first input pin. There is a third pin between the foot and the second input pin, and the third pin is one of a ground pin, a power pin or an empty pin. The semiconductor wafer of claim 7, wherein the tuner further includes a modulator that modulates the first signal via the fourth input and the sixth input to generate the first mixed signal and the second mixed Wave signal. The semiconductor wafer of claim 7, wherein the tuner further comprises a loop-through (LT) amplifier having a third input coupled to the second output for amplifying the signal.