TWI599163B - A semiconductor chip - Google Patents
A semiconductor chip Download PDFInfo
- Publication number
- TWI599163B TWI599163B TW105115879A TW105115879A TWI599163B TW I599163 B TWI599163 B TW I599163B TW 105115879 A TW105115879 A TW 105115879A TW 105115879 A TW105115879 A TW 105115879A TW I599163 B TWI599163 B TW I599163B
- Authority
- TW
- Taiwan
- Prior art keywords
- input
- signal
- pin
- amplifier
- tuner
- Prior art date
Links
Landscapes
- Amplifiers (AREA)
Description
本發明係有關一種調諧器模組晶片,尤其指一種同時具有調諧器及轉阻放大器(transimpedence amplifier, TIA)之半導體晶片。The present invention relates to a tuner module wafer, and more particularly to a semiconductor wafer having a tuner and a transimpedance amplifier (TIA).
現今光纖通信網路成為發展寬頻通信的趨勢。例如光纖到家或光纖到建築物等光纖到點之發展是光纖通信網路發展的目標,以逐步取代原有的銅線傳輸。Today's fiber-optic communication networks have become the trend of developing broadband communications. For example, fiber-to-the-home or fiber-to-building fiber-to-point development is the goal of fiber-optic communication networks to gradually replace the original copper transmission.
在目前光纖到府的有線電視(Optical CATV)己成為主流媒體的傳輸媒介之一,但是現在TV資訊傳輸量越來越大且使用者對網路要求更為快速的情形下,光纖的傳輸數據量已逐漸不敷使用。為了因應傳輸數據量不敷使用的問題,除了改善光纖傳遞速度以外,光纖兩端的接收與傳輸亦顯得相當重要,尤其是接收端裝置的體積及製作成本更是需要改善的要點。At present, optical cable TV (Optical CATV) has become one of the transmission media of mainstream media, but now that TV information transmission volume is getting larger and users are more demanding on the network, the transmission data of optical fiber The amount has gradually disappeared. In order to solve the problem of insufficient data transmission, in addition to improving the fiber transmission speed, the receiving and transmitting of the fiber ends are also very important, especially the volume and manufacturing cost of the receiving device are more important points to be improved.
本發明之主要目的,在於提供一種半導體晶片,其中本發明將一轉阻放大器及一調諧器整合至一半導體晶片上,可模組化設計此電路,以避免二者匹配不佳的情況產生,進而使電路設計難度及成本降低,另外將二者整合在一晶片上可降低生產成本及縮小光傳輸元件體積。The main object of the present invention is to provide a semiconductor wafer in which a transimpedance amplifier and a tuner are integrated on a semiconductor wafer, and the circuit can be modularly designed to avoid poor matching between the two. In turn, the circuit design difficulty and cost are reduced, and the integration of the two on one wafer can reduce the production cost and reduce the volume of the optical transmission component.
為達到上述之目的,本發明提供一種半導體晶片,其係包括一轉阻放大器,具有一第一輸入適於耦接至一光接收器之一第一輸出,其中該轉阻放大器根據該第一輸入產生一訊號,由該轉阻放大器之一第二輸出而輸出;以及一調諧器,具有一第二輸入耦接該第二輸出,用以調變該訊號,其中該轉阻放大器及該調諧器係設置於單一半導體晶片上,且該轉阻放大器及該調諧器為單一半導體晶片上之積體電路。In order to achieve the above object, the present invention provides a semiconductor wafer including a transimpedance amplifier having a first input adapted to be coupled to a first output of an optical receiver, wherein the transimpedance amplifier is The input generates a signal outputted by the second output of the transimpedance amplifier; and a tuner having a second input coupled to the second output for modulating the signal, wherein the transimpedance amplifier and the tuning The device is disposed on a single semiconductor wafer, and the transimpedance amplifier and the tuner are integrated circuits on a single semiconductor wafer.
現將經由對說明性實施例、隨附圖式及申請專利範圍之以下詳細描述的評述,使本發明之此等以及其他組件、步驟、特徵、效益及優勢變得明朗。These and other components, steps, features, advantages and advantages of the present invention will become apparent from the description of the appended claims.
圖式揭示本發明之說明性實施例。其並未闡述所有實施例。可另外或替代使用其它實施例。為節省空間或更有效地說明,可省略顯而易見或不必要之細節。相反,可實施一些實施例而不揭示所有細節。當相同數字或標號出現在不同圖式中時,其係指相同或類似組件或步驟。當以下描述連同隨附圖式一起閱讀時,可更充分地理解本發明之態樣,該等隨附圖式之性質應視為說明性而非限制性的。The drawings disclose illustrative embodiments of the invention. It does not describe all of the embodiments. Other embodiments may be used in addition or instead. In order to save space or more effectively explain, obvious or unnecessary details may be omitted. Instead, some embodiments may be implemented without revealing all the details. When the same number or label appears in a different figure, it refers to the same or similar components or steps. The invention will be more fully understood from the following description, taken in conjunction with the accompanying drawings.
請參考第1a圖所示,本發明之調諧器模組晶片100可接收一光接收元件200所傳送之訊號,此調諧器模組晶片100為一半導體晶片,此光接收元件200為一矽半導體晶片或一矽鍺半導體(SiGe semiconductor)晶片其中之一,且光接收元件200例如是一收光二極體、高頻二極體、雪崩光電二極體、感光耦合單元或互補性氧化金屬半導體單元其中之一,本發明光接收元件200較佳實施例為一收光二極體。調諧器模組晶片100包括一放大器10及一調諧器30,其中放大器例如是一轉阻放大器(transimpedence amplifier, TIA),本發明放大器10較佳實施例為一轉阻放大器。另外,此放大器10可包括一差動輸入放大器或一單端輸入放大器,本發明放大器10較佳實施例為一差動輸入放大器。Referring to FIG. 1a, the tuner module chip 100 of the present invention can receive a signal transmitted by a light receiving component 200. The tuner module wafer 100 is a semiconductor wafer, and the light receiving component 200 is a semiconductor. One of a wafer or a SiGe semiconductor wafer, and the light receiving element 200 is, for example, a light-receiving diode, a high-frequency diode, an avalanche photodiode, a photosensitive coupling unit, or a complementary metal oxide semiconductor unit. One of the preferred embodiments of the light receiving element 200 of the present invention is a light collecting diode. The tuner module chip 100 includes an amplifier 10 and a tuner 30, wherein the amplifier is, for example, a transimpedance amplifier (TIA). The preferred embodiment of the amplifier 10 of the present invention is a transimpedance amplifier. Additionally, the amplifier 10 can include a differential input amplifier or a single-ended input amplifier. The preferred embodiment of the amplifier 10 of the present invention is a differential input amplifier.
光接收元件200包括一光接收器20(例如是一收光二極體),此光接收器20之一正極端及一負極端分別耦接至一接地端(Vss)及一電源電壓端(Vdd),並且在正極端與接地端(Vss)之間及負極端與電源電壓端(Vdd)之間分別耦接一電感元件22,而該放大器10之一第一輸入端102及一第二輸入端104分別耦接至該光接收元件200內之一光接收器20之正極端及負極端,其中電感元件22可視為一低通濾波器,用以消除雜訊。當光接收器20(例如是收光二極體)接收一光訊號時,晶片內的空乏區會產生電子電洞對,其逆向偏壓的電場會驅使電子電洞各往N、P極移動,如此就產生一電流訊號,而該放大器10將光接收器20產生之電流訊號轉換成一電壓差值,該放大器10根據此電壓差值產生一輸出訊號V o傳送至調諧器(tuner)30之一訊號接收端30a,該調諧器30可調變該輸出訊號V o並輸出一輸出訊號至一外部元件。 The light receiving component 200 includes a light receiver 20 (for example, a light-receiving diode). One positive terminal and one negative terminal of the optical receiver 20 are respectively coupled to a ground terminal (Vss) and a power voltage terminal (Vdd). And an inductive component 22 is coupled between the positive terminal and the ground terminal (Vss) and between the negative terminal and the power supply voltage terminal (Vdd), and the first input terminal 102 and a second input of the amplifier 10 are respectively The terminals 104 are respectively coupled to the positive terminal and the negative terminal of the optical receiver 20 in the light receiving component 200. The inductive component 22 can be regarded as a low pass filter for eliminating noise. When the optical receiver 20 (for example, the light-receiving diode) receives an optical signal, the depletion region in the wafer generates an electron hole pair, and the reverse biased electric field drives the electron holes to move toward the N and P poles. thus generates a current signal, and the amplifier 10 converts the current signal arising from the light receiver 20 to a voltage difference value, the amplifier 10 generates an output signal V o is transmitted to the tuner (tuner) according to one of the voltage difference 30 The signal receiving end 30a, the tuner 30 can change the output signal Vo and output an output signal to an external component.
本發明之上述之光接收器20為差動輸出至放大器10內,但光接收器20也可單端輸出至放大器10內,請參考第1b圖及第1c圖所示,第1b圖中的光接收器20之輸出位在負極端與電源電壓端(Vdd)之間,而第1c圖中的光接收器20之輸出位在正極端與接地端(Vss)之間。The above-mentioned optical receiver 20 of the present invention is differentially outputted into the amplifier 10. However, the optical receiver 20 can also be outputted to the amplifier 10 at a single end. Please refer to FIG. 1b and FIG. 1c, and FIG. 1b. The output of the photoreceiver 20 is between the negative terminal and the supply voltage terminal (Vdd), and the output of the photoreceiver 20 in Fig. 1c is between the positive terminal and the ground terminal (Vss).
放大器10之電路示意圖如第2圖所示,放大器10的一第一輸入端(Inp)10a及一第二輸入端(Inn)10b分別耦接一電容單元106a及電容單元106b,該電容單元106a耦接至一第一開關單元118a之通道及一電感單元110a,此第一開關單元118a例如是一N型金氧半場效電晶體(NMOS)或一P型金氧半場效電晶體(PMOS),本發明之第一開關單元118a係以N型金氧半場效電晶體(NMOS)進行說明,因此電容單元106a耦接至N型金氧半場效電晶體(NMOS)之源極(Source) 通道,而電感單元110a另一端耦接接地端(Vss),而該電容單元106b耦接至一第二開關單元118b之通道及一電感單元110b,其中第二開關單元118b係以N型金氧半場效電晶體(NMOS)進行說明,因此電容單元106b耦接至N型金氧半場效電晶體(NMOS)之源極(Source) 通道,而電感單元110b另一端耦接接地端(Vss)。此放大器10的一輸出端(Outp)10c耦接至第一開關單元118a之通道及一電阻單元116a,例如是輸出端10c耦接N型金氧半場效電晶體(NMOS)之汲極(Drain) 通道及電阻單元116a,而電阻單元116a另一端耦接電源電壓端(Vdd),也就是電阻單元116a耦接於電源電壓端(Vdd)與第一輸出端10c之間,而位在電源電壓端(Vdd)與第二開關單元118b之通道之間可耦接一電阻單元116b,此電阻單元116b耦接第二開關單元118b之汲極(Drain) 通道。在此實施例中,電容單元106a, 106b、電感單元110a, 110b及電阻單元116a, 116b為一負載,其中該電容單元106a, 106b及電感單元110a, 110b可視為低通濾波器,用以負責消除雜訊。A circuit diagram of the amplifier 10 is shown in FIG. 2. A first input terminal (Inp) 10a and a second input terminal (Inn) 10b of the amplifier 10 are respectively coupled to a capacitor unit 106a and a capacitor unit 106b. The capacitor unit 106a is coupled to a capacitor unit 106a. The first switch unit 118a is coupled to a channel of a first switch unit 118a and an inductor unit 110a. The first switch unit 118a is, for example, an N-type MOSFET or a P-type MOSFET. The first switching unit 118a of the present invention is described by an N-type metal oxide half field effect transistor (NMOS), so the capacitor unit 106a is coupled to the source channel of the N-type metal oxide half field effect transistor (NMOS). The other end of the inductor unit 110a is coupled to the ground terminal (Vss), and the capacitor unit 106b is coupled to the channel of a second switch unit 118b and an inductor unit 110b, wherein the second switch unit 118b is an N-type gold-oxygen half field. The effect transistor (NMOS) is described. Therefore, the capacitor unit 106b is coupled to the source channel of the N-type metal oxide half field effect transistor (NMOS), and the other end of the inductor unit 110b is coupled to the ground terminal (Vss). An output terminal (Outp) 10c of the amplifier 10 is coupled to the channel of the first switching unit 118a and a resistor unit 116a. For example, the output terminal 10c is coupled to the drain of the N-type metal oxide half field effect transistor (NMOS). The channel and the resistor unit 116a, and the other end of the resistor unit 116a is coupled to the power supply voltage terminal (Vdd), that is, the resistor unit 116a is coupled between the power supply voltage terminal (Vdd) and the first output terminal 10c, and is located at the power supply voltage. A resistor unit 116b is coupled between the terminal (Vdd) and the channel of the second switch unit 118b. The resistor unit 116b is coupled to the drain channel of the second switch unit 118b. In this embodiment, the capacitor units 106a, 106b, the inductive units 110a, 110b and the resistor units 116a, 116b are a load, wherein the capacitor units 106a, 106b and the inductive units 110a, 110b can be regarded as low-pass filters for being responsible for Eliminate noise.
如第2圖及第3圖所示,此調諧器模組晶片100更包括一自動增益控制(automatic gain control, AGC)電路40,如第2圖的放大器10的第一開關單元118a耦接至自動增益控制電路40,也就是第一開關單元118a (N型金氧半場效電晶體)的之閘極(Gate)通道耦接至自動增益控制電路40之一輸出端40a,而自動增益控制電路之輸入端40b耦接至放大器10的輸出端10c,此自動增益控制電路40係根據該輸入端40b之輸出訊號調整該輸出端40a的電壓。自動增益控制電路40用以使放大器10的增益自動地隨自動增益控制電路40的輸入信號強度而自動調整。As shown in FIG. 2 and FIG. 3, the tuner module chip 100 further includes an automatic gain control (AGC) circuit 40. The first switching unit 118a of the amplifier 10 of FIG. 2 is coupled to The automatic gain control circuit 40, that is, the gate channel of the first switching unit 118a (N-type metal oxide half field effect transistor) is coupled to one of the output terminals 40a of the automatic gain control circuit 40, and the automatic gain control circuit The input terminal 40b is coupled to the output terminal 10c of the amplifier 10. The automatic gain control circuit 40 adjusts the voltage of the output terminal 40a according to the output signal of the input terminal 40b. The automatic gain control circuit 40 is operative to automatically adjust the gain of the amplifier 10 automatically with the input signal strength of the automatic gain control circuit 40.
請參考第4圖所示,此第4圖為調諧器30之一電路圖範列,此調諧器30包括:a. 一低雜訊放大器(low noise amplifier, LNA)302位在調諧器30之訊號接收端30a之下游端,其中此低雜訊放大器放大器包括一單端至差動放大器或一差動至差動放大器其中之一,低雜訊放大器302可將調諧器30所接收之輸出訊號V o放大; b. 一第一濾波器304位在低雜訊放大器302之下游端,其中此第一濾波器304例如是一帶通濾波器 (band-pass filter),此第一濾波器304可將低雜訊放大器302放大後之訊號過濾,將雜訊去除,例如是去除鏡像信號;c. 二混波器(Mixers)306a、306b位在濾波器304之下游端,其中此二混波器306a、306b例如是一降頻轉換器(frequency-down converters),該混波器306a、306b可用來將射頻(radio frequency)的收集信號轉換成中頻(intermediate frequency)的收集信號;d. 一調變器(modulation)314位在二混波器306a、306b之上游端並且耦接一本機振盪器316,其中此調變器314例如是一同相正交(In-phase/Quadrature)調變器,此調變器314之一第一輸出耦接該混波器306a,而調變器314之一第二輸出耦接該混波器306b,其中調變器314之第一輸出及第二輸出之相位差係為90度且頻率係為相同的,而混波器306a根據調變器314之第一輸出對訊號進行混波以產生一第一混波訊號,混波器306b根據調變器314之第二輸出對訊號進行混波以產生一第二混波訊號,其中第一混波訊號與第二混波訊號為二正交訊號,也就是第一混波訊號與第二混波訊號之相位差係為90度;e. 二第一可變增益放大器(variable-gain amplifiers, VGA)308a、308b分別位在二混波器306a、306b之下游端,其中此第一可變增益放大器308a、308b包括一單端至差動放大器或一差動至差動放大器其中之一,第一可變增益放大器308a、308b可將調變後之第一混波訊號與第二混波訊號進行電壓放大; f. 一第二濾波器310a位在第一可變增益放大器308a、308b之下游端,其中該第二濾波器310a例如是一鏡像抑制濾波器(Image Rejection Filter),此第二濾波器310a接收該第一可變增益放大器308a、308b之輸出訊號並解決鏡像訊號的問題,並將雜訊去除;g. 第三濾波器310b的一輸入端耦接第二濾波器310a的一輸出端,第三濾波器310b可以對第三濾波器310b的該輸入(例如第二濾波器310a所輸出的訊號)執行濾波,以產生一輸出(例如一預定通道或頻率中的訊號)。第三濾波器310b可以是一通道選擇濾波器,其可過濾出或選擇出一預定通道或頻率中所攜帶的訊號;h. 一第二可變增益放大器(variable-gain amplifiers, VGA)312a位在第三濾波器310b之下游端,其中此第二可變增益放大器312a包括一單端至差動放大器或一差動至差動放大器其中之一,第二可變增益放大器312a可將第三濾波器310b過濾後之訊號放大並傳送至調諧器30之輸出端Vo,由此輸出端Vo將調變後之訊號輸出至一外部元件;i. 功率偵測器(Power Detector)318分別耦接第一可變增益放大器308a、308b之輸出端及耦接第一濾波器304之輸出端;j. 一直流偏移消除器320分別耦接第二可變增益放大器312a之輸出端,以及耦接第三濾波器310b之輸入端,其中直流偏移消除器320用以將第二濾波器310a至第二可變增益放大器312a之訊號路徑所產生之直流電偏移電壓成分消除;k. 頻率合成器322可耦接調諧器模組晶片100之外的一振盪器(oscillator)324,此振盪器324內可具有一石英晶體,用以產生一參考時脈訊號至頻率合成器322,或是此振盪器324可由一RLC電路取代石英晶體產生參考時脈訊號至頻率合成器322,此RLC電路係由複數電阻元件、複數電感元件及複數電容所構成,而此RLC電路係內建在調諧器模組晶片100; L. 一頻率合成器(frequency synthesizer)322經由耦接本機振盪器316與調變器314耦接,其中頻率合成器322例如是一非整數鎖相迴路(fractional-N PLL),用以產生一合成時脈訊號,其中該合成時脈訊號之頻率為上述振盪器324所產生之參考時脈訊號頻率的整數倍,其中合成時脈訊號之頻率可透過頻率合成器322輸入端的電壓或電流控制,而本機振盪器316根據頻率合成器322所產生之合成時脈訊號產生另一時脈訊號至上述調變器314,該調變器314根據此時脈訊號將二混波器306a、306b所處理的訊號調變成兩個正交的第一混波訊號與第二混波訊號。 Please refer to FIG. 4, which is a circuit diagram of the tuner 30. The tuner 30 includes: a. a low noise amplifier (LNA) 302 bit signal at the tuner 30. The downstream end of the receiving end 30a, wherein the low noise amplifier amplifier comprises a single-ended to differential amplifier or a differential to differential amplifier, and the low noise amplifier 302 can receive the output signal V received by the tuner 30. o amplifying; b. a first filter 304 is located at the downstream end of the low noise amplifier 302, wherein the first filter 304 is, for example, a band-pass filter, and the first filter 304 can The low noise amplifier 302 amplifies the signal filtering to remove the noise, for example, to remove the image signal; c. The second mixers 306a, 306b are located at the downstream end of the filter 304, wherein the second mixer 306a 306b is, for example, a frequency-down converters, and the mixers 306a, 306b can be used to convert a radio frequency collected signal into an intermediate frequency collected signal; d. Modulation 314 bits in the second mixer 306a, 306b The upstream end is coupled to a local oscillator 316, wherein the modulator 314 is, for example, an in-phase/quadrature modulator, and the first output of the modulator 314 is coupled to the hybrid The second output of the modulator 314 is coupled to the mixer 306b, wherein the first output and the second output of the modulator 314 have a phase difference of 90 degrees and the frequency is the same. The mixer 306a mixes the signal according to the first output of the modulator 314 to generate a first mixed signal, and the mixer 306b mixes the signal according to the second output of the modulator 314 to generate a second The mixed signal, wherein the first mixed signal and the second mixed signal are two orthogonal signals, that is, the phase difference between the first mixed signal and the second mixed signal is 90 degrees; e. Gain-amplifiers (VGA) 308a, 308b are respectively located at the downstream of the two mixers 306a, 306b, wherein the first variable gain amplifiers 308a, 308b comprise a single-ended to differential amplifier or a differential To one of the differential amplifiers, the first variable gain amplifiers 308a, 308b can adjust the first mixed The signal and the second mixed signal are voltage amplified; f. a second filter 310a is located at a downstream end of the first variable gain amplifier 308a, 308b, wherein the second filter 310a is, for example, an image suppression filter (Image Rejection Filter), the second filter 310a receives the output signals of the first variable gain amplifiers 308a, 308b and solves the problem of the image signal, and removes the noise; g. an input end of the third filter 310b is coupled An output of the second filter 310a, the third filter 310b may perform filtering on the input of the third filter 310b (eg, the signal output by the second filter 310a) to generate an output (eg, a predetermined channel or The signal in the frequency). The third filter 310b may be a channel selection filter that filters out or selects a signal carried in a predetermined channel or frequency; h. a second variable gain amplifier (VGA) 312a bit At a downstream end of the third filter 310b, wherein the second variable gain amplifier 312a includes one of a single-ended to differential amplifier or a differential to differential amplifier, and the second variable gain amplifier 312a can be third The filtered signal of the filter 310b is amplified and transmitted to the output terminal Vo of the tuner 30, whereby the output terminal Vo outputs the modulated signal to an external component; i. The Power Detector 318 is coupled respectively. An output of the first variable gain amplifier 308a, 308b and an output coupled to the first filter 304; a DC offset canceller 320 coupled to the output of the second variable gain amplifier 312a, and coupled The input end of the third filter 310b, wherein the DC offset canceller 320 is configured to cancel the DC offset voltage component generated by the signal path of the second filter 310a to the second variable gain amplifier 312a; k. Frequency synthesizer 322 coupler An oscillator 324 other than the tuner module chip 100, the oscillator 324 may have a quartz crystal for generating a reference clock signal to the frequency synthesizer 322, or the oscillator 324 may be The RLC circuit replaces the quartz crystal to generate a reference clock signal to the frequency synthesizer 322. The RLC circuit is composed of a plurality of resistive elements, a plurality of inductive elements, and a plurality of capacitors, and the RLC circuit is built in the tuner module chip 100; A frequency synthesizer 322 is coupled to the modulator 314 via a coupled local oscillator 316, wherein the frequency synthesizer 322 is, for example, a non-integer phase-locked loop (fractional-N PLL) for generating a The clock signal is synthesized, wherein the frequency of the synthesized clock signal is an integer multiple of the reference clock signal frequency generated by the oscillator 324, wherein the frequency of the synthesized clock signal can be controlled by the voltage or current of the input end of the frequency synthesizer 322. The local oscillator 316 generates another clock signal according to the synthesized clock signal generated by the frequency synthesizer 322 to the modulator 314. The modulator 314 combines the second signal according to the pulse signal at this time. The signals processed by the 306a, 306b are modulated into two orthogonal first mixed signals and second mixed signals.
另外,在電源電壓端Vdd與第一濾波器304之間更可耦接複數電感元件50,用以減少背景雜訊,其中此電感元件50為內建調諧器模組晶片100內,或是調諧器模組晶片100之外的一電感元件。另外,此調諧器模組晶片100內更包括一串列通訊匯流排單元326,用以提供一同步串列通信(inter-chip synchronous serial communication)介面耦接其它晶片(或系統),使各個晶片之間能額外有一時脈訊號線(clock line),使各個晶片(或系統)之時脈同步化,其中串列通訊匯流排單元326例如是一內部整合電路 ( inter integrated chips, I²C)、串行外設介面(Serial Peripheral Interface Bus,SPI)或微線介面(microwire interface)其中之一,本發明串列通訊匯流排單元326最佳實施例係以內部整合電路(I²C)為說明。另外,調諧器模組晶片100內更包括一環通放大器(loop-through amplifier)328耦接在訊號接收端30a與低雜訊放大器302之間,用以將放大器10(例如是轉阻放大器(TIA))所傳輸之訊號更進一步的放大,而輸出至其它接收裝置,其中此環通放大器328包括一單端至差動放大器或一差動至差動放大器其中之一。另外,調諧器模組晶片100內更包括一電壓穩壓器(voltage regulator)330,用以提供調諧器模組晶片100在工作時一穩定電壓,例如是提供一穩定電壓至放大器10之一電源電壓端(Vdd)及調諧器模組晶片100之一電源電壓端(Vdd),其中電壓穩壓器330例如是一低壓差線性穩壓器(low dropout regulator, LDO)。In addition, a plurality of inductive components 50 can be coupled between the power supply voltage terminal Vdd and the first filter 304 for reducing background noise, wherein the inductive component 50 is built into the tuner module chip 100, or is tuned. An inductive component other than the module die 100. In addition, the tuner module chip 100 further includes a serial communication bus unit 326 for providing an inter-chip synchronous serial communication interface to couple other chips (or systems) for each chip. An additional clock line can be used to synchronize the clocks of the respective chips (or systems), wherein the serial communication bus unit 326 is, for example, an inter integrated chip (I2C), a string. One of the Serial Peripheral Interface Bus (SPI) or microwire interface, the preferred embodiment of the serial communication bus unit 326 of the present invention is illustrated by an internal integrated circuit (I2C). In addition, the tuner module chip 100 further includes a loop-through amplifier 328 coupled between the signal receiving end 30a and the low noise amplifier 302 for using the amplifier 10 (for example, a transimpedance amplifier (TIA). The transmitted signal is further amplified and output to other receiving devices, wherein the loop-through amplifier 328 includes a single-ended to differential amplifier or a differential to differential amplifier. In addition, the tuner module chip 100 further includes a voltage regulator 330 for providing a constant voltage of the tuner module chip 100 during operation, for example, providing a stable voltage to one of the amplifiers 10. The voltage terminal (Vdd) and one of the power supply voltage terminals (Vdd) of the tuner module chip 100, wherein the voltage regulator 330 is, for example, a low dropout regulator (LDO).
請參考第5圖所示,此調諧器模組晶片100可設置在一電路基板600上,此調諧器模組晶片100具有一金屬接墊(meatal pad)101,可利用打線方式(Wire bonding)經由一金屬導線60電性連接至電路基板600之一金屬接墊62上,此金屬導線60之材質包括金、銅或銀其中之一,並在電路基板600及調諧器模組晶片100上形成一聚合物層64包覆及保護調諧器模組晶片100及金屬導線60,其中電路基板600例如是一陶瓷基板、一金屬基板、一導線架基板或一印刷電路板,其中陶瓷基板包括氧化鋁(Al 2O 3)基板、氮化鋁(AlN)基板或氧化铍(BeO)基板其中之一,另外,在電路基板600上可設置一或多個被動元件(圖中未示)並電性連接至電路基板600之金屬接墊62,此被動元件例如是一電阻元件、一可變電阻元件、一熱敏電阻元件、一電容元件或一電感元件之一或及其組合。 Referring to FIG. 5, the tuner module chip 100 can be disposed on a circuit substrate 600. The tuner module chip 100 has a metal pad 101, which can be wired. The metal wire 60 is electrically connected to one of the metal pads 62 of the circuit substrate 600. The metal wire 60 is made of one of gold, copper or silver and formed on the circuit substrate 600 and the tuner module chip 100. A polymer layer 64 covers and protects the tuner module wafer 100 and the metal wires 60. The circuit substrate 600 is, for example, a ceramic substrate, a metal substrate, a lead frame substrate or a printed circuit board, wherein the ceramic substrate comprises alumina. One of (Al 2 O 3 ) substrate, aluminum nitride (AlN) substrate or beryllium oxide (BeO) substrate, and one or more passive components (not shown) may be disposed on the circuit substrate 600 and electrically The metal pad 62 is connected to the circuit substrate 600. The passive component is, for example, a resistive component, a variable resistive component, a thermistor component, a capacitive component or an inductive component or a combination thereof.
第6圖揭露本發明調諧器模組晶片100之引腳配置圖。此調諧器模組晶片100封裝包括二個引腳RFinp及引腳RFinn,分別耦接至該放大器10之二個輸入端10a, 10b,其中引腳GND在引腳RFinp及引腳RFinn之間,將引腳RFinp及引腳RFinn隔開,其中此引腳GND為接地端(Ground),且此引腳RFinp及引腳RFinn位在此調諧器模組晶片100封裝同一側(同一邊),另外在引腳RFinp及引腳RFinn之間的引腳GND也可替換成引腳PWR(power)或是替換成空引腳(無作用之接腳);調諧器模組晶片100另包括二個引腳Vo1, Vo2分別耦接至調諧器30之二個輸出端Vo1 Vo2,其中引腳GND在引腳Vo1, Vo2之間,將引腳Vo1, Vo2隔開,且此引腳Vo1, Vo2位在此調諧器模組晶片100封裝同一側(同一邊),另外在引腳Vo1, Vo2之間的引腳GND也可替換成引腳PWR(power)或是替換成空引腳(無作用之接腳);調諧器模組晶片100更可包括複數引腳GND耦接至上述放大器10、自動增益控制電路40及調諧器30的接地接點,或者耦接至該調諧器模組晶片100之一接地參考,這些引腳GND可提供一接地電壓至上述放大器10、自動增益控制電路40及調諧器30,;調諧器模組晶片100更可包括引腳VDD5V用以輸入5V電源並轉換成3.7V電壓從引腳LDO輸出,引腳LDO輸出之3.7V電壓將被直接提供至複數引腳VIN進而耦接至上述放大器10、自動增益控制電路40及調諧器30的電源接點,用以供應放大器10、自動增益控制電路40及調諧器30電源;調諧器模組晶片100更可包括引腳AVDDRX作為一內部交流電接地端(internal alternate-current (AC) ground)。FIG. 6 illustrates a pin configuration diagram of the tuner module wafer 100 of the present invention. The tuner module chip 100 package includes two pins RFinp and pins RFinn respectively coupled to the two input terminals 10a, 10b of the amplifier 10, wherein the pin GND is between the pin RFinp and the pin RFinn. The pin RFinp and the pin RFinn are separated, wherein the pin GND is a ground (Ground), and the pin RFinp and the pin RFinn bit are on the same side (the same side) of the tuner module chip 100, and The pin GND between the pin RFinp and the pin RFinn can also be replaced with a pin PWR (power) or replaced with an empty pin (inactive pin); the tuner module chip 100 further includes two leads The pins Vo1 and Vo2 are respectively coupled to the two output terminals Vo1 Vo2 of the tuner 30, wherein the pin GND is between the pins Vo1 and Vo2, and the pins Vo1 and Vo2 are separated, and the pins Vo1 and Vo2 are located at The tuner module chip 100 is packaged on the same side (the same side), and the pin GND between the pins Vo1 and Vo2 can also be replaced with a pin PWR (power) or replaced with an empty pin (no effect) The tuner module chip 100 may further include a plurality of pins GND coupled to the ground contact of the amplifier 10, the automatic gain control circuit 40, and the tuner 30, or Coupled to a ground reference of the tuner module chip 100, the pin GND can provide a ground voltage to the amplifier 10, the automatic gain control circuit 40 and the tuner 30; the tuner module chip 100 can further include The pin VDD5V is used to input a 5V power supply and is converted to a 3.7V voltage to be output from the pin LDO. The 3.7V voltage of the pin LDO output is directly supplied to the complex pin VIN and coupled to the amplifier 10 and the automatic gain control circuit 40. And a power contact of the tuner 30 for supplying the amplifier 10, the automatic gain control circuit 40 and the tuner 30 power supply; the tuner module chip 100 further includes a pin AVDDRX as an internal alternating current (internal alternate-current (internal alternate-current (internal alternate-current (internal alternate-current (internal alternate-current (internal alternate-current AC) ground).
本發明經由光接收元件200接收光訊號後產生電流訊號,再經由放大器10(轉阻放大器)將此電流訊號轉換成電壓訊號輸入至調諧器模組晶片100,再經由調諧器模組晶片100內的限制放大器328及低雜訊放大器320則將放大器10所傳輸之電壓訊號作進一步的放大,再經由第一濾波器304將雜訊去除,再經由調變器314將混波器306a、306b所處理的訊號調變成兩個正交的第一混波訊號與第二混波訊號(相位差為90度),再經由第一可變增益放大器308a、308b將訊號放大,並由第二濾波器310a過濾,將雜訊去除,再由第三濾波器310b濾出或選擇出一預定通道或頻率中所攜帶的訊號,最後再由第二可變增益放大器312a、312b將訊號放大而輸出至調諧器30之輸出端Vo。After receiving the optical signal through the light receiving component 200, the present invention generates a current signal, and then converts the current signal into a voltage signal input to the tuner module chip 100 via the amplifier 10 (transimpedance amplifier), and then passes through the tuner module chip 100. The limiting amplifier 328 and the low noise amplifier 320 further amplify the voltage signal transmitted by the amplifier 10, remove the noise through the first filter 304, and then the mixers 306a, 306b via the modulator 314. The processed signal is modulated into two orthogonal first mixed signal and second mixed signal (phase difference is 90 degrees), and then the signal is amplified by the first variable gain amplifiers 308a, 308b, and the second filter is used. 310a filters, removes the noise, filters out or selects a signal carried in a predetermined channel or frequency by the third filter 310b, and finally amplifies the signal by the second variable gain amplifier 312a, 312b and outputs the signal to the tuning. The output of the device 30 is Vo.
本發明將調諧器30與放大器10(例如是一轉阻放大器)整合在一晶片上,可模組化設計此電路,以避免二者匹配不佳的情況產生,進而使電路設計難度及成本降低,另外將二者整合在一晶片上可降低生產成本及縮小光傳輸元件體積。The invention integrates the tuner 30 and the amplifier 10 (for example, a transimpedance amplifier) on a chip, and can modularly design the circuit to avoid the poor matching between the two, thereby making the circuit design difficult and cost lower. In addition, the integration of the two on one wafer can reduce the production cost and reduce the volume of the optical transmission component.
以上所述係藉由實施例說明本發明之特點,其目的在使熟習該技術者能暸解本發明之內容並據以實施,而非限定本發明之專利範圍,故,凡其他未脫離本發明所揭示之精神所完成之等效修飾或修改,仍應包含在以下所述之申請專利範圍中。The above description of the embodiments of the present invention is intended to be understood by those skilled in the art, and the invention may be practiced without departing from the scope of the invention. Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the claims described below.
100‧‧‧調諧器模組晶片
200‧‧‧光接收元件
10‧‧‧放大器
30‧‧‧調諧器
20‧‧‧光接收器
102‧‧‧第一輸入端
104‧‧‧第二輸入端
30a‧‧‧訊號接收端
10a‧‧‧第一輸入端
10b‧‧‧第二輸入端
106a‧‧‧電容單元
106b‧‧‧電容單元
118a‧‧‧第一開關單元
118b‧‧‧第二開關單元
110b‧‧‧電感單元
10c‧‧‧輸出端
116a‧‧‧電阻單元
110a‧‧‧電感單元
116b‧‧‧電阻單元
40‧‧‧自動增益控制電路
40a‧‧‧輸出端
40b‧‧‧輸入端
302‧‧‧低雜訊放大器
304‧‧‧第一濾波器
306a‧‧‧混波器
306b‧‧‧混波器
314‧‧‧調變器
316‧‧‧本機振盪器
308a‧‧‧第一可變增益放大器
308b‧‧‧第一可變增益放大器
310a‧‧‧第二濾波器
310b‧‧‧第三濾波器
312a‧‧‧第二可變增益放大器
312b‧‧‧第二可變增益放大器
318‧‧‧功率偵測器
320‧‧‧直流偏移消除器
322‧‧‧頻率合成器
324‧‧‧振盪器
50‧‧‧電感元件
326‧‧‧串列通訊匯流排單元
328‧‧‧環通放大器
330‧‧‧電壓穩壓器
600‧‧‧電路基板
101‧‧‧金屬接墊
60‧‧‧金屬導線
62‧‧‧金屬接墊
64‧‧‧聚合物層100‧‧‧ Tuner Module Wafer
200‧‧‧Light receiving components
10‧‧‧Amplifier
30‧‧‧ Tuner
20‧‧‧Optical Receiver
102‧‧‧ first input
104‧‧‧second input
30a‧‧‧Signal Receiver
10a‧‧‧ first input
10b‧‧‧second input
106a‧‧‧Capacitor unit
106b‧‧‧Capacitor unit
118a‧‧‧First switch unit
118b‧‧‧Second switch unit
110b‧‧‧Inductance unit
10c‧‧‧output
116a‧‧‧Resistance unit
110a‧‧‧Inductance unit
116b‧‧‧Resistance unit
40‧‧‧Automatic gain control circuit
40a‧‧‧output
40b‧‧‧ input
302‧‧‧Low noise amplifier
304‧‧‧First filter
306a‧‧‧Mixer
306b‧‧‧Mixer
314‧‧‧Transformer
316‧‧‧Local Oscillator
308a‧‧‧First Variable Gain Amplifier
308b‧‧‧First Variable Gain Amplifier
310a‧‧‧second filter
310b‧‧‧ third filter
312a‧‧‧Second variable gain amplifier
312b‧‧‧Second variable gain amplifier
318‧‧‧Power Detector
320‧‧‧DC offset canceller
322‧‧‧ frequency synthesizer
324‧‧‧Oscillator
50‧‧‧Inductive components
326‧‧‧Serial communication bus unit
328‧‧‧Circuit amplifier
330‧‧‧Voltage regulator
600‧‧‧ circuit substrate
101‧‧‧Metal pads
60‧‧‧Metal wire
62‧‧‧Metal pads
64‧‧‧ polymer layer
第1a圖為本發明調諧器模組晶片與第一種光接收晶片之間的電路結構圖。 第1b圖為本發明調諧器模組晶片與第二種光接收晶片之間的電路結構圖。 第1c圖為本發明調諧器模組晶片與第三種光接收晶片之間的電路結構圖。 第2圖為本發明之轉阻放大器之電路示意圖。 第3圖為本發明之另一調諧器模組晶片與光接收晶片之間的電路結構圖。 第4圖為本發明之調諧器之電路示意圖。 第5圖為本發明之調諧器模組晶片之封裝結構示意圖。 第6圖為本發明之調諧器模組晶片之引腳配置圖。Figure 1a is a circuit diagram of the tuner module wafer of the present invention and the first type of light receiving wafer. Figure 1b is a circuit diagram of the tuner module wafer and the second light receiving wafer of the present invention. Figure 1c is a circuit diagram of the tuner module wafer and the third light receiving wafer of the present invention. Figure 2 is a circuit diagram of the transimpedance amplifier of the present invention. Figure 3 is a circuit diagram of another tuner module chip and a light receiving wafer of the present invention. Figure 4 is a circuit diagram of the tuner of the present invention. FIG. 5 is a schematic view showing the package structure of the tuner module chip of the present invention. Figure 6 is a diagram showing the pin configuration of the tuner module chip of the present invention.
雖然在圖式中已描繪某些實施例,但熟習此項技術者應瞭解,所描繪之實施例為說明性的,且可在本發明之範疇內構想並實施彼等所示實施例之變化以及本文所述之其他實施例。While certain embodiments have been illustrated in the drawings, the embodiments of the invention And other embodiments described herein.
20‧‧‧光接收器 20‧‧‧Optical Receiver
100‧‧‧調諧器模組晶片 100‧‧‧ Tuner Module Wafer
200‧‧‧光接收元件 200‧‧‧Light receiving components
30a‧‧‧訊號接收端 30a‧‧‧Signal Receiver
102‧‧‧第一輸入端 102‧‧‧ first input
104‧‧‧第二輸入端 104‧‧‧second input
10‧‧‧放大器 10‧‧‧Amplifier
40‧‧‧自動增益控制電路 40‧‧‧Automatic gain control circuit
30‧‧‧調諧器 30‧‧‧ Tuner
40a‧‧‧輸出端 40a‧‧‧output
40b‧‧‧輸入端 40b‧‧‧ input
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW105115879A TWI599163B (en) | 2016-05-20 | 2016-05-20 | A semiconductor chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW105115879A TWI599163B (en) | 2016-05-20 | 2016-05-20 | A semiconductor chip |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI599163B true TWI599163B (en) | 2017-09-11 |
TW201742373A TW201742373A (en) | 2017-12-01 |
Family
ID=60719314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105115879A TWI599163B (en) | 2016-05-20 | 2016-05-20 | A semiconductor chip |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI599163B (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8159619B2 (en) * | 2008-10-07 | 2012-04-17 | Sunplus Technology Co., Ltd. | Multi-standard integrated television receiver |
US8319899B2 (en) * | 2009-09-01 | 2012-11-27 | Sharp Kabushiki Kaisha | Front-end circuit, tuner, and television broadcasting receiver |
-
2016
- 2016-05-20 TW TW105115879A patent/TWI599163B/en active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8159619B2 (en) * | 2008-10-07 | 2012-04-17 | Sunplus Technology Co., Ltd. | Multi-standard integrated television receiver |
US8319899B2 (en) * | 2009-09-01 | 2012-11-27 | Sharp Kabushiki Kaisha | Front-end circuit, tuner, and television broadcasting receiver |
Non-Patent Citations (2)
Title |
---|
2008年1月16日公開文件Wei Xu "Analog CMOS Design for Optical Coherence Tomography Signal Detection and Processing"IEEE Transactions on Biomedical Engineering ( Volume: 55, Issue: 2, Feb. 2008 ) * |
2008年7月15日公開文件Sangsu Jin "Wide-band CMOS loop-through amplifier for Cable TV tuner" Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE * |
Also Published As
Publication number | Publication date |
---|---|
TW201742373A (en) | 2017-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8285230B2 (en) | Amplifying circuit, semiconductor integrated circuit, wireless transmission system, and communication apparatus | |
US9882538B2 (en) | Distributed output matching network for a radio frequency power amplifier module | |
US8112044B2 (en) | Transceiver system and method of using same | |
US20110020011A1 (en) | Amplifier, Optical Receiver Circuit, Optical Module and Data Exchange System | |
US8594583B2 (en) | Apparatus and method for radio frequency reception with temperature and frequency independent gain | |
JP5630648B2 (en) | Reception device, reception method, and electronic device | |
US10651806B2 (en) | Method and system for a pseudo-differential low-noise amplifier at KU-band | |
TW201414188A (en) | Trans-impedance amplifiers (TIA) thermally isolated from optical modules | |
TWI513241B (en) | Gain control in a shared rf front-end path for different standards that use the same frequency band | |
EP1177629B1 (en) | Output buffer with independently controllable current mirror legs | |
US7466928B2 (en) | Optical receiver with dynamic gain and bandwidth | |
US20130016748A1 (en) | Transimpedance amplifier, semiconductor device, and optical module | |
JP2004336749A (en) | Photo-amplifier circuit with improved power supply voltage rejection | |
US20060043425A1 (en) | Semiconductor integrated circuit device which restricts an increase in the area of a chip, an increase in the number of lead terminals of a package, and can reduce parasitic inductance | |
TWI599163B (en) | A semiconductor chip | |
JP7419770B2 (en) | Optical receiving circuit and optical receiver | |
CN110249523B (en) | Amplifier with a high-frequency amplifier | |
US7239207B2 (en) | Transimpedance amplifier | |
US8018286B2 (en) | Low power integrated circuit | |
CN107453720A (en) | Semiconductor chip | |
JP2005020138A (en) | Current/voltage converter circuit and optical receiver | |
JP2009017494A (en) | Bias circuit, power amplification circuit, receiver, transmitter, and transceiver | |
JP2006270287A (en) | High frequency power amplifier circuit | |
US20120305753A1 (en) | Circuit for setting the voltage potential at the output of a pin photoreceiver and photoreceiver assembly | |
TW201742395A (en) | A chip for optical receiver |