TWI596675B - Finfet channel on oxide structures and related methods - Google Patents

Description

FinFET channel on oxide substrate and related methods

With the development of the electronics industry, there is a need for smaller, faster-running electronic components that can simultaneously support a large number of increasingly complex and precise functions. Therefore, a continuing trend in the semiconductor industry is to manufacture low cost, high performance, and low power integrated circuit devices (ICs). To date, it has been largely achieved that production efficiency is reduced and associated costs are reduced by scaling down semiconductor IC sizes (e.g., minimum feature sizes). However, this scaling also adds complexity to the semiconductor fabrication process. Therefore, to achieve continuous development of semiconductor ICs and electronic components, similar improvements in semiconductor manufacturing processes are required.

Recently, multi-gate electronic components have been introduced in an attempt to reduce the current in the off state, reduce short channel effects (SCEs), and improve gate control by increasing gate-to-channel coupling. One such multi-gate electronic component introduced is a fin field effect transistor (FinFET). The FinFET takes its name from its fin structure, which extends from the sheet material formed thereon and is used to form a field effect transistor (FET) channel. FinFETs are compatible with conventional complementary metal oxide semiconductor (CMOS) processes, and their three-dimensional structure allows them to be scaled arbitrarily while maintaining gate control and mitigating SCEs. In conventional processes, anti-punch-through (APT) ion implantation is achieved by FinFET fin elements to prevent punch-through of the FinFET source/drain depletion region. However, by implanting dopant ions (for example, dopants for implanting APT) into the fins of FinFET electronic components, this directly leads to the FinFET channel region. Defects are formed in the domain and impurities are brought into the FinFET channel region. Such channel defects and impurities can cause scattering of the carrier as it flows through the FinFET, thereby reducing channel mobility and adversely affecting electronic component performance. Injecting dopants through the FinFET fins can also result in non-uniform dopant distribution and can cause other problems such as variations in FinFET electronic component parameters. Therefore, the prior art fully demonstrates that it still needs to be improved in various aspects.

100-134‧‧‧ method

200‧‧‧ components

202‧‧‧Substrate

202A‧‧‧Substrate part

204, 206‧‧‧Anti-punch-through (APT) area

208, 210‧‧‧ patterned light layer

212, 214‧‧‧Ion implantation process

302, 304, 302A, 304A‧‧‧ epitaxial layer

306‧‧‧Hard mask (HM) layer

306A‧‧‧HM section

308‧‧‧Oxide

308A‧‧‧Oxide layer part

310‧‧‧ nitride layer

310A‧‧‧ nitride layer part

402‧‧‧Fins

404‧‧‧Channel

302R‧‧‧ Residual material section

302C‧‧‧Oxidized layer

304SW‧‧‧ sidewall

602‧‧‧Oxide layer

702‧‧‧ liner

802‧‧‧ dielectric layer

902‧‧‧Isolated Area

H _FIN , H‧‧‧Fin height

W _FIN ‧‧‧Fin width

904‧‧‧ top surface

402BP‧‧‧ water level

1102‧‧‧ gap

1302, 1406‧‧‧ dielectric layer

1302A‧‧‧Dielectric area

1402‧‧‧gate stacking

1404‧‧‧ Sidewall gasket

1408‧‧‧electrode layer

1410‧‧‧hard mask

1412‧‧‧Oxide layer

1414‧‧‧ nitride layer

1502‧‧‧ source area

1504‧‧‧Bungee area

1602‧‧‧Source structure

1604‧‧‧汲 structure

1702‧‧‧ILD layer

1704‧‧‧Channel

1802‧‧‧High dielectric constant/metal gate stack

To assist the reader in achieving the best understanding, it is recommended that you read the following detailed description when reading this disclosure. It should be understood that various features are not shown in the <RTIgt; In fact, for more clarity, various feature sizes can be arbitrarily increased or decreased.

1 is a flow chart of a method of fabricating a FinFET element or portion thereof in accordance with one or more aspects of the present disclosure; FIGS. 2A, 3, 4A, 5A, 6A, 7A, 8, 9, 10A, 11A, 12A, 13A, and 14 -18 is an isometric view of an embodiment of element 200 in accordance with the method aspect illustrated in FIG. 1; and FIGS. 2B, 4B, 5B, 6B, 7B, 10B, 11B, 12B, and 13B are aspects of the method illustrated in FIG. Corresponding to the respective isometric views described above, a cross-sectional view of an embodiment of the component 200.

This description provides several different implementations or embodiments that can be used to implement various features of the invention. Specific examples of the components and devices described below are used to simplify the disclosure. Of course, these are just examples and are not intended to be limited thereto. For example, forming a first feature on or in a second feature as described below includes an embodiment in which the first and second features are formed in direct contact, and also included in the Embodiments of additional features are formed between the first and second features, and such first and second features may not be in direct contact. In addition, the disclosure may repeat reference numerals in different examples. And / or reference letters. The purpose of this repetition is to be concise and clear, but does not in itself determine the relationship between the described embodiments and/or construction.

In addition, spatially related terms such as "below", "below", "below", "above", and "above", etc., are used herein. Briefly, the relationship of one element or feature to another element(s) or another feature(s) is shown. Related terms in this space are intended to include different orientations of the elements in use or operation in addition to the orientation depicted in the figures. Additionally, the device can be oriented (rotated 90 degrees or oriented in other directions), and the spatially related descriptive symbols used herein can be equally illustrated accordingly.

It should also be noted that the embodiments presented herein are shown in the form of multi-gate transistors or fin-type multi-gate transistors with reference to the FinFET elements used herein. Such an element may include a P-type metal oxide semiconductor FinFET element or an N-type metal oxide semiconductor FinFET element. The FinFET component can be a dual gate component, a triple gate component, a monolithic component, a top-sand insulation (SOI) component, and/or other configurations. One of the conventional techniques is understood to be that other examples of semiconductor components can be used in other aspects of the present disclosure. For example, some embodiments described herein may also be applied to a gate surrounding (GAA) component, an omega gate (Ω gate) component, or a Pi gate (II gate) component.

1 illustrates a method 100 of fabricating a semiconductor that includes fabricating a fin having a dopant-free channel disposed on a board. The term "dopant-free" material as used herein is used to describe a material (eg, a semiconductor material) having an extrinsic dopant having a concentration of from about 0 cm" ³ to about 1 x ¹⁰¹⁷ cm" ³ . In some examples, the term "zero dopant" as used herein may be used interchangeably with "no dopant" having a similar meaning. Additionally, in some embodiments, the terms "zero dopant" and "non-dopant" as used herein may be applied to sheet regions, fin regions, or non-artificial doping (eg, by ion implantation processes, diffusion processes, or Other regions of non-human doping formed by other doping processes. As described below, the presence of a dopant in the channel of the electronic component can cause the carrier to be dispersed in the active electronic component, thereby greatly degrading the performance of the electronic component. As described below, electronic components, such as FinFET electronic components, having a zero-doped channel region that is substantially epitaxially grown without dopants greatly improve the performance of the electronic components (eg, increase the operation of electronic components) Current in). As used herein, "dopant" or "external dopant" is used to describe an impurity (eg, B, P, As, etc.) that can be introduced into a semiconductor crystal lattice, thereby altering the electrical properties of the semiconductor. For example, an N-type impurity can be used for a semiconductor forming an N-type material, and a P-type impurity can be used for a semiconductor forming a P-type material. It should be understood that the method 100 includes the steps of a technical process flow feature having a complementary metal oxide semiconductor (CMOS) and is therefore only briefly described herein. Other steps may be performed before, after, and/or during method 100.

2A, 3, 4A, 5A, 6A, 7A, 8, 9, 10A, 11A, 12A, 13A, and 14-18 are isometrics of an embodiment of the method 100 shown in FIG. view. 2B, 4B, 5B, 6B, 7B, 10B, 11B, 12B, and 13B are cross-sectional views of embodiments of semiconductor device 200 in accordance with various stages of method 100 illustrated in FIG. 1, corresponding to respective isometric views. It should be understood that the semiconductor component 200 can be fabricated by a CMOS technology process, and thus some processes are only briefly described herein. Additionally, semiconductor component 200 can include various other components and structures, such as components (eg, additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory) Other types of (SRAM) and/or other logic circuits, etc. However, it is simplified for a better understanding of the disclosure. In some embodiments, semiconductor component 200 includes a plurality of semiconductor components (eg, transistors) that can be interconnected, including PFETs, NFETs, and the like. In addition, it is to be understood that the process steps of the method 100 (including the description given with reference to FIGS. 2-18) are merely exemplary and are not intended to be limited to the scope specifically described in the following claims.

The method 100 begins at block 102 by providing a substrate. Referring to the example in FIG. 2, in an embodiment of block 102, a substrate 202 is provided. In some embodiments, substrate 202 It may be a semiconductor substrate such as a germanium substrate. The substrate 202 can include various layers including a conductive layer and an insulating layer formed on the semiconductor substrate. Substrate 202 can include various doping configurations well known in the art, depending on the design requirements. Substrate 202 may also include other semiconductors such as germanium, tantalum carbide (SiC), germanium telluride (SiGe), or diamond. Alternatively, substrate 202 can comprise a compound semiconductor and/or an alloy semiconductor. In addition, the substrate 202 can optionally include an epitaxial layer (epi layer) for coping with improved performance, including on-insulator (SOI) structures, and/or other suitable refinement structures.

The method 100 then proceeds to block 104 where the APT deployment is performed. Referring to the examples in Figures 2A and 2B, an embodiment of block 104 is shown. In some embodiments, a first photolithography (photograph) step is performed to pattern a P-type anti-punch through (APT) region 204. For example, in some embodiments, performing the first photo step may include forming a photoresist layer (resistance) on the substrate 202, exposing the photoresist to a pattern (eg, a P-type APT implant mask), performing post-development bake The baking process is performed and the photoresist is developed to form a patterned photoresist layer 208. As shown in FIG. 2A, after forming the patterned photoresist layer 208, an ion implantation process 212 is performed in the P-type APT region 206 of the substrate 202 while the N-type APT region 204 remains covered by the photoresist layer 208. For example, the P-type dopant implanted into the P-type APT region 206 by the ion implantation process 212 can include boron, aluminum, gallium, indium, or other P-type acceptor materials. After the ion implantation process 212, the photoresist layer 208 can be removed, for example, by solvent, photoresist stripping, ashing, or other suitable technique. Thereafter, in some embodiments, a second photo step is performed, wherein the second photo technique can include forming a photoresist layer on the substrate 202, exposing the photoresist to a pattern (eg, an N-type APT implant mask), implementing A post-development baking process is performed and the photoresist is developed to form a patterned photoresist layer 210. As shown in FIG. 2B, after forming the patterned photoresist layer 210, an ion implantation process 214 is performed in the N-type APT region 204 of the substrate 202 while the P-type APT region 206 remains covered by the photoresist layer 210. For example, the N-type dopant implanted into the N-type APT region 204 by the ion implantation process 214 can include arsenic, phosphorus, antimony or other N-type donor materials. After the ion implantation process 214, the photoresist layer 210 can be removed, for example, by solvent, photoresist stripping, ashing, or other suitable technique. It should be understood that the first and second photo steps can be performed in any order, for example, the N-type APT region 204 can be implanted prior to the P-type APT region 206. Moreover, in various embodiments, the APT arrangement can have a high dopant concentration, for example, between about 1 x 10 ¹⁸ cm ^-3 and 1 x 10 ¹⁹ cm ^-3 . As described below, such a high APT dopant concentration can be better utilized due to the presence of a subsequently formed dielectric layer on the APT implant substrate that is used to prevent dopant diffusion.

Implementing the APT implant process 212, 214 prior to forming the FinFET fin structure can avoid FinFET fin damage and component degradation. For example, as will be described below, in an existing semiconductor process flow, an ion implantation process (eg, an APT ion implantation process) is performed by a FinFET fin element, which may cause damage to the fin element, including damage to the FinFET channel region, It can lead to carrier scattering and thus to reduced component performance. Although high temperature annealing can be used to attempt to remove such defects (also used for dopant activation), it does not remove all defects due to ion implantation, and the substrate (or fin element) can therefore not be restored to it. The state before ion implantation. Furthermore, dopant implantation by FinFET fin elements can result in a non-uniform doping profile that includes dopants distributed within the FinFET channel region. It is well known in the art that increasing the doping concentration in the channel of the element can increase the mobility of the element due to ion implantation sputtering.

The embodiments of the present disclosure provide benefits on the basis of the prior art, but it should be understood that other embodiments may provide different benefits, and the benefits described herein are not all necessary, and there is no special Advantageous effects can be applied to all embodiments. For example, the embodiments described herein include methods and structures for preventing degradation of semiconductor components resulting from ion implantation processes, such as APT ion implantation processes, including formation of defects and introduction of channel impurities. In some embodiments, the N-type APT region 204 and/or the P-type APT region 206 (as described above) are implanted prior to forming the FinFET fin elements (as described below). Therefore, deterioration of APT ion implantation is avoided. In some embodiments, an epitaxially grown zero dopant channel layer is formed on the APT implant substrate as described below. Moreover, in various embodiments, the epitaxially grown zero dopant channel layer is separated from the APT implant substrate by an oxide layer that serves to prevent diffusion of the APT dopant. Due to this beneficial effect of the oxidative barrier layer, the APT implant can have a high dopant concentration, for example between about 1 x 10 ¹⁸ cm ^-3 and 1 x 10 ¹⁹ cm ^-3 . In some embodiments, since the epitaxially grown zero dopant channel layer is substantially free of dopants, carrier channel sputtering is mitigated and the mobility and drive current of the components are improved. In various embodiments, the zero dopant channel layer (and active element channel) has a dopant concentration of less than 1 x 10 ¹⁷ cm ^-3 . In some processes, including the use of an oxidized SiGe layer to prevent diffusion, the SiGe layer may not be completely oxidized, which causes Ge residue to be detrimental to the performance of the component. Thus, as described below, embodiments of the present disclosure further provide a method for fully oxidizing a SiGe layer while also providing a method of reducing and/or eliminating the above Ge residue without damaging the height or width of the FinFET. Additionally, it should be noted that the methods and structures described herein can be used with NFET or PFET components. In addition, although the description herein is primarily directed to FinFET components, one of ordinary skill in the art to which the present disclosure pertains is to be understood that the methods and structures described herein can be equally applied to components without departing from the scope of the present disclosure. Other types. In addition, other embodiments and advantageous effects will be readily apparent to those skilled in the art in view of this disclosure.

Referring to Figure 1, method 100 then proceeds to block 106 by growing one or more epitaxial layers. Referring also to the example of FIG. 3, in the embodiment of block 106, an epitaxial layer 302 is formed on the APT implant substrate 202, and an epitaxial layer 304 is formed over the epitaxial layer 302. In some embodiments, epitaxial layer 302 has a thickness ranging from about 2-10 nm. In some embodiments, the epitaxial layer 304 has a thickness ranging from about 30-60 nm. For example, epitaxial growth of layers 302, 304 can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers 302, 304 have the same material as the substrate 202. In some embodiments, the epitaxially grown layers 302, 304 have a different material than the substrate 202. In at least some examples, epitaxial layer 302 includes an epitaxially grown germanium telluride (SiGe) layer, and epitaxial layer 304 includes an epitaxially grown germanium (Si) layer. Alternatively, in some embodiments, any of the epitaxial layers 302, 304 may include other materials such as germanium; (such as tantalum carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or A compound semiconductor of indium telluride; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or a combination thereof. In various embodiments, the epitaxial layers 302, 304 are substantially non-dopant (ie, have an extrinsic dopant concentration of from about 0 cm ^-3 to 1 x 10 ¹⁷ cm ^-3 ), wherein, for example, in epitaxial growth No intentional doping steps were performed in the process. As described in more detail below, epitaxially grown zero dopant epitaxial layer 304 can be used as a channel region for subsequent formation of FinFET elements. Thus, carrier scattering through the FinFET channel can be substantially reduced for FinFET components, including the substantially dopant-free epitaxially grown zero dopant epitaxial layer 304 described herein.

In various embodiments, the epitaxial layer 302 has a first rate of oxidation, and the epitaxial layer 304 has a second rate of epitaxy that is lower than the first rate of epitaxy. For example, in an embodiment (the epitaxial layer 302 includes SiGe and the epitaxial layer 304 includes Si), the rate of oxidation of Si in the epitaxial layer 304 is lower than the rate of oxidation of SiGe in the epitaxial layer 302. During the subsequent oxidation process (after formation of the FinFET fin elements), as described below, portions of the fin elements including the epitaxial layer 302 may be completely oxidized while only the sidewall portions of the fin elements including the epitaxial layer 304 may be oxidized. In some embodiments, for example, the fully oxidized portion of the epitaxial layer 302 in the fin element is used to prevent diffusion of the APT dopant prior to implantation of the APT dopant into the substrate 202 such that the APT dopant will not Diffusion into the subsequently formed FinFET channel. Also, in some embodiments, the oxidized sidewalls of the epitaxial layer 304 in the fin element are used to fine tune the shape of the fin element while forming the FinFET channel.

Also in the example shown in FIG. 3, a hard mask (HM) layer 306 can be formed on the epitaxial layer 304. In some embodiments, HM layer 306 includes an oxide layer 308 (eg, a pad oxide layer that can include SiO ₂ ) and a nitride layer 310 formed over oxide layer 308 (eg, can include Si ₃ N ₄ Pad nitride layer). In some examples, oxide layer 308 can include thermally grown oxide, CVD deposited oxide, and/or ALD deposited oxide, and nitride layer 310 can include a nitride layer deposited by CVD or other suitable technique. . For example, oxide layer 308 can have a thickness between about 5 nm and about 40 nm. In some embodiments, the nitride layer 310 can have a thickness between about 20 nm and about 160 nm.

The method 100 then proceeds to block 108 to form a fin element for subsequent FinFET formation. Referring to the examples in FIGS. 4A and 4B, in the embodiment of block 108, a plurality of fin elements 402 extending from the substrate 202 are formed. In various embodiments, each of the fin elements 402 includes a substrate portion 202A formed from the substrate 202, a first epitaxial layer 302A formed from the epitaxial layer 302, and a second Lei formed from the epitaxial layer 304. The crystal layer 304A and the HM layer portion 306A (including the oxide layer portion 308A and the nitride layer portion 310A) formed from the HM layer.

Like the substrate 202, the fins 402 may include germanium or another element (such as germanium) semiconductor; compound semiconductors such as tantalum carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide An alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or a combination thereof. The fins 402 can be fabricated using a verified process including photolithography and etching processes. The lithography process can include forming a photoresist layer on the substrate 202 (eg, on the HM layer 306 in FIG. 3), exposing the photoresist to the pattern, performing a post-development bake process, and developing the photoresist to form light having Resistive mask element. In some embodiments, patterning the photoresist to form a masking element can be implemented using electron beam (e-beam) lithography. The masking element can then be used to protect the area of the substrate 202 and the layer formed thereby, while forming an etch process through the HM layer 306, through the epitaxial layers 302, 304, and into the substrate in an unprotected area. Channel 404 of 202, thereby leaving a plurality of extended fins 402. Channel 402 can be etched using dry etching (eg, reactive ion etching), wet etching, and/or other suitable processes. Many other embodiments of the method of forming the fins can also be employed. As described in more detail below, in some embodiments, the second epitaxial layer portion 304A can be used as a FinFET element channel. In addition, since the second epitaxial layer portion 304A is a zero dopant, and the dopant is always maintained during the fabrication of the device as described below, the FinFET The channel region thus essentially remains free of dopants. Thus, in accordance with embodiments of the present disclosure, FinFET carrier channel scattering is mitigated and component mobility and drive current are improved.

As shown in Figures 4A and 4B, the sidewalls of the fins 402, particularly the second epitaxial layer portion 304A, are substantially vertical. In various embodiments, this vertical fin profile improves the component performance of the FinFET. In some cases, the fins 402 are formed, initially allowing the fins 402 to have a wedge shape. However, in some embodiments, as described below, a subsequent implementation of the oxidation process can be employed to adjust the profile of the fins 402 and thereby form vertical sidewalls.

The method 100 then proceeds to block 110 where a trimming process is performed. Referring to the example in FIGS. 4A/5A, in an embodiment of block 110, the first epitaxial layer portion 302A is trimmed to form a trimmed epitaxial layer portion 302B. In various embodiments, as described below. Forming the trimmed epitaxial layer portion 302B ensures that the epitaxial layer portion 302B can be completely oxidized during the subsequent oxidation process. For example, in embodiments where epitaxial layer 302 includes SiGe, trimmed epitaxial layer portion 302B may also include SiGe. Therefore, during the subsequent oxidation process, the SiGe trimmed epitaxial layer portion 302B will be completely oxidized. In some embodiments, the trimming process used to form the trimped epitaxial layer portion 302B includes an etch process such as a wet etch process. For example, the etchant used in the trimming process may include a mixture of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) (referred to as a mixture of sulfur peroxide (SPM)), ammonium hydroxide (NH ₄ OH). a mixture of H ₂ O ₂ and water (H ₂ O) (referred to as ammonium percarbonate mixture (APM)), a mixture of NH ₄ OH and H ₂ O ₂ , H ₂ O ₂ and/or other etching well known in the art. Agent. Alternatively, in some embodiments, the trim process may include a dry etch process or a dry/wet etch process combination.

The method 100 then proceeds to block 112 where the oxidation process is performed. Referring to the examples in FIGS. 5A/6A and 5B/6B, in an embodiment of block 112, element 200 is exposed to an oxidation process that completely oxidizes the trimmed epitaxial layer portion of each of the plurality of fin elements 402 302, thereby forming an oxide layer 302C. In some embodiments, the oxide layer 302C (eg, can include a SiGe oxide layer) has a thickness ranging from about 5-20 nm. In various realities In an embodiment, the oxidation process may also form an oxide layer 602 on one or more of the substrate 202, the substrate portion 202A, the second epitaxial layer portion 304A, and the HM layer portion 306A. In some examples, the oxidation process can be implemented to expose the original 200 to a wet oxidation process, a dry oxidation process, or a combination thereof. In at least some embodiments, element 200 is exposed to a wet oxidation process using a vapor or water stream as an oxidant at a pressure of about 1 ATM, a temperature range of about 400-600 ° C, and a time of about 0.5-2 hours. . It should be understood that the oxidation process environment provided herein is merely exemplary and is not intended to be limited thereto. As shown in Figures 6A/6B, the oxidation process also simultaneously oxidizes sidewalls 304SW of second epitaxial layer portion 304A (e.g., instead of oxidizing all of second epitaxial layer portion 304A). In some embodiments, the contour of the oxidized adjustable fin 402 of the sidewall 304SW is provided, for example, to reduce and/or adjust the wedge profile formed prior to the fin 402 (eg, after forming the fin element at block 108).

As noted above, in some embodiments, the first epitaxial layer portion 302A (and the trimmed epitaxial layer portion 302B) can include a material having a first oxidation rate, and the second epitaxial layer portion 304A can include a first A material having a rate of oxidation wherein the second rate of oxidation is lower than the rate of first oxidation. For example, in an embodiment where (the first epitaxial layer portion 302A (and the trimmed epitaxial layer portion 302B) comprises SiGe and the second epitaxial layer portion 304A includes Si), a higher SiGe oxidation rate (ie, Compared with Si) it is ensured that the SiGe layer (i.e., the trimmed epitaxial layer portion 302B) can be completely oxidized, while only the sidewall portion of the Si layer (i.e., the second epitaxial layer portion 304A) is oxidized. It should be understood that any of the above plurality of materials may optionally act on the first and second epitaxial layer portions 302A and 304A as long as the oxidation rate of the second epitaxial layer portion 304 is lower than the first epitaxial layer. The oxidation rate of layer portion 302A (and lower than the rate of oxidation of trimmed epitaxial layer portion 302B). In this manner, the fully oxidized layer 302C of each of the fin elements 402 serves to prevent the APT dopant from diffusing prior to implantation into the substrate 202, while exhibiting that the substrate portion 202A is directly below the oxide layer 302C. Thus, in various embodiments, the oxide layer 302C is used to prevent diffusion of APT dopants in the substrate portion 202A into the second epitaxial layer portion 304A while serving as a subsequent shape. The channel region of the FinFET element. Moreover, in some embodiments, the profile of the fins 402 can also be adjusted by adjusting oxidation on the sidewalls 304SW of the second epitaxial layer portion 304A. It will also be understood by those skilled in the art that the oxidation process environment can be selected to tailor the fins 402 to any number of profiles, depending on the desired design of the component, process technology, or other process conditions.

Returning to the description of the oxidized trimmed epitaxial layer portion 302B, wherein the trimmed epitaxial layer portion 302 comprises SiGe, it is understood that in the further SiGe layer, Ge is relatively more oxidized than Si. complex. Therefore, as described above, a portion of the material (for example, Ge) in the trimmed layer portion 302B may be diffused into one or both of the second epitaxial layer portion 304A and the substrate portion 202A during the oxidation process. Thereby, a residual material portion 302R is formed. In various embodiments, the residual material portion 302R includes non-oxidized Ge residues and/or Ge that is only partially oxidized. In various examples, such residual Ge in the residual material portion 302R (and individual residual Ge in the residual material portion 302R in the second epitaxial layer portion 304A) presents reliability issues for subsequent fabrication of the FinFET element. Therefore, it is desirable to remove the residual Ge in the residual material portion 302R, especially for the second epitaxial layer portion 304A, since the second epitaxial layer portion 304A will serve as the element channel for subsequent fabrication of the component. Thus, as described below, embodiments of the present disclosure provide a method of removing such Ge residues without damaging the fin 402 height and/or fin 402 width, while also serving to improve the performance of the FinFET elements.

The method 100 then proceeds to block 114 where an oxide etch process is performed. In an embodiment of block 114, element 200 can be exposed to an etch process for one of substrate 202, substrate portion 202A, second epitaxial layer portion 304A (eg, sidewall 304SW), and HM layer portion 306A. The oxide layer 602 is removed in more or more. In some embodiments, the etching process can also remove a portion of the oxide layer 302C. In some embodiments, the oxide etch process includes a wet etch process, wherein the etchant for wet etching can include hydrofluoric acid (HF) (eg, HF weights up to 49% by weight of H ₂ O) and deionization (DI) a dilute mixture of H ₂ O wherein the ratio of HF:H ₂ O is about 1:50, about 1:100 or other suitable ratio. Alternatively, in some embodiments, the etching process may include a dry etching process or a combination of dry/wet etching processes.

The method 100 then proceeds to block 116 where the liner layer is deposited and annealed. Referring to the examples in FIGS. 6A/7A and 6B/7B, after the oxide layer 602 is removed by the oxidative etch process in block 114 and one of the blocks 116, the pad layer 702 can then be deposited on the device. 200 and enters into channel 404. In some embodiments, the liner layer 702 comprises tantalum nitride deposited by CVD or other suitable technique. In some embodiments, the liner layer 702 can include another material such as hafnium oxynitride, aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum oxynitride (AlON), and/or well known in the art. Other suitable materials. In various embodiments, the material selected for the liner layer 702 includes materials that can be easily removed by a wet etch process. In some examples, the material selected for the liner layer 702 includes a material that has the ability to resist oxidation (eg, to prevent annealing during the annealing process). In some embodiments, since the oxide layer 602 is completely removed in block 114, the deposited liner layer 702 can be at least directly with the second epitaxial layer portion 304A, the oxidized layer 302C, and the substrate portion 202A. Contact is shown in Figure 7A/7B. For example, the liner layer 702 can have a thickness between about 3 nm and about 8 nm. In some embodiments, after forming the liner layer 702, the component 200 can be subjected to an annealing process to remove defects therefrom and improve the quality of the liner layer 702. For example, in some embodiments, the liner layer 702 can be annealed at a temperature of about 750 ° C to 1050 ° C for a time of about 30 s to 30 min. In various embodiments, the liner layer can be annealed at a pressure of about 1 ATM and, in some cases, under a nitrogen (N ₂ ) environment.

The method 100 then proceeds to block 118 to form an isolation zone. Referring to the examples in Figures 7A/7B, 8 and 9, in the embodiment of block 118, a plurality of isolation regions 902 (Figure 9) are formed. In some embodiments, the plurality of isolation regions 902 can include a plurality of shallow trench isolation (STI) structures. For example, in some embodiments, dielectric layer 802 (FIG. 8) is first deposited on substrate 202, and trench 404 is filled with dielectric layer 802. In some embodiments, dielectric layer 802 can comprise SiO ₂ , tantalum nitride, hafnium oxynitride, fluorine-doped tellurite glass (FSG), low dielectric materials, combinations thereof, and/or other suitable well known in the art. s material. In various examples, dielectric layer 802 can be deposited by a CVD process, a low pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. In some embodiments, after depositing dielectric layer 802, element 200 is annealed to improve the quality of dielectric layer 802. In some embodiments, the oxide field, the LOCOS structure, and/or other suitable isolation structures may be additionally or alternatively implanted on the substrate and/or implanted within the substrate. However, other embodiments are also possible. For example, in some embodiments, dielectric layer 802 (and subsequently formed isolation regions 902) can comprise a multi-layer structure, for example, having one or more liner layers. After deposition of the dielectric layer 802, the deposited dielectric layer 802 is thinned and the deposited dielectric layer 802 is polished, for example, by a CMP process. Referring to Figure 9, there is shown an element 200 in an intermediate process stage, i.e., performing a CMP process to remove excess material from the dielectric layer 802, grinding the top surface of the element 200, and thereby forming an isolation region 902. In some embodiments, isolation region 902 is configured to isolate a fin active region (eg, second epitaxial layer portion 304A).

Referring to Figures 8 and 9, and in some embodiments, a CMP process for the top surface of the abrasive element 200 and forming the isolation region 902 can also be used to remove the HM layer portion 306A from the plurality of fin elements 402. In some embodiments, removing the HM layer portion 306A includes removing the oxide layer portion 308A and the nitride layer portion 310A. Removal of HM layer portion 306A (including removal of oxide layer portion 308A and nitride layer portion 310A) can be selectively performed by employing a suitable etching process (eg, dry or wet etching). After the HM layer portion 306A is removed from the top of each of the fin elements 402, whether a CMP process or an etch process is employed, the second epitaxial layer portion 304A under each of the fin elements 402 is exposed.

The method 100 then proceeds to block 120 even if the isolation region is recessed. Referring to the examples in FIGS. 9 and 10A/10B, in the embodiment of block 120, the isolation region 902 surrounding the fin element 402 is recessed to laterally expose the upper portion 402A of the fin element 402. In some embodiments, the recess process can include a dry etch process, a wet etch process, and/or combinations thereof. For example, the recess may include a dry process non-ionic recess process, which uses a reaction gas or reaction gas composition (such as _{HF + NH 3, NF 3 +} NH 3 and / or other suitable reaction gas). In some embodiments, the dry ionless recess process is performed using a CERTAS® gas chemical etching system (available from Tokyo Electron Limited, Tokyo, Japan). In some embodiments, the dry ionless recess process is implemented using a SICONI® system (available from Applied Materials, Inc., Santa Clara, Calif.). In some examples, the recess process can include wet etching using a hydrofluoric acid (HF) (eg, HF weight of 49% by weight of H ₂ O) and a dilute mixture of deionized (DI) H ₂ O, wherein The ratio of HF:H ₂ O is about 1:50, about 1:100 or other suitable ratio.

In some embodiments, the depth of the recess is controlled (eg, by controlling the etch time) to obtain the desired height "H" of the upper portion 402A that the fin element 402 has exposed. As shown in FIG. 10B, for example, each of the plurality of fins 402 has a height "H _FIN " and a width "W _FIN " that define at least a portion during formation of the fin element in block 108. In some examples, the fin height "H _FIN " may be between about 30 nm and 60 nm (eg, as defined by the thickness of the epitaxial layer 304), and the fin width "W _FIN " may be between about 4 nm and 10 nm ( For example, it is defined by the formation of the fin process in block 108). In various embodiments, the depth of the recess of the isolation region 902 is controlled such that the top surface 904 of the recessed isolation region 902 is disposed on a horizontal plane on the horizontal plane 402BP, wherein the horizontal surface 402BP is defined by the fin bottom surface 402B. Thus, in such an embodiment, the height "H" of the exposed upper portion 402A of the fin 402 can be less than the fin height "H _FIN " (eg, less than between about 30 nm and 60 nm). In some embodiments, the depth of the recess of the isolation region 902 is controlled such that the top surface 904 of the recessed isolation region 902 is disposed in a horizontal plane that is substantially coplanar with the horizontal plane 402BP defined by the fin bottom surface 402B. Thus, in such an embodiment, the height "H" of the exposed upper portion 402A of the fin 402 is substantially the same as the fin height "H _FIN " (eg, substantially between about 30 nm and 60 nm). Thus, in general, the top surface 904 of the recessed isolation region 902 can be aligned with the plane 402BP or can also be above the plane 402BP (which is defined by the fin bottom surface 402B). Undesirable parasitic capacitance can be avoided by controlling the height of the recessed isolation regions 902 described herein. In addition, reducing and/or avoiding such parasitic capacitances can avoid loss of performance of high quality AC components (eg, losses due to reduced RC delay).

The method 100 then proceeds to block 122 to etch the liner layer. Referring to the examples in FIGS. 10A/10B and 11A/11B, in an embodiment of block 122, the liner layer 702 is etched to expose the residual Ge of the residual material portion 302R in the second epitaxial layer portion 304A. In some embodiments, the process for etching the liner layer 702 can include a wet etch process, a dry etch process, and/or combinations thereof. In some embodiments, the liner layer 702 can be etched using a wet etch process that performs heated phosphoric acid (H ₃ PO ₃ ). However, in some embodiments, other wet and/or dry etchants may also be used to etch liner layer 702 without departing from the scope of the present disclosure. Moreover, in some embodiments, the etch process (eg, the etch process of the liner layer 702) can include an over etch process that can result in the formation of a void 1102 adjacent to the second epitaxial layer portion 304A, the second epitaxial layer Portion 304A exposes the residual Ge of residual material portion 302R therein. In some embodiments, the over etch process can also expose at least a portion of the fin bottom surface 402B. In some embodiments, the liner layer 702 can be over etched by about 2 nm to 6 nm. In some examples, the overetch process may also include etching the etchant of the oxide layer 302C, and thus etching more fin bottom surfaces 402B. In some cases, the oxide layer 302C may also employ the same etchant used to etch the liner layer 702. In some embodiments, the etched layer 302C may employ an etchant different than that used to etch the liner layer 702. In some examples, the etchant is selective, i.e., only the liner layer 702 can be etched without etching the oxide layer 302C. Thus, after etching the liner layer 702, the residual Ge of the residual material portion 302R in the second epitaxial layer portion 304A is exposed and can be subsequently removed.

It should be noted that, in at least some existing solutions, in order to expose residual Ge in such residual material portion 302R (eg, in second epitaxial layer portion 304A), it is necessary to recess isolation region 902, thereby The top surface 904 of the recessed isolation region 902 is lower than the plane 402BP defined by the fin bottom surface 402B (Fig. 10B). This can result from being as described above The generation of the built-in capacitance reduces the AC performance of the subsequently fabricated components. Moreover, by forming the liner layer 702 prior to forming the isolation regions 902, embodiments of the present disclosure help to avoid the above problems. In particular, as described above, the presently disclosed embodiment including the backing layer 702 ensures that the top surface 904 of the recessed isolation region 902 remains substantially aligned with or above the plane 402BP defined by the fin bottom surface 402B (avoiding Reducing efficient AC performance) also provides for residual Ge that exposes the residual material portion 302R at the fin bottom surface 402 and/or adjacent to the fin bottom surface 402B via etching and/or over etching for the liner layer 702.

The method 100 then proceeds to block 124 to clean up the residual Ge. Referring to the examples in FIGS. 11A/11B and 12A/12B, in the embodiment of block 124, the exposed residual Ge can be removed by the etching process used to etch the liner layer 702 in block 122. In some embodiments, the process for cleaning Ge residues can include a wet etch process, a dry etch process, and/or combinations thereof. In some embodiments, the exposed Ge residue is cleaned (ie, etched or removed) using a mixture of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) (referred to as a mixture of sulfur peroxides ( SPM)), ammonium hydroxide (NH ₄ OH), a mixture of H ₂ O ₂ and water (H ₂ O) (referred to as ammonium percarbonate mixture (APM)), a mixture of NH ₄ OH and H ₂ O ₂ , H ₂ O ₂ and/or other etchants well known in the art. Alternatively, in some embodiments and in at least a portion of the overetches implemented in block 122, residual Ge may be removed from the residual material portion 302R, and residuals may also be removed from at least a portion of the fin bottom surface 402B. Ge. Thus, cleaning the residual Ge improves the performance of subsequently fabricated FinFET elements in accordance with the embodiments described herein.

The method 100 then proceeds to block 126 where a virtual gate stack is formed. Referring to the example in FIGS. 13A/13B, in an embodiment of block 126, a dielectric layer 1302 is formed. In some embodiments, dielectric layer 1302 is deposited on substrate 202 and fins 402, including within the channel between adjacent fins 402. In some embodiments, dielectric layer 1302 can comprise SiO ₂ , tantalum nitride, a high-k material, or other suitable material. In various examples, dielectric layer 1302 can be deposited by a CVD process, a low pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. For example, the dielectric layer 1302 can be used to prevent damage to the fin element 402 by subsequent processes (eg, a subsequently formed virtual gate stack).

Referring now to the example in FIG. 14, in another embodiment of block 126, gate stacking continues. For example, in some embodiments, gate stack 1402 is formed and sidewall spacers 1404 disposed on sidewalls of gate stack 1402 are formed. In one embodiment, the gate stack is a virtual gate stack. However, in some embodiments of method 100, gate stack 1402 can be a high dielectric constant/metal gate stack. Referring now to the replacement gate process description method 100, those skilled in the art will readily appreciate that the methods and structures described herein are equally applicable to gate priority processes. In some examples, the gate priority process includes forming a gate stack prior to forming the source/drain or prior to activating the source/drain dopant. For example only, the gate priority process may include gate dielectric and metal gate deposition, which is performed after a gate stack etch process for defining a gate critical dimension. In some embodiments of the gate priority process, forming the gate stack can be performed after forming the source/drain (which includes the doped source/drain regions), and in some examples it is at the active source/汲The polar dopant is then carried out.

In some embodiments employing a gate follow-up process, gate stack 1402 is a dummy gate stack and will be replaced by a final gate stack in a subsequent process stage of component 200. In particular, the gate stack 1402 can be replaced by a high dielectric constant layer (HK) and a metal gate electrode (MG) in a subsequent process stage. In some embodiments, the gate stack 1402 is formed on the substrate 202 and is at least partially disposed on the fin element 402. Additionally, in various embodiments, a gate stack 1402 is formed over the dielectric layer 1302 that forms a deposition as described above prior to forming the gate stack 1402. In some embodiments, the gate stack 1402 includes a dielectric layer 1406, an electrode layer 1408, and a hard mask 1410, which may include an oxide layer 1412 and a nitride layer 1414 formed over the oxide layer 1412. In some embodiments, gate stack 1402 is formed by various process steps such as layer deposition, patterning, etching, and other suitable process steps. In some examples, the layer deposition process includes CVD (which These include low pressure CVD and plasma enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. In some embodiments, the patterning process includes lithographic techniques (eg, photolithography or e-beam lithography), which may also include photoresist coating (eg, spin coating), soft baking, mask calibration , exposure, post-development baking, photoresist development, rinsing, drying (eg, spin-on drying and/or hard baking), other suitable lithographic techniques, and/or combinations thereof. In some embodiments, the etch technique family includes dry etching (eg, RIE etching), wet etching, and/or other etching methods.

In some embodiments, the dielectric layer 1406 of the gate stack 1402 includes hafnium oxide. Alternatively or in addition, the dielectric layer 1406 of the gate stack 1402 may comprise tantalum nitride, a high dielectric constant material, or other suitable material. In some embodiments, the gate stack electrode layer 1408 can comprise polysilicon (polysilicon). In some embodiments, the oxide layer 1412 of the hard mask 1410 includes a pad oxide layer that includes SiO ₂ . In some embodiments, the nitride layer 1414 of the hard mask 1410 includes a pad nitride layer comprising Si ₃ N ₄ , hafnium oxynitride or tantalum carbide.

In various embodiments, sidewall spacers 1404 are disposed on sidewalls of gate stack 1402. The sidewall spacer 1404 can include a dielectric material such as hafnium oxide, tantalum nitride, tantalum carbide, niobium oxynitride, or combinations thereof. In some embodiments, the sidewall spacer 1404 includes multiple layers such as a primary spacer sidewall and a liner layer. For example, sidewall spacers 1404 can be formed by depositing a dielectric material on gate stack 1402 and by etch back dielectric material. In some embodiments, an etch back process (eg, an etch back process for forming a pad) can include a multi-step etch process to improve etch selectivity and provide over etch control. In some embodiments, prior to forming sidewall spacer 1404, an ion implantation process is performed to form a small amount of doped drain (LDD) structure in semiconductor component 200. In other embodiments, such an LDD structure can be formed by epitaxial growth of the in-situ doped layer prior to forming the sidewall spacer 1404. In some embodiments, plasma doping (PLAD) may be employed to form the LDD structure. Also, in other embodiments, an ion implanter can be implemented after the sidewall spacer 1404 is formed. Art to form an LDD structure. In some embodiments, after forming the LDD structure, the semiconductor component 200 can be subjected to a high temperature pre-heating process (annealing) to eliminate defects and activate the dopant (ie, place the dopant in an alternate location). It should be understood that according to various embodiments, any potential APT dopant diffusion pre-planted and disposed in substrate region 202A (eg, due to a high temperature pre-heating process) will pass through the fully oxidized layer 302C prevents its diffusion into the FinFET channel region (ie, the second epitaxial layer portion 304A).

In some embodiments, still referring to the example in FIG. 14, after forming a dummy gate stack (eg, gate stack 1402), dielectric layer 1302 can be etched back to form dielectric region 1302A, and thereby exposing the fins Element 402 has no portion that is covered by gate stack 1402. In some embodiments, the etch back dielectric layer 1302 can include a wet etch process, a dry etch process, a multi-step etch process, and/or combinations thereof. Thus, retaining the dielectric layer 1302 during formation of the gate stack 1402 can help to effectively protect the fin elements 402 during such a process.

The method 100 then proceeds to block 128 to etch the fin elements. Referring to the examples in FIGS. 14 and 15, in the embodiment of block 128, portions of the fin element 402 on either side of the gate stack 1402 (the portion exposed due to the formation of the dielectric region 1302A) may be etched. The etched portion of the fin element 402 can include portions of the fin element 402 in the source/drain regions 1502, 1504 on either side of the gate stack 1402. In some embodiments, portions of the etched fin element 402 can be implemented using a dry etch process, a wet etch process, and/or combinations thereof. Moreover, in some embodiments, the portion of the oxide region below the etched portion of the fin element 402 is also etched, which portion can include an oxide layer 302C (eg, adjacent to the liner layer 702). In some embodiments, etching exposes the underlying substrate region 202A at an oxide region below the etched portion of the fin element 402. In various embodiments, etching the oxide region (eg, oxide layer 302C) under the etched portion of fin element 402 may be performed using a dry etch process, a wet etch process, and/or combinations thereof, it being noted that In the embodiments described herein, oxide layer 302C retains the existing underlying gate stack 1402 that helps prevent diffusion of APT dopant from substrate region 202A into the component channel region. (ie, the second epitaxial layer portion 304A covered by the gate stack 1402).

The method 100 then proceeds to block 130 to form a source/drain structure. Referring to the examples in FIGS. 15 and 16, in the embodiment of block 130, source/drain structures 1602, 1604 are formed in source/drain regions 1502, 1504. In some embodiments, source/drain structures 1602, 1604 are formed by epitaxially growing a layer of semiconductor material in source/drain regions 1502, 1504. In some examples, the dummy sidewall spacers may be formed prior to epitaxial source/drain growth and removed after epitaxial source/drain. Additionally, in some embodiments, as described above, the primary sidewall spacers may be formed after epitaxial source/drain growth. In various embodiments, the layer of semiconductor material grown in the source/drain regions 1502, 1504 can comprise Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source/drain structures 1602, 1604 can be doped in situ during the epi process. For example, in some embodiments, epitaxially grown SiGe source/drain structures 1602, 1604 can be doped with boron. In some embodiments, the epitaxially grown Si epi source/drain structures 1602, 1604 can be doped with carbon to form a Si: C source/drain structure, doped with phosphorus to form a Si:P source/drain structure. Or doping both carbon and phosphorus to form a SiCPU source/drain structure. In some embodiments, the source/drain structures 1602, 1604 may not be doped in-situ, and an arrangement process may be employed instead of doping the source/drain structures 1602, 1604. In various embodiments, the doping amount for doping the source/drain structures 1602, 1604 is greater than the doping amount for doping the LDD structure. In some embodiments, forming source/drain structures 1602, 1604 can be implemented by a separate process sequence that corresponds to each of the N- and P-type source/drain structures 1602, 1604. In some embodiments, after forming the source/drain structures 1602, 1604, an epi-annealing process is performed, ie, the semiconductor component 200 is subjected to a high temperature pre-heating process. However, as described above, the oxide layer (eg, oxide layer 302C), which remains below the gate stack 1402, will prevent any potential APT dopants from being in the substrate region 202A during such high temperature preheating processes. Diffusion enters into the element channel region (ie, the second epitaxial layer portion 304A covered by the gate stack 1402).

The method then proceeds to block 132 to form an interlayer dielectric (ILD) layer And remove the virtual gate stack. Referring to the examples in FIGS. 16 and 17, in the embodiment of block 132, an ILD layer 1702 is formed on the substrate 202. In some embodiments, a contact etch stop layer (CESL) is formed on the substrate 202 prior to forming the ILD layer 1702. In some examples, the CESL includes a tantalum nitride layer, a hafnium oxide layer, a hafnium oxynitride layer, and/or other materials well known in the art. CESL can be formed by a plasma enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 1702 includes materials such as ethyl orthosilicate (TEOS) oxide, zero-doped germanium or an antimony-doped oxide, such as borophosphonite glass (BPSG), melting Quartz glass (FSG), phosphonium silicate glass (PSG), boron-doped glass (BSG) and/or other suitable dielectric materials. The ILD layer 1702 can be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after forming the ILD layer 1702, the semiconductor component 200 can be subjected to a high temperature pre-heating process to anneal the ILD layer. As described above, the oxide layer (e.g., oxide layer 302C) prevents any potential APT dopant from diffusing from the substrate region 202A into the element channel region during such high temperature pre-heating processes. In some examples, a grinding process can be performed to expose the top surface of the virtual gate stack 1402. For example, the grinding process includes a chemical mechanical polishing (CMP) process that removes portions of the ILD layer 1702 (and the CESL layer (if present)) overlying the dummy gate stack 1402 and polishes the top surface of the semiconductor component 200. Additionally, the CMP process can remove the hard mask 1410 overlying the dummy gate stack 1402 to expose the electrode layer 1408, such as a polysilicon layer. Thereafter, in some embodiments, the previously formed virtual gate stack 1402 structure (eg, dielectric layer 1406 and electrode layer 1408) can be removed from the substrate. In some embodiments, electrode layer 1408 can be removed without removing dielectric layer 1406. Removing the electrode layer 1408 from the gate stack 1402 (or removing the electrode layer 1408 and the dielectric layer 1406) may thereby form the channel 1704, and may subsequently form a final gate structure in the channel 1704 (eg, as described below) , including high dielectric constant layer and metal gate electrode). The removal of the dummy gate stack structure can be performed using a selective etch process such as selective wet etch, signal dry etch, or a combination thereof.

The method 100 then proceeds to block 134 to form a high dielectric constant/metal gate stack. Referring to the examples in FIGS. 17 and 18, in the embodiment of block 134, a high dielectric constant/metal gate stack 1802 is formed in the channel 1704 of the component 200. In various embodiments, the high dielectric constant/metal gate stack includes an interface layer (which is formed substantially on the non-dopant channel material of the fin (ie, the second epitaxial layer portion 304A)), formed in the a high-k gate dielectric layer on the interface layer, and a metal layer formed on the high-k gate dielectric layer. The high-k dielectrics used and described herein include dielectric materials having a high dielectric constant (e.g., a dielectric constant (~3.9) of thermal yttrium oxide). The metal layer using the high dielectric constant/metal gate stack may comprise a metal, a metal alloy or a metal telluride. Additionally, forming a high dielectric constant/metal gate stack can include a deposition process to form various gate materials, one or more liner layers, and including one or more CMP processes to remove excess gate material and The top surface of the semiconductor element 200 is thus polished.

In some embodiments, the interface layer of the high dielectric constant/metal gate stack 1802 can include a dielectric material such as hafnium oxide (SiO ₂ ), HfSiO, or hafnium oxynitride (SiON). The interface layer can be formed by chemical oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable methods. The gate dielectric layer of the high dielectric constant/metal gate stack 1802 can include a high dielectric coefficient layer such as hafnium oxide (HfO ₂ ). Alternatively, a high dielectric constant / metal gate stack gate 1802. electrode dielectric layer may comprise other high-k dielectric, such as _{TiO2, HfZrO, Ta 2 O 3} , HfSiO 4, ZrO 2, ZrSiO 2, LaO , AlO, ZrO, TiO, Ta ₂ O ₅ , Y2O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , Si ₃ N ₄ , nitrogen oxides (SiON), combinations thereof, or other suitable materials. The high dielectric coefficient gate dielectric layer can be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and/or other suitable methods. The metal layer of the high dielectric constant/metal gate stack 1802 may comprise a single layer or alternatively a multilayer structure, such as a metal layer (with a selective work function to improve component performance (work function metal layer)), a liner layer Various combinations of wetting layers, bonding layers, metal alloys or metal halides. For example, the metal layer of the high dielectric constant/metal gate stack 1802 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W. , Re, Ir, Co, Ni, other suitable metallic materials or combinations thereof. Additionally, the metal layer provides an N-type or P-type work function, which can be an electro-optic (eg, FinFET) gate electrode, and in at least some embodiments, the metal layer of the high-k/metal gate stack 1802 can include polysilicon Floor. In various embodiments, the metal layer of high dielectric constant/metal gate stack 1802 can be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Additionally, different metal layers can be used to separately form the metal layers of the high dielectric constant/metal gate stack 1802 for N-FET and P-FET transistors. In various embodiments, a CMP process is performed to remove excess metal from the metal layer of high dielectric constant/metal gate stack 1802, and thereby provide a high dielectric constant/metal gate stack 1802 that is substantially flat The surface of the metal layer.

Semiconductor component 200 can also undergo processes known in the art to form various structures and regions. For example, a subsequent process can form an interlayer dielectric (ILD) layer (or layers), contact openings, contact metal, and various contact/hole/line and multilayer interconnect structures on substrate 202 (eg, A metal layer and an interlayer dielectric) configured to connect various structures to form a functional circuit comprising one or more FinFET elements. An advantageous aspect of this example is that it can include vertical interconnects (such as holes or contacts) and horizontal interconnects (such as metal lines). Various interconnect structures can employ a variety of conductive materials including copper, tungsten, and/or germanium. In one example, a damascene and/or dual damascene process is used to form a multilayer interconnect structure associated with copper. Moreover, other process steps can be performed before, during, and after method 100, and depending on various embodiments of method 100, some of the process steps described above can be replaced or omitted.

With regard to the description provided herein, the present disclosure provides a method and structure for avoiding generation due to ion implantation processes including formation of defects and introduction of channel impurities (ie, undesirable channel dopants). Degradation of semiconductor components. In some examples, one or more APT ion implantation processes are performed prior to forming the FinFET fin elements. In some embodiments, an epitaxially grown zero dopant channel layer is formed on the APT implant substrate. Moreover, in various embodiments, the epitaxially grown zero dopant channel layer is separated from the APT implant substrate by a dielectric layer, wherein the dielectric layer is used to block the APT dopant. Due to the beneficial effects of the oxide barrier layer, the APT implant can have a high dopant concentration, for example, between about 1 x 10 ¹⁸ cm ^-3 and 1 x 10 ¹⁹ cm ^-3 . In some embodiments, since the epitaxially grown zero dopant channel layer is substantially free of dopants, sputtering of the carrier channel is mitigated and the mobility of the components and the drive current are improved. Embodiments of the present disclosure also provide a method for fully oxidizing a SiGe layer that functions substantially as an oxidization barrier (eg, by trimming the SiGe layer prior to oxidation), and also for not damaging the FinFET height or width A method of reducing and/or eliminating Ge residue (for example, by inserting a tantalum nitride liner layer before forming the isolation region). The present disclosure also ensures that the top surface of the recessed isolation region can be substantially aligned with or above the plane defined by the fin bottom surface (e.g., above the oxide barrier), thus avoiding a reduction in AC performance. Those skilled in the art will readily appreciate that the methods and structures described herein can be applied to a variety of other semiconductor components without departing from the scope of the present disclosure, such that these other components also achieve the same benefits.

Accordingly, one of the embodiments of the present disclosure describes the fabrication of a semiconductor component (eg, a FinFET component) having a channel region that is substantially zero dopant. In some embodiments, the method includes forming a plurality of fins from the substrate. In various embodiments, each of the plurality of fins includes: a portion of the substrate, a portion of the first epitaxial layer on the portion of the substrate, and a second epitaxial layer on the portion of the first epitaxial layer a part of. For example, the portion of the first epitaxial layer of each of the plurality of fins is oxidized. In some embodiments, after oxidizing the portion of the first epitaxial layer, a liner layer is formed over each of the plurality of fins. In various examples, an isolation region that is adjacent to the recess of the liner layer is formed. Thereafter, the liner layer can be etched to expose a portion of residual material (eg, Ge residue) that is adjacent to the portion of the second epitaxial layer of each of the plurality of fins At the bottom, as well as removing the portion of the residual material.

In another embodiment, described is a method of depositing a first epitaxial layer on a substrate and depositing a second epitaxial layer on the first epitaxial layer. In some embodiments, a plurality of fins extending from the substrate are formed. In various examples, each of the plurality of fins includes a portion of the substrate, a portion of the first epitaxial layer on the portion of the substrate, and a second portion on the portion of the first epitaxial layer Part of the epitaxial layer. The portion of the second epitaxial layer has a height. In some examples, a liner layer is deposited on each of the plurality of fins. An isolation region can be formed that is adjacent to the liner layer and in contact with the liner layer. In some embodiments, the liner layer is etched to expose a portion of the remaining material that is adjacent to the bottom of the portion of the second epitaxial layer and that cleans the portion of the residual material layer. In some cases, the isolation region is recessed prior to etching the liner layer, the amount of depression being less than the height of the second epitaxial layer portion.

In another embodiment, a semiconductor component is described that includes a plurality of fins extending from a substrate. In some examples, each of the plurality of fins includes a first semiconductor layer, a dielectric layer on the first semiconductor layer, and a second semiconductor layer on the dielectric layer. For example, the second semiconductor layer includes a bottom surface that defines a first horizontal plane. In various embodiments, the semiconductor device further includes a recessed isolation region, the recessed isolation region abutting the plurality of fins, wherein the recessed isolation region includes a top portion adjacent to the second semiconductor layer, wherein the top portion defines a second horizontal plane, and wherein the second horizontal plane is disposed on the first horizontal plane. Additionally, the semiconductor component can include a gate stack formed on the second semiconductor layer.

The above summary of the features of several embodiments is provided to enable those skilled in the art to better understand the aspects of the disclosure. It will be appreciated by those skilled in the art that the present disclosure can be readily utilized as a basis for designing or modifying other processes to achieve the same objectives and/or achieve the same benefits. It should also be understood by those skilled in the art that such equivalent constructions may not depart from the spirit and scope of the disclosure, and Various changes, substitutions and alterations can be made without departing from the spirit and scope of the disclosure.

100-134‧‧‧ method

Claims (10)

A method of fabricating a semiconductor device, comprising: forming a plurality of fins extending from a substrate, wherein each of the plurality of fins comprises a portion of the substrate, a portion of a first epitaxial layer on the substrate, and a portion of the second epitaxial layer on the portion of the first epitaxial layer; oxidizing the portion of the first epitaxial layer of each of the plurality of fins; after oxidizing the portion of the first epitaxial layer Forming a liner layer over each of the plurality of fins; forming an isolation region adjacent to the recess of the liner layer; etching the liner layer to expose a portion of the residual material adjacent to the plurality of fins a bottom of the portion of the second epitaxial layer of each of the fins; and removing the portion of the residual material. The method of claim 1 wherein the portion of residual material comprises a germanium (Ge) residue. The method of claim 1 further comprising trimming the portion of the first epitaxial layer of each of the plurality of fins prior to oxidizing the portion of the first epitaxial layer. The method of claim 1, further comprising: performing anti-punch-through (APT) ion implantation in the substrate prior to forming the plurality of fins; and after performing APT ion implantation and before forming the plurality of fins, Depositing the first epitaxial layer on the substrate and depositing the second epitaxial layer on the first epitaxial layer. The method of claim 1 wherein the portion of the second epitaxial layer of each of the plurality of fins comprises an undoped epitaxial layer. The method of claim 1 wherein the first epitaxial layer has a first oxidation rate, and wherein the second epitaxial layer has a second oxidation rate that is lower than the first oxidation rate. A method of fabricating a semiconductor device, comprising: depositing a first epitaxial layer on a substrate, and depositing a second epitaxial layer on the first epitaxial layer; forming a plurality of fins extending from the substrate, wherein the plurality of Each of the fins includes a portion of the substrate, a portion of the first epitaxial layer on the portion of the substrate, and a portion of the second epitaxial layer on the portion of the first epitaxial layer, wherein the The portion of the second epitaxial layer has a height; a liner layer is deposited on each of the plurality of fins; an isolation region is formed, the isolation region is adjacent to the liner layer and in contact with the liner layer; etching the a liner layer to expose a portion of the residual material adjacent to a bottom portion of the portion of the second epitaxial layer; and cleaning the portion of the residual material layer. The manufacturing method according to claim 7, wherein the first epitaxial layer comprises germanium telluride (SiGe), wherein the second epitaxial layer comprises silicon (Si), and wherein the residual material portion comprises germanium (Ge) residues Things. A semiconductor component comprising: a plurality of fins extending from a substrate, wherein each of the plurality of fins comprises a first semiconductor layer, a dielectric layer on the first semiconductor layer, and a first layer on the dielectric layer a second semiconductor layer, wherein the second semiconductor layer comprises a bottom surface defining a first horizontal plane; a recessed isolation region, the recessed isolation region adjoins the plurality of fins, wherein the recessed isolation region comprises adjacent to the first a top of the second semiconductor layer, wherein the top defines a second horizontal plane, and wherein the second horizontal plane is disposed on the first horizontal plane; a pad layer adjacent to the isolation region of the recess; and a gate stack formed on the second semiconductor layer. The semiconductor device of claim 9 further comprising: said recessed isolation region, wherein said recessed isolation region comprises a first dielectric material, and wherein said first dielectric material comprises a void, said void being between said Between the bottom of the second semiconductor layer and the isolation region of the recess, and a second dielectric material, the second dielectric material fills the void.