TWI596617B - Contorl circuit applied in e-fuse system and related method - Google Patents

Description

Control circuit and related method applied to electronic fuse system

The present invention relates to an electronic fuse (E-fuse) system, and more particularly to a control circuit for an electronic fuse system and a related method.

A conventional semiconductor device includes a fuse circuit having a redundant memory cell, wherein the fuse circuit is programmed with the address of the damaged memory cell, and is used to determine whether to access a redundant memory cell. . Here, the word compile represents a series of cutting or non-cutting operations performed on a fuse for a corresponding target file, wherein the fuse is included in the fuse circuit, and is conventionally applied to a semiconductor device. The fuse circuit architecture requires a large amount of area and consumes considerable power.

One of the objects of the present invention is to disclose a control circuit for an electronic fuse system that can effectively reduce the use area and a related method to solve the above problems.

In accordance with an embodiment of the invention, a control circuit for use in an electronic fuse system is disclosed, wherein the control circuit is selectively operable in a feeding mode and a reading mode when the control circuit operates In the giving mode, the control circuit is configured to store a code, wherein the code indicates whether a fuse of the electronic fuse system is connected to the control circuit; and when the control circuit operates in the read mode The control circuit is configured to read a state of the fuse coupled to the control circuit.

According to an embodiment of the invention, a control method for an electronic fuse system includes: selectively operating in a giving mode and the reading mode, and storing a code when operating in the giving mode, wherein the program The code indicates whether a fuse of the electronic fuse system is connected; when operating in the read mode, a state of the fuse of the electronic system is read.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the device. The second device is indirectly electrically connected to the second device through other devices or connection means.

1 is a schematic diagram of an electronic fuse system 100 according to an embodiment of the present invention. As shown in FIG. 1, the electronic fuse system 100 includes a control circuit 101, a fuser 102, and a The fuse 103, wherein the control circuit 101 selectively operates in a feeding mode and a reading mode, and when the control circuit 101 operates in the giving mode, the control circuit 101 stores a code PROG, wherein the program The code PROG is used to indicate whether the fuse 103 and the control circuit 101 are connected through the fuse blower 102; when the control circuit 101 operates in the read mode, the control circuit confirms whether the fuse is connected or disconnected. The fuse blower 102 coupled to the control circuit 101 is configured to receive the code PROG stored in the control circuit 101 and determine whether to connect the fuse 103 to the control circuit 101 according to the code PROG.

2 is a schematic diagram of a control circuit 101 of an electronic fuse system 100 according to an embodiment of the present invention. As shown in FIG. 2, the control circuit 101 includes a latch circuit 201, a read circuit 202, and an initial circuit. 203 and an output terminal OT, wherein the latch circuit 201 is configured to store the code PROG on the output terminal OT when the control circuit 101 operates in the giving mode, and the read circuit 202 is coupled to the fuse 103, wherein the read The circuit 202 is configured to confirm the state of the fuse 103 when a read signal READ control circuit 101 enters the read mode, and the initial circuit 203 is coupled to a predetermined voltage VDD and is latched by an initial signal IN. The lock circuit 201 is initialized. The read circuit 202 can be implemented by a transistor. In this example, the read circuit 202 is a switching element implemented by an N-type metal oxide semiconductor field effect transistor (NMOSFET) SW1, and the N-type metal The oxide semiconductor field effect transistor SW1 is controlled by the read signal READ. In addition, in this embodiment, the initial circuit 203 is a switching element implemented by a P-type metal oxide semiconductor field effect transistor (PMOSFET) SW3, and the P-type metal oxide semiconductor field effect transistor SW3 system Controlled by the initial signal IN, it should be noted that this is merely an example and is not a limitation of the present invention. As shown in FIG. 2, a source terminal of the P-type MOSFET SW3 is coupled. Up to a preset voltage VDD, a gate terminal is coupled to the initial signal IN, and a terminal is coupled to an end point N1. A source terminal of the N-type MOSFET FET is coupled to the fuse 103. The gate is coupled to the read signal READ and the other terminal is coupled to an end point N1. In detail, the initial signal IN turns on the P-type transistor SW3 to pass the preset voltage VDD to the latch circuit 201 through the terminal N1 to initialize the logic value on the output terminal OT; and the read signal READ turns on the N-type transistor. SW1, and confirming the state of the fuse 103 by reading the logic value on the output terminal OT when the control circuit 101 operates in the read mode, the function and architecture of the latch circuit 201 will be discussed in subsequent paragraphs.

3 is a schematic diagram of a latch circuit 201 of the control circuit 101 according to an embodiment of the present invention. As shown in FIG. 3, the latch circuit 201 includes an input unit 301, a feedback unit 302, and an inverter INV. The input unit 301 includes a transistor T1, and the feedback unit 302 includes transistors T2, T3, and T4, and a switch SW2. In this embodiment, the transistors T1-T3 and SW2 are both N-type metal oxide semiconductors. The field effect transistor is implemented, and the transistor T4 is implemented by a P-type metal oxide semiconductor field effect transistor, but this is merely an illustrative example and is not a limitation of the present invention. As shown in FIG. 3, the source terminal of the transistor T1 is coupled to a predetermined voltage (in this embodiment, the ground terminal), the gate terminal is coupled to the code PROG, and the 汲 terminal is coupled to a source of the switch SW2. Extremely, in addition, a gate terminal of the switch SW2 is coupled to the signal FEED. A source terminal of the transistor T2 is coupled to the ground terminal, a gate terminal is coupled to the output terminal OT, and a terminal is coupled to a source terminal of the transistor T3. A gate terminal of the transistor T3 is coupled to the initial signal IN, and a terminal is coupled to the terminal N1. A source terminal of the transistor T4 is coupled to the preset voltage VDD, a gate terminal is coupled to the output terminal OT, and a terminal is coupled to the terminal terminal N1. An input of the inverter INV is coupled to the terminal N1, and an output of the inverter INV is coupled to the output terminal OT. Detailed operations in the grant mode and the read mode will be discussed in subsequent paragraphs.

Referring to FIG. 2, FIG. 3 and FIG. 4, FIG. 4 is a timing diagram of an initial signal, a read signal, and a signal given according to an embodiment of the present invention. As shown in FIG. 4, when the electronic fuse system 100 is used. At initialization, the initial signal IN is a logic value of 0, the initial circuit 203 is thus turned on and the preset voltage VDD (ie, logic value 1) is turned on to the terminal N1, and the logic value of the output terminal OT is thus changed to a logic value of 0, As such, the latch circuit 201 is successfully initialized. When the signal FEED is given a logic value of 1, the control circuit 101 operates in the giving mode, and the switch SW2 controlled by the giving signal FEED is thus turned on. At this time, the transistors T2, T3, T4 and the inverter INV form a latch. The latch is turned off, and the read circuit 202 and the initial circuit 203 are turned off. Figure 5 is a schematic diagram showing the operation of the control circuit in the giving mode according to an embodiment of the present invention. The transistor T1 receives the program code PROG and displays it on the output terminal OT. If the program code PROG is a logic value 1, the output terminal OT is The logical value 1 informs the fuse blower 102 coupled to the control circuit 101 to connect the fuse 103 to the read circuit 202 in the control circuit 101, otherwise the fuse 103 will be disconnected from the control circuit 101 when reading When the signal READ becomes a logic value 1, the control circuit 101 operates in the read mode, and FIG. 6 is a schematic diagram of the control circuit 101 operating in the read mode according to an embodiment of the present invention, and the N-type controlled by the read signal READ at this time. The transistor SW1 is turned on, and the initial circuit 203 and the switch SW2 are thus turned off, and the state of the fuse 103 is transmitted to the output terminal OT to indicate whether the fuse 103 is connected to the read circuit 202 through the fuse blower 102.

Briefly summarized, the present invention discloses a control circuit architecture applied to an electronic fuse system that can effectively reduce area usage and power loss. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Electronic fuse system

101‧‧‧Control circuit

102‧‧‧Fuse blower

103‧‧‧Fuse

PROG‧‧‧ Code

SW1, SW3‧‧‧ switch

READ‧‧‧ read signal

IN‧‧‧ initial signal

OT‧‧‧output endpoint

201‧‧‧Latch

202‧‧‧Read circuit

203‧‧‧ initial circuit

VDD‧‧‧preset voltage

T1-T4‧‧‧O crystal

N1‧‧‧ endpoint

INV‧‧‧ reverser

1 is a schematic view of an electronic fuse system in accordance with an embodiment of the present invention. 2 is a schematic diagram of a control circuit of an electronic fuse system according to an embodiment of the present invention. Figure 3 is a schematic diagram of a latch circuit of a control circuit in accordance with an embodiment of the present invention. Figure 4 is a timing diagram of an initial signal, a read signal, and a signal given in accordance with an embodiment of the present invention. Figure 5 is a schematic illustration of the control circuit operating in a mode of administration in accordance with an embodiment of the present invention. Figure 6 is a schematic illustration of the control circuit operating in a read mode in accordance with an embodiment of the present invention.

101‧‧‧Control circuit

103‧‧‧Fuse

OT‧‧‧output endpoint

201‧‧‧Latch circuit

PROG‧‧‧ Code

IN‧‧‧ initial signal

READ‧‧‧ read signal

203‧‧‧ initial circuit

202‧‧‧Read circuit

N1‧‧‧ endpoint

SW1, SW3‧‧‧ switch

Claims (18)

A control circuit for an electronic fuse (E-fuse) system, wherein the control circuit selectively operates in a feeding mode and a reading mode, when the control circuit operates in the giving mode The control circuit is configured to store a code, wherein the code is used to indicate whether a fuse is connected to the control circuit; when the control circuit operates in the read mode, the control circuit is used to read A state of the fuse coupled to the control circuit. The control circuit of claim 1, wherein the control circuit stores the code when the control circuit operates in the giving mode, and a fuse of the electronic fuse system determines whether the code is based on the code The fuse of the electronic fuse system is connected to the control circuit. The control circuit of claim 2 includes: an output terminal coupled to the fuse blower; a latch circuit coupled to the output terminal, wherein the control circuit operates In the giving mode, the latch circuit is configured to store the code on the output terminal; a read circuit is coupled between the fuse and the output terminal, wherein when the control circuit operates In the read mode, the read circuit is used to read the state of the fuse. The control circuit of claim 3, wherein the read circuit comprises a first switch, and when the control circuit operates in the read mode, the read circuit receives a read signal to turn on the first switch. This state of the fuse is read. The control circuit of claim 4, wherein the latch circuit comprises a second opening Off, and when the control circuit operates in the giving mode, the latch circuit receives a give signal to turn on the second switch to store the code and close the first switch. The control circuit of claim 3, wherein the latch circuit includes an input unit for receiving the code and a feedback unit coupled to the output terminal. The control circuit of claim 5, further comprising: an initial circuit coupled to the latch circuit of the control circuit, wherein the initial circuit initializes the latch circuit through an initial signal to cause the output terminal Has a logical value of 0. The control circuit of claim 7, wherein the initial circuit includes a third switch coupled between a reference voltage and the latch circuit, and when the initial signal turns on the third switch, the initial circuit The latch circuit is initialized to have the output endpoint have a logic value of zero. The control circuit of claim 8, wherein the first switch, the second switch, and the third switch are Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). A control method applied to an electronic fuse (E-fuse) system, comprising: selectively operating in a giving mode or a reading mode; and when operating in the giving mode, storing a code, wherein the code And a fuse for indicating whether to connect the electronic fuse system; and reading a state of the fuse of the electronic fuse system when operating in the read mode. The control method of claim 10, wherein when operating in the giving mode, the method further comprises: storing the code; and using a fuse of the electronic fuse system to determine the code according to the code Whether to connect the fuse of the electronic fuse system. The control method of claim 11, further comprising: when operating in the giving mode, using a latch circuit to store the code; when operating in the read mode, using a read circuit to read This state of the fuse. The control method of claim 12, wherein the read circuit comprises a first switch, and when operating in the read mode, the read circuit receives a read signal to turn on the first switch to read This state of the fuse. The control method of claim 13, wherein the latch circuit includes a second switch, and when the control circuit operates in the giving mode, the latch circuit receives a give signal to turn on the second switch to store The code and close the first switch. The control method of claim 12, wherein the latch circuit includes an input unit for receiving the code and a feedback unit coupled to the output terminal. The control method of claim 14, further comprising: initializing the latch circuit by an initial signal by using an initial circuit coupled to the latch circuit. The control method of claim 16, wherein the initial circuit includes a third switch coupled to a reference voltage and the latch circuit, and when the initial signal turns on the third switch, the initial circuit The latch circuit is initialized. The control method of claim 17, wherein the first switch, the second switch, and the third switch are Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs).