TWI594571B - An output stage circuit - Google Patents

Description

Output stage circuit

The present invention relates to an output stage circuit architecture.

At present, in the design of the output stage circuit, in order to achieve high speed and high efficiency, most of the circuit adopts push-pull architecture output. The advantage of this architecture is that the output voltage can reach near rail-to-rail (rail-to). The output of -rail) is therefore efficient and easy to integrate in integrated circuits. With the advancement of semiconductor manufacturing, it has come to the generation of nanometers, so the breakdown voltage that the miniature component can withstand is getting lower and lower. Therefore, the output voltage range will be limited by the process characteristics and become lower and lower. In systems where the output voltage is greater than the component breakdown voltage, it will become increasingly difficult.

An embodiment of the present disclosure provides an output stage circuit including: a power inverter coupled to a signal terminal; and a dynamic bias circuit electrically coupled to a system Between the voltage terminal and the power inverter, the dynamic bias circuit includes at least one Zener diode for maintaining a voltage across the gate and the source of the at least one transistor of the power inverter In a first absolute value range, the voltage between the gate and the drain of the at least one transistor and the voltage between the drain and the source are within a second absolute value range.

An embodiment of the present disclosure provides a signal processing method for an output stage circuit, the method comprising: receiving a first level signal; maintaining a voltage across a gate and a source of the P-type transistor, and maintaining the gate and the gate The voltage across the drain and the voltage across the drain and source maintain the P-type transistor operating in the linear region when turned on; output a system with the highest voltage; receive a second level a signal; maintaining a voltage across the gate and source of the N-type transistor and maintaining a voltage across the gate and the drain, and maintaining a voltage across the drain and the source, the voltage making the N The transistor operates in the linear region when turned on; and outputs a system minimum voltage.

The features and technical advantages of the present invention are set forth in the <RTIgt; Additional features and advantages of the invention will be described hereinafter and form the subject of the claims of the invention. It will be appreciated by those skilled in the art that the conception and the specific embodiments disclosed herein can be readily utilized as a basis for modification or design of other structures or procedures for the same purpose. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.

11‧‧‧ Sensor array

12‧‧‧High-voltage multiplexer

13‧‧‧pulse

14‧‧‧Digital Signal Processor

15‧‧‧A/D converter

16‧‧‧ Adjustable Gain Amplifier

17‧‧‧Low noise amplifier

18‧‧‧Transfer/receive switch

19‧‧‧ nodes

20‧‧‧High voltage signal

21‧‧‧Upper half dynamic bias circuit

22‧‧‧lower half dynamic bias circuit

23‧‧‧Power inverter

24‧‧‧ upper half protection circuit

25‧‧‧lower half protection circuit

26‧‧‧ load

27‧‧‧The first half of the quasi-phase shifter

28‧‧‧Second phase quasi-phase shifter

27-1‧‧‧bit phase shifter and delay circuit

28-1‧‧‧Phase phase shifter and delay circuit

29‧‧‧ nodes

30‧‧‧ nodes

31‧‧‧ nodes

32‧‧‧ diode

33‧‧‧resistance

34‧‧‧Zina diode

35‧‧‧ diode

36‧‧‧resistance

37‧‧‧Zina diode

38‧‧‧resistance

39‧‧‧ Capacitance

41‧‧‧The first half of the quasi-phase shifter

42‧‧‧Zina diode

43‧‧‧resistance

44‧‧‧resistance

45‧‧‧Power inverter

46‧‧‧ load

47‧‧‧ nodes

48‧‧‧ nodes

49‧‧‧ nodes

51‧‧‧Upper half dynamic bias circuit

52‧‧‧Zina diode

53‧‧‧resistance

54‧‧‧Xiaoji diode

61‧‧‧Second-level quasi-phase shifter

62‧‧‧Zina diode

63‧‧‧resistance

64‧‧‧resistance

66‧‧‧Inverter

71‧‧‧lower half dynamic bias circuit

72‧‧‧Zina diode

73‧‧‧resistance

74‧‧‧Xiaoji diode

81‧‧‧The upper half of the protection circuit

91‧‧‧ Lower half protection circuit

92‧‧‧Zina diode

93‧‧‧resistance

94‧‧‧resistance

95‧‧‧resistance

100‧‧‧ Ultrasonic system

101‧‧‧The first half of the quasi-phase shifter

102‧‧‧bit phase shifter and delay circuit

103‧‧‧Second-phase quasi-phase shifter

104‧‧‧bit phase shifter and delay circuit

106‧‧‧ nodes

108‧‧‧ nodes

200‧‧‧Output stage circuit

300‧‧‧Output stage circuit

400‧‧‧Output stage circuit

MP1, MP2, MP4‧‧‧P type transistor

MN1, MN2, MN3‧‧‧N type transistor

VH1‧‧‧ first high end

VH2‧‧‧ second high end

VL1‧‧‧ first low end

VL2‧‧‧ second low end

IN_P, IN_N‧‧‧ signal input

Q1, Q2, Q6, Q7, Q10, Q11‧‧‧P type transistors

Q3, Q4, Q5, Q8, Q9‧‧‧N type transistors

R1~R7‧‧‧P type transistor

VC‧‧‧ fixed power supply

VDD‧‧‧ voltage terminal

S1~S7‧‧‧N type transistor

VSS‧‧‧voltage end

The aspects of the disclosure of the present application are best understood from the following detailed description and the accompanying drawings. Note that various features are not drawn to scale in accordance with standard implementations of the industry. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1 is a diagram showing a device representation of an ultrasonic system in accordance with some embodiments.

2 is a device representation of an output stage circuit in accordance with some embodiments.

3 is a diagram of a device representation of an output stage circuit in accordance with some embodiments.

4 is a diagram of a device representation of an output stage circuit in accordance with some embodiments.

The drawings of the present disclosure have been generally described above, so that a detailed description of the present disclosure will be better understood. Other technical features and advantages of the subject matter of the claims of the present disclosure will be described below. It is to be understood by those of ordinary skill in the art that the present invention disclosed herein may be It is also to be understood by those of ordinary skill in the art that this invention is not limited to the spirit and scope of the disclosure disclosed in the appended claims.

The following disclosure provides many different embodiments or examples for implementing different features of the present application. Specific examples of components and configurations are described below to simplify the disclosure of the present application. Of course, these are merely examples and are not intended to limit the application. For example, the following description forming the first feature on or over the second feature can include forming the first and second contacts in direct contact Embodiments of the features may also include embodiments in which other features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, the application may repeat the component symbols and/or letters in different examples. This repetition is for the purpose of simplicity and clarity, and is not intended to govern the relationship between the various embodiments and/or the structures discussed.

Furthermore, the present application may use spatially corresponding words, such as "lower", "lower", "lower", "higher", "higher" and the like, to describe one of the patterns. The relationship of an element or feature to another element or feature. Spatially corresponding words are used to include different orientations of the device in use or operation in addition to the orientations depicted in the drawings. The device may be positioned (rotated 90 degrees or other orientations) and the spatially corresponding description used in this application may be interpreted accordingly.

Embodiments of the present disclosure disclose an output stage circuit in which the output voltage is not limited to the component breakdown voltage. In the integrated circuit, the advanced process allows the semiconductor component to continue to be miniaturized, and the shorter the semiconductor component channel, the faster the switching speed, but the result of the miniaturization makes the micro-semiconductor component itself less able to withstand high voltage and high current operation at the same time. For example, in the field of ultrasonic circuits, the output requires a high-voltage pulse generator to drive the probe. If you want to use the integrated circuit process to achieve high voltage output, the output stage circuit needs special design to overcome the individual. The low breakdown voltage of the component. In general, the output stage circuit of a high voltage pulse generator is limited by the breakdown voltage of the component. For example, a 60V component can only output an output voltage of 0~60V or ±30V for the output stage. The present invention provides an output stage circuit in which the output voltage is not limited to the breakdown voltage of the component, and the output voltage of the large swing can be designed with a low voltage semiconductor component.

1 is a diagram showing a device representation of an ultrasonic system 100 in accordance with some embodiments. The ultrasonic system 100 includes a sensor array 11, a high voltage multiplexer 12, a pulser 13, a digital signal processor 14, an A/D converter 15, a variable gain amplifier 16, a low noise amplifier 17, and a transmission/reception switch 18. Wait. The sensor array 11 is electrically connected to the high voltage multiplexer 12, the high voltage multiplexer 12, the output end of the pulser 13, the transmission/reception switch 18 is connected to the node 19, and the transmission/reception switch 18 is connected to the low noise amplifier 17, low noise. Amplifier 17 is connected to adjustable gain amplification The adjustable gain amplifier 16 is connected to the A/D converter 15. The low noise amplifier 17 is located between the transmit/receive switch 18 and the variable gain amplifier 16. The variable gain amplifier 16 is located in the A/D converter. Between 15 and the low noise amplifier 17, the A/D converter 15 is located between the variable gain amplifier 16 and the digital signal processor 14, and the digital signal processor 14 is connected to the pulser 13 and the A/D converter 15.

The digital signal processor 14 is capable of processing the signal calculation of the entire ultrasonic system 100. The digital signal processor 14 commands the pulser 13 to emit a high voltage signal 20, and the channel of the transmission/reception switch 18 controls the high voltage signal 20 to pass through the node. 19 and transmitted to the high voltage multiplexer 12, the high voltage multiplexer 12 controls the switching of the plurality of signal channels through the switching control of the selection line, and the signal is further transmitted to the sensor array 11, and the sensor array 11 (transducer array) can carry the electrons The signal is converted to sound waves or other physical signals such as light or heat, and the sound waves are emitted onto the object being sensed, such as a person or an animal. The sensed object receives the sound wave to generate reflected sound waves or other physical information, and the sensor array 11 can sense the measured information and can convert the sensed information into a low voltage signal. The low voltage signal with physiological information is transmitted through the channel of the high voltage multiplexer 12, and the low voltage signal is transmitted to the node 19, and the low voltage signal is transmitted to the low noise amplifier 17 through the transmission/reception switch 18, and the low noise amplifier 17 will be low voltage. The signal is amplified to facilitate signal processing in the next stage, and the low voltage signal is further processed by the variable gain amplifier 16 and the A/D converter 15. The digital signal processor 14 receives the low voltage signal with physiological information and interprets it. The variable gain amplifier 16 can adjust the gain of the signal to match the upper and lower circuits. The A/D converter 15 is capable of converting an analog signal into a digital signal.

This case focuses on the output stage circuit in the pulser 13. The purpose is to use the integrated circuit process and low voltage resistant components to achieve high voltage, high swing output, as detailed below.

2 is a device representation of an output stage circuit 200 in accordance with some embodiments. The output stage circuit 200 includes an upper half dynamic bias circuit 21, a lower half dynamic bias circuit 22, a power inverter 23, an upper half protection circuit 24, a lower half protection circuit 25, a load 26, and a top half. Part quasi-phase shifter 27, lower half quasi-phase shifter 28, first high voltage end VH1, second high The voltage terminal VH2, the first low voltage terminal VL1, the second low voltage terminal VL2, the level shifter and the delay circuit 27-1, the level shifter and the delay circuit 28-1.

The power inverter 23 includes P-type transistors MP1, MP2 and N-type transistors MN1, MN2. The P-type transistors MP1, MP2 and the N-type transistors MN1, MN2 are gold-oxygen half field effect power elements. The gate of the P-type transistor MP1 is connected to the quasi-phase shifter 27 of the upper half; the source of the P-type transistor MP1 is connected to the first high-voltage terminal VH1; the drain of the P-type transistor MP1 is connected to the source of the P-type transistor MP2 . The gate and source of the P-type transistor MP2 are connected to the upper half of the dynamic bias circuit 21; the drain of the P-type transistor MP2 is connected to the drain of the N-type transistor MN1. The gate and source of the N-type transistor MN1 are connected to the lower half of the dynamic bias circuit 22, and the source of the N-type transistor MN1 is simultaneously connected to the drain of the N-type transistor MN2. The gate of the N-type transistor MN2 is connected to the quasi-phase shifter 28 of the lower half, and the source of the N-type transistor MN2 is connected to the first low-voltage end VL1. In particular, the node 29 is located between the P-type transistors MP1 and MP2, and the node 29 is connected to the drain of the P-type transistor MP1, the source of the P-type transistor MP2, and the end of the upper half of the dynamic bias circuit 21. One end of the upper half protection circuit 24. The node 30 is located between the P-type transistor MP2 and the N-type transistor MN1, and the node 30 is connected to the drain of the P-type transistor MP2, the drain of the N-type transistor MN1, and one end of the load 26. The node 31 is located between the N-type transistors MN1 and MN2. The node 31 is connected to the source of the N-type transistor MN1, the drain of the N-type transistor MN2, and the lower half of the lower half of the dynamic bias circuit 22. One end of the protection circuit 25.

The upper half quasi-phase shifter 27 is connected to the first high voltage terminal VH1, the second high voltage terminal VH2, the signal input terminal IN_P, and the gate of the P type transistor MP1. The second half quasi-phase shifter 28 is connected to the gates of the first low voltage terminal VL1, the second low voltage terminal VL2, the signal input terminal IN_N, and the N type transistor MN2, respectively. The first half of the quasi-phase shifter 27 can include, for example, a circuit composed of a plurality of transistors, which can boost the signal of the signal input terminal IN_P and output a larger absolute value voltage, for example, the first high voltage terminal VH1 and the second high voltage terminal VH2. The voltage of the second half of the quasi-phase shifter 28 can include, for example, a circuit composed of a plurality of transistors, which can step down the signal of the signal input terminal IN_N and output The larger absolute voltage is, for example, the voltage of the first low voltage terminal VL1 and the second low voltage terminal VL2.

The upper half dynamic bias circuit 21 includes a diode 32, a resistor 33, and a Zener diode 34. The diode 32 is connected between the second high voltage terminal VH2 and the gate of the P-type transistor MP2, the anode of the diode 32 is connected to the gate of the P-type transistor MP2, and the cathode of the diode 32 is connected to the second high voltage terminal. VH2. The Zener diode 34 is connected between the node 29 and the gate of the P-type transistor MP2, in other words, the Zener diode 34 is connected between the source and the gate of the P-type transistor MP2. In detail, the anode of the Zener diode 34 is connected to the gate of the P-type transistor MP2, and the cathode of the Zener diode 34 is connected to the source of the P-type transistor MP2. The resistor 33 is connected in parallel with the Zener diode 34, one end of the resistor 33 is connected to the source of the P-type transistor MP2, and the other end of the resistor 33 is connected to the gate of the P-type transistor MP2.

The lower half dynamic bias circuit 22 includes a diode 35, a resistor 36, and a Zener diode 37. The diode 35 is connected between the second low voltage terminal VL2 and the gate of the N-type transistor MN1, the cathode of the diode 35 is connected to the gate of the N-type transistor MN1, and the anode of the diode 35 is connected to the second low-voltage terminal. VL2. The Zener diode 37 is connected between the node 31 and the gate of the N-type transistor MN1. In other words, the Zener diode 37 is connected between the source and the gate of the N-type transistor MN1. In detail, the anode of the Zener diode 37 is connected to the source of the N-type transistor MN1, and the cathode of the Zener diode 37 is connected to the gate of the N-type transistor MN1. The resistor 36 is connected in parallel with the Zener diode 37, one end of the resistor 36 is connected to the source of the N-type transistor MN1, and the other end of the resistor 36 is connected to the gate of the N-type transistor MN1.

The upper half protection circuit 24 includes an N-type transistor MN3, the gate of the N-type transistor MN3 is connected to the level shifter and the delay circuit 27-1, and indirectly receives the signal from the signal input terminal IN_P; the N-type transistor MN3 The drain connection node 29; the source of the N-type transistor MN3 is grounded.

The lower half protection circuit 25 includes a P-type transistor MP4, the gate of the P-type transistor MP4 is connected to the level shifter and the delay circuit 28-1, and indirectly receives the signal from the signal input terminal IN_N; the P-type transistor MP4 Datum connection node 31; source of P-type transistor MP4 Ground.

In this embodiment, the load 26 includes a resistor 38 and a capacitor 39. The load 26 is a sensor or other external device, and is not limited to the embodiment.

In this embodiment, the manner of operation may be slightly divided into a positive half-wave mode in which the upper half of the transistor is turned on and a negative half-wave mode in which the lower half of the transistor is turned on. In the positive half-wave mode, the P-type transistors MP1, MP2 are turned on: the N-type transistors MN1, MN2 are turned off. The output voltage of the first high voltage terminal VH1 is greater than the second high voltage terminal VH2, for example: VH1=60V; VH2=55V. The first half of the quasi-phase shifter 27 receives the signal input terminal IN_P signal and outputs the second high voltage terminal VH2 to the P-type transistor MP1, so that the P-type transistor MP1 is turned on, the voltage of the node 29 is VH1-V _SD , and the V _SD is P. Source-drain across the transistor MP1. The second high voltage terminal VH2 is at a lower voltage, so the Zener diode 34 exhibits a reverse bias conduction, the anode voltage of the Zener diode 34 is (VH1-V _SD -V _ZENER ), and the V _ZENER is a Zener diode. The cross pressure of the body 34. Further, the second high voltage terminal VH2 is pushed back, and the diode 32 is turned on. Therefore, the voltage of the anode of the Zener diode 34 is VH2+V _DIODE , which satisfies the equation of (VH2+V _DIODE )=(VH1-V _SD -V _ZENER ). . Since the Zener diode 34 and the resistor 33 appear in parallel, the voltage across the resistor 33 is equal to V _ZENER . In particular, a parallel Zener diode 34 and a resistor 33 are connected across the source-gate of the P-type transistor MP2 to maintain a voltage across the gate and source of the P-type transistor MP2. In the absolute value range, the absolute value range is within the voltage working range of the Zener diode 34 reverse bias, so the absolute value range is the reverse bias voltage to 0V, which is a dynamic cross-pressure, so that a dynamic Bias is applied to the P-type transistor MP2 gate. Moreover, the voltage across the gate-source of the P-type transistor MP2 is equal to the voltage across the Zener diode 34, and is limited by the voltage of the Zener diode 34, so that the P-type transistor MP2 operates in the linear region when it is turned on. (Triode area), while avoiding P-type transistor MP2 working in the collapse zone. At this time, the P-type transistor MP2 is turned on and operates in the linear region, and the voltage of the node 30 is VH1-2V _SD , which is only slightly smaller than the voltage of the first high-voltage terminal VH1, and the load 26 receives the voltage VH1-2V _SD . In addition, the upper half protection circuit 24 assumes a closed state; the lower half protection circuit 25 assumes an open state, so that the node 31 is grounded to prevent the lower half element N-type transistors MN1, MN2 from being subjected to an overvoltage; for the N-type transistor MN1 The node 31 is grounded to ensure that the voltage between the drain and the source of the N-type transistor MN1 is within an absolute value range. In addition, the node 31 is biased by the Zener diode 37 to make the N-type transistor MN1 The gate quickly returns to -V _DIODE to maintain the cross-voltage between the gate and the drain of the N-type transistor MN1 within an absolute value; for the N-type transistor MN2, the node 31 is grounded to ensure The voltage across the drain and source of the N-type transistor MN2, and the voltage across the gate and the drain are within an absolute value range.

In the negative half-wave mode, the P-type transistors MP1, MP2 are turned off; the N-type transistors MN1, MN2 are turned on. The absolute value of the output voltage of the first low voltage terminal VL1 is greater than the absolute value of the voltage of the second low voltage terminal VL2, and both are negative voltages, for example: VL1=-60V; VL2=-55V; thus |VL1|>|VL2|. The second half quasi-phase shifter 28 receives the input terminal IN_N signal and outputs the second low voltage terminal VL2 to the N-type transistor MN2, so that the N-type transistor MN2 is turned on, the voltage of the node 31 is VL1+V _DS , and the V _DS is N-type. The 汲-source cross-voltage of transistor MN2. The node 31 and the second low voltage terminal VL2 are all negative values, and the second low voltage terminal VL2 is higher pressure, and the voltage of the node 31 is equal to the anode voltage of the Zener diode 37, so the Zener diode 37 is inverted. The partial conduction, the voltage of the cathode of the Zener diode 37 is VL1+V _DS +V _ZENER , and V _ZENER is the voltage across the Zener diode 37. Pushing back from the second low voltage terminal VL2, the diode 35 is turned on, so the voltage of the cathode of the Zener diode 37 is VL2-V _DIODE , which satisfies the equation of (VL2-V _DIODE )=(VL1+V _DS +V _ZENER ) . Since the Zener diode 37 and the resistor 36 are in parallel, the voltage across the resistor 36 is equal to V _ZENER . In particular, a parallel Zener diode 37 and a resistor 36 are connected across the source-gate of the N-type transistor MN1 to maintain a voltage across the gate and source of the N-type transistor MN1. In the absolute value range, the absolute value range is within the voltage working range of the Zener diode 37 reverse bias, so the absolute value range is the reverse bias voltage to 0V, which is a dynamic cross-pressure, so that a dynamic The bias is applied to the gate of the N-type transistor MN1. Moreover, the voltage across the gate-source of the N-type transistor MN1 is equal to the voltage across the Zener diode 37, and the voltage limitation of the Zener diode 37 causes the N-type transistor MN1 to operate in the linear region when turned on. (three-pole area), while avoiding the N-type transistor MN1 working collapse zone. Therefore, at this time, the N-type transistor MN1 is turned on and operates in the linear region, and the voltage of the node 30 is VL1+2V _DS , the voltage is a negative value, and is only slightly higher than the voltage of the first low-voltage terminal VL1, and the load 26 receives the voltage. VL1+2V _DS . In addition, the upper half protection circuit 24 is turned on; the lower half protection circuit 25 is turned off, so that the node 29 is grounded; the upper half element P-type transistors MP1, MP2 are prevented from being overvoltaged; for the P-type transistor MP2, The node 29 is grounded to ensure that the voltage between the drain and the source of the P-type transistor MP2 is within an absolute value range. In addition, the node 29 is biased by the Zener diode 34 to make the P-type transistor MP2 The gate quickly returns to +V _DIODE to maintain the cross-voltage between the gate and the drain of the P-type transistor MP2 in an absolute value range; for the P-type transistor MP1, the node 29 is grounded to ensure P The voltage between the drain and the source of the transistor MP1 and the voltage across the gate and the drain are within an absolute value range. The Zener diode 34 and the resistor 33 limit the voltage across the gate-source of the P-type transistor MP2, which is within an absolute value range, such as V _SG |5V|, P-type transistor MP2 gate - the voltage across the drain is within an absolute value, such as V _GD |60V|, P-type transistor MP2 source - the voltage across the drain is within an absolute value, such as V _SD |60V|, the voltage across the gate-drain and the voltage across the source-drain are in the same absolute range; Zener diode 37 and resistor 36 limit the gate-source of the N-type transistor MN1 The voltage across the gate, the voltage across the gate and the drain, and the voltage across the source and the drain are each within an absolute value to ensure that the P-type transistor MP2 and the N-type transistor MN1 operate when they are turned on. The linear region makes the output swing of the node 30 reach VH1-2V _SD ~ VL1 + 2V _DS , which is close to the highest voltage and the lowest voltage difference of the system. Therefore, the high voltage output swing can be achieved by the power component with low voltage resistance. High voltage load devices are used, such as ultrasonic sensors or logic inverters.

FIG. 3 illustrates a device representation of output stage circuit 300 in accordance with some embodiments. The output stage circuit 300 includes an upper half dynamic bias circuit 51, a lower half dynamic bias circuit 71, a power inverter 45, an upper half protection circuit 81, a lower half protection circuit 91, a load 46, and a top half. The position quasi-phase shifter 41, the lower half quasi-phase shifter 61, the first high voltage end VH1, the second high voltage end VH2, the first low pressure end VL1, and the second low pressure end VL2.

The power inverter 45 includes P-type transistors Q1 and Q2 and N-type transistors Q3 and Q4. P-type transistors Q1, Q2 and N-type transistors Q3, Q4 are gold-oxygen half-field effects Rate element or channel enhancement MOSFET, or other element suitable for this embodiment. The gate of the P-type transistor Q1 is connected to the quasi-phase shifter 41 of the upper half; the source of the P-type transistor Q1 is connected to the first high-voltage terminal VH1; the drain of the P-type transistor Q1 is connected to the source of the P-type transistor Q2. . The gate and the source of the P-type transistor Q2 are respectively connected to the upper half of the dynamic bias circuit 51; the drain of the P-type transistor Q2 is connected to the drain of the N-type transistor Q3. The gate and the source of the N-type transistor Q3 are respectively connected to the lower half of the dynamic bias circuit 71, and the source of the N-type transistor Q3 is simultaneously connected to the drain of the N-type transistor Q4. The gate and the source of the N-type transistor Q4 are respectively connected to the lower half quasi-phase shifter 61, and the source of the N-type transistor Q4 is connected to the first low-voltage end VL1. In particular, the node 47 is located between the P-type transistors Q1 and Q2, and the node 47 is connected to the drain of the P-type transistor Q1, the source of the P-type transistor Q2, and the end of the upper half of the dynamic bias circuit 51. One end of the upper half protection circuit 81. The node 48 is located between the P-type transistor Q2 and the N-type transistor Q3, and the node 48 is connected to the drain of the P-type transistor Q2, the drain of the N-type transistor Q3, and one end of the load 46. The node 49 is located between the N-type transistors Q3 and Q4, and the node 49 is connected to the source of the N-type transistor Q3, the drain of the N-type transistor Q4, the one end of the lower half of the dynamic bias circuit 71, and the lower half. One end of the protection circuit 91.

In the present embodiment, the upper half quasi-phase shifter 41 includes a plurality of Zener diodes 42, resistors 43, 44, and an N-type transistor Q5. A plurality of Zener diodes 42 are connected in parallel with the resistors 43. The anodes of the Zener diodes 42 are simultaneously connected to the gate of the P-type transistor Q1 and the drain of the N-type transistor Q5; each Zener diode 42 The cathode is connected to the first high voltage terminal VH1. The gate of the N-type transistor Q5 is connected to the input signal input terminal IN_P, and the other end of the IN_P is grounded; the source of the N-type transistor Q5 is connected to the resistor 44, and one end of the resistor 44 is grounded.

The second half quasi-phase shifter 61 includes a plurality of Zener diodes 62, a resistor 63, a P-type transistor Q6, a resistor 64, a constant power source VC, and an inverter 66. A plurality of Zener diodes 62 and a resistor 63 are connected in parallel, and an anode of each Zener diode 62 is connected to a source of the N-type transistor Q4; a cathode of each Zener diode 62 is simultaneously connected to the N-type transistor Q4. The gate of the gate and P-type transistor Q6. One end of the inverter 66 is connected to the fixed power source VC, and one end is grounded. Gate of P-type transistor Q6 The input terminal of the pole connection inverter 66, the input signal terminal IN_N is connected to the input end of the inverter 66; the source of the P-type transistor Q6 is connected to the resistor 64, the other end of the resistor 64 is connected to the fixed power source VC, and the fixed power source VC is driven. The voltage of the P-type transistor Q6 is, for example, 5V. Therefore, it is much smaller than the first high voltage end VH1 or the second high voltage end VH2.

The upper half dynamic bias circuit 51 includes three Zener diodes 52, a resistor 53, a Schottky diode 54 and a second high voltage terminal VH2. The Schottky diode 54 is connected between the second high voltage terminal VH2 and the gate of the P-type transistor Q2, and the anode of the Schottky diode 54 is connected to the gate of the P-type transistor Q2; the Xiaoji diode 54 The cathode is connected to the second high voltage terminal VH2. The three Zener diodes 52 are connected in parallel, and each Zener diode 52 is connected between the node 47 and the gate of the P-type transistor Q2, in other words, each Zener diode The body 52 is connected between the source and the gate of the P-type transistor Q2. In detail, the anode of each Zener diode 52 is connected to the gate of the P-type transistor Q2, and the cathode of each Zener diode 52 is connected to the source of the P-type transistor Q2. The resistor 53 is connected in parallel with each of the Zener diodes 52. One end of the resistor 53 is connected to the source of the P-type transistor Q2, and the other end of the resistor 53 is connected to the gate of the P-type transistor Q2.

The lower half dynamic bias circuit 71 includes three Zener diodes 72, a resistor 73, a Schottky diode 74, and a second low voltage terminal VL2. The Schottky diode 74 is connected between the second low voltage terminal VL2 and the gate of the N-type transistor Q3, and the cathode of the Schottky diode 74 is connected to the gate of the N-type transistor Q3, and the Schottky diode 74 The anode is connected to the second low pressure end VL2. Each Zener diode 72 is connected between the node 49 and the gate of the N-type transistor Q3. In other words, each Zener diode 72 is connected between the source and the gate of the N-type transistor Q3. In detail, the anode of each Zener diode 72 is connected to the source of the N-type transistor Q3, and the cathode of each Zener diode 72 is connected to the gate of the N-type transistor Q3. The resistor 73 is connected in parallel with each of the Zener diodes 72. One end of the resistor 73 is connected to the source of the N-type transistor Q3, and the other end of the resistor 73 is connected to the gate of the N-type transistor Q3.

The upper half protection circuit 81 includes a P-type transistor Q7, an N-type transistor Q8, an N-type transistor Q9, and a constant power source VC. The P-type transistor Q7 and the N-type transistor Q8 are complementary pairs, and the gates of the P-type transistor Q7 and the N-type transistor Q8 are connected, and are connected to the signal input terminal. IN_P, the drain of P-type transistor Q7 is connected to the drain of N-type transistor Q8, the source of P-type transistor Q7 is connected to constant power supply VC, and the source of N-type transistor Q8 is grounded. The output terminals of the complementary P-type transistor Q7 and the N-type transistor Q8 are connected to the gate of the N-type transistor Q9. In other words, the gate of the N-type transistor Q9 is simultaneously connected to the drain of the P-type transistor Q7, N-type. The drain of the transistor Q8. The source of the N-type transistor Q9 is grounded, and the drain of the N-type transistor Q9 is connected to the node 47.

The lower half protection circuit 91 includes a P-type transistor Q10, a Zener diode 92, resistors 93, 94, 95, a P-type transistor Q11, and a constant power source VC. The gate of the P-type transistor Q10 is connected to the signal input terminal IN_N, and the drain of the P-type transistor Q10 is connected to the resistor 94, the cathode of the Zener diode 92, and the gate of the P-type transistor Q11. The resistor 94 and the Zener diode 92 are connected in parallel, the anode of the Zener diode 92 is connected to the constant power source VC, and the cathode of the Zener diode 92 is connected to the gate of the P-type transistor Q11. The drain of the P-type transistor Q11 is connected to the node 49, the source of the P-type transistor Q11 is connected to the resistor 95, and the other end of the resistor 95 is grounded. In the present embodiment, the load 46 represents a sensor or other external device, and is not limited to the embodiment.

In particular, in the positive half-wave mode operation, a parallel Zener diode 52 and a resistor 53 are connected across the source-gate of the P-type transistor Q2 to maintain the gate of the P-type transistor Q2. The cross-voltage between the source and the source is within an absolute value range, and the absolute value range is within the voltage operating range of the Zener diode 52 reverse bias, so the absolute value range is the reverse bias voltage to 0V, which is A dynamic crossover voltage causes a dynamic bias to be generated to the gate of the P-type transistor Q2. Moreover, the voltage across the gate-source of the P-type transistor Q2 is equal to the voltage across the Zener diode 52, and the voltage of the Zener diode 52 is limited, so that the P-type transistor Q2 operates in the linear region when it is turned on. (Triode area), while avoiding P-type transistor Q2 working in the collapse zone. Therefore, at this time, the P-type transistor Q2 is turned on and operates in the linear region (three-pole region), and the node 48 can output a voltage close to the first high-voltage terminal VH1. In addition, the upper half protection circuit 81 is turned off; the lower half protection circuit 91 is turned on, causing the node 49 to be grounded; and the lower half element N-type transistors Q3, Q4 are prevented from being overvoltaged.

In particular, in the negative half-wave mode operation, the parallel Zener diode 72 and the resistor 73 are connected across the gate-source of the N-type transistor Q3 to maintain the N-type transistor Q3. The voltage across the gate and the source is within an absolute value range, and the absolute value range is within the voltage operating range of the Zener diode 72 reverse bias, so the absolute value range is between the reverse bias voltage and 0V. It is a dynamic voltage across the voltage so that a dynamic bias is generated to the gate of the N-type transistor Q3. Moreover, the voltage across the gate-source of the N-type transistor Q3 is equal to the voltage across the Zener diode 72, and the voltage limitation of the Zener diode 72 causes the N-type transistor Q3 to operate in the linear region when it is turned on. (three-pole area), while avoiding the N-type transistor Q3 working in the collapse zone. Therefore, at this time, the N-type transistor Q3 is turned on and operates in the linear region, and the node 48 can output a voltage close to the first low-voltage terminal VL1. In addition, the upper half protection circuit 81 is turned on; the lower half protection circuit 91 is turned off, causing the node 47 to be grounded; and the upper half element P-type transistors Q1, Q2 are prevented from being subjected to an overvoltage.

The Zener diode 52 and the resistor 53 limit the voltage across the gate-source of the P-type transistor Q2; the Zener diode 72 and the resistor 73 limit the gate-source cross between the N-type transistor Q3 Pressing to ensure that the P-type transistor Q2 and the N-type transistor Q3 are turned on when operating in the linear region, so that the output swing of the node 48 reaches VH1~VL1, which is close to the highest pressure and the lowest pressure difference of the system, so the embodiment can Low-voltage power components achieve high-voltage output swings for use in high-voltage load devices such as ultrasonic sensors.

4 is a diagram of a device representation of an output stage circuit 400 in accordance with some embodiments. The output stage circuit 400 includes an upper half quasi-phase shifter 101, a level shifter and delay circuit 102, a lower half quasi-phase shifter 103, a level shifter and delay circuit 104, and a P-type transistor R1 R7. , N-type transistors S1 ~ S7. The signal input terminal IN_P is connected to the upper half quasi-phase shifter 101, the level shifter and the delay circuit 102; the signal input terminal IN_N is connected to the lower half quasi-phase shifter 103, the level shifter and the delay circuit 104. The upper half of the output stage circuit 400 has a P-type transistor and an N-type transistor as a complementary pair, such as a P-type transistor R1 and an N-type transistor S1. The source of the P-type transistor R1 is connected to the drain of the N-type transistor S1, the gate of the P-type transistor R1 is connected to the signal from the quasi-phase shifter 101 of the upper half, and the gate connection of the N-type transistor S1 is from The signal of the level shifter and delay circuit 102. The other complementary pair is a P-type transistor R5 and an N-type transistor S5, and the P-type transistor R5 is simultaneously connected to the source and the N of the P-type transistor R1. The drain of the transistor S1, the source of the P-type transistor R5 is connected to the drain of the N-type transistor S5, the source of the N-type transistor S5 is connected to the voltage terminal VDD, and the gate connection of the P-type transistor R5 is from the upper half. The signal of the quasi-phase shifter 101 is connected, and the gate of the N-type transistor S5 is connected to the signal from the level shifter and the delay circuit 102. The other complementary pair is a P-type transistor R6 and an N-type transistor S6. The P-type transistor R6 is also connected to the source of the P-type transistor R5 and the drain of the N-type transistor S5, and the P-type transistor R6. The source is connected to the drain of the N-type transistor S6, the source of the N-type transistor S6 is connected to the voltage terminal 2VDD, and the gate of the P-type transistor R6 is connected to the signal from the quasi-phase shifter 101 of the upper half, the N-type transistor The gate of S6 connects the signals from the level shifter and delay circuit 102. The P-type transistor R7 is simultaneously connected to the source of the P-type transistor R6 and the drain of the N-type transistor S6, and the source of the P-type transistor R7 is connected to the voltage terminal 3VDD.

The lower half of the output stage circuit 400 has a P-type transistor and an N-type transistor as a complementary pair, such as an N-type transistor S2 and a P-type transistor R2. The source of the N-type transistor S2 is connected to the drain of the P-type transistor R2, the gate of the N-type transistor S2 is connected to the signal from the quasi-phase shifter 103 of the lower half, and the gate connection of the P-type transistor R2 is derived from The signal of the level shifter and delay circuit 104. The other complementary pair is an N-type transistor S3 and a P-type transistor R3. The N-type transistor S3 is simultaneously connected to the source of the N-type transistor S2 and the drain of the P-type transistor R2, and the N-type transistor S3 The source is connected to the drain of the P-type transistor R3, the source of the P-type transistor R3 is connected to the voltage terminal VSS, and the gate of the N-type transistor S3 is connected to the signal from the quasi-phase shifter 103 of the lower half, the P-type transistor R3 The gate connects the signal from the level shifter and delay circuit 104. The other complementary pair is an N-type transistor S4 and a P-type transistor R4. The N-type transistor S4 is simultaneously connected to the source of the N-type transistor S3 and the drain of the P-type transistor R3, and the N-type transistor S4 The source is connected to the drain of the P-type transistor R4, the source of the P-type transistor R4 is connected to the voltage terminal 2VSS, and the gate of the N-type transistor S4 is connected to the signal from the quasi-phase shifter 103 of the lower half, the P-type transistor The gate of R4 connects the signals from the level shifter and delay circuit 104. The N-type transistor S7 is simultaneously connected to the source of the N-type transistor S4 and the drain of the P-type transistor R4, and the source of the N-type transistor S7 is connected to the voltage terminal 3VSS.

The node 106 is located between the P-type transistor R1 and the N-type transistor S2, and the node 106 is simultaneously connected to the drain of the P-type transistor R1 and the drain of the N-type transistor S2; the node 108 is located in the N-type transistor S1 and P-type Between the transistors R2, the node 108 simultaneously connects the source of the N-type transistor S1 and the source of the P-type transistor R2. In this embodiment, the complementary pairs are overlapped with each other. As the number of complementary pairs increases, for example, the number of complementary pairs in the upper half is m, the voltage terminal is connected to mVDD; the number of complementary pairs in the lower half is n, and the voltage terminal is connected to nVSS. In short, the complementary pairs are overlapped with each other, so that the swing of the output is increased to reach the swing of mVDD~nVSS. Therefore, the embodiment can achieve a high-voltage output swing with a low-voltage-resistant power component, thereby achieving an effect of multiplying the output voltage. It is supplied to high voltage load devices.

In summary, this case provides an output stage circuit architecture for various analog (integral/discrete) circuits or digital (integral/discrete) circuits. The Zener diode is used to limit the operation of the transistor in the linear region, so that the output stage circuit can be achieved without being limited to the breakdown voltage of the component, to achieve a high voltage output swing with a low voltage resistant power component, or by a power process of a miniature process. The effect of the output voltage multiplication. This architecture can be applied to medical imaging systems that require high-voltage emission components, such as ultrasound scanners, computer tomography, magnetic resonance imaging or engineering systems such as engineering ultrasonic detection, communication integrated circuit transmitters, high-quality sound systems. Amplifiers, etc.

In one embodiment, the at least one Zener diode of the output stage circuit is connected between the gate of the at least one transistor and the source, and the anode of the at least one Zener diode is connected to the gate. A cathode of the at least one Zener diode is connected to the source.

In one embodiment, the at least one Zener diode of the output stage circuit is connected between the gate of the at least one transistor and the source, and the anode of the at least one Zener diode is connected to the source. A cathode of the at least one Zener diode is coupled to the gate.

In an embodiment, the dynamic bias circuit of the output stage circuit further includes: at least one resistor connected in parallel with the at least one Zener diode.

In an embodiment, the dynamic bias circuit of the output stage circuit includes: at least one diode is located between the voltage terminal of the system and the gate, and an anode of the at least one diode is connected to the gate The cathode of the at least one diode is connected to the voltage terminal of the system.

In an embodiment, the dynamic bias circuit of the output stage circuit includes: at least one diode is located between the voltage terminal of the system and the gate, and an anode of the at least one diode is connected to the voltage end of the system, A cathode of at least one diode is connected to the gate.

In one embodiment, the power inverter of the output stage circuit includes at least two pairs of stacked complementary MOS field effect transistors.

In an embodiment, the output stage circuit of the output stage circuit further includes: a protection circuit coupled to the power inverter for guiding an instantaneous overvoltage, the protection circuit comprising at least one transistor, the at least one transistor The gate is coupled to the signal terminal, the source of the at least one transistor is grounded, and the drain of the at least one transistor of the protection circuit is connected to the source of the at least one transistor of the power inverter.

In an embodiment, the output stage circuit of the output stage circuit further includes: a protection circuit coupled to the power inverter for guiding an instantaneous overvoltage, the protection circuit comprising at least one transistor, the at least one transistor The gate is coupled to the signal terminal, the source of the at least one transistor is grounded, and the drain of the at least one transistor of the protection circuit is connected to the source of the at least one transistor of the power inverter.

In an embodiment, the output stage circuit of the output stage circuit includes: at least one quasi-phase shifter, wherein the input end of the at least one quasi-phase shifter is respectively connected to the signal end and the system voltage end, the at least one bit The output of the quasi-phase shifter is connected to one of the gates of the power inverter.

In an embodiment, the voltage terminal of the system of the output stage circuit includes: a first high voltage end electrically connected to one source of the power inverter; and a second high voltage end configured to The output voltage of a high voltage terminal is greater than the output voltage of the second high voltage terminal, and the output voltages of the first and second high voltage terminals are positive values; and the first low voltage terminal is electrically connected to the first low voltage terminal. And a second low voltage end, the output voltage of the first low voltage end is configured to be smaller than the output voltage of the second low voltage end, and the output voltages of the first and second low voltage ends are negative.

In an embodiment, the signal processing method includes: closing a protection circuit coupled to the P-type transistor according to the first level signal, opening a protection circuit coupled to the N-type transistor; and according to the second level The signal is turned off to close the protection circuit coupled to the N-type transistor, and the protection circuit coupled to the P-type transistor is turned on.

The foregoing is a summary of the features of the embodiments, and those skilled in the art can understand the various aspects of the disclosure. Those skilled in the art will appreciate that the disclosure of the present application can be readily utilized as a basis for designing or modifying other processes and structures to achieve the same objectives and/or the same advantages as the embodiments described herein. It should be understood by those skilled in the art that the present invention is not limited by the spirit and scope of the present disclosure, and that various changes, substitutions and substitutions can be made by those skilled in the art without departing from the spirit of the disclosure. range.

21‧‧‧Upper half dynamic bias circuit

22‧‧‧lower half dynamic bias circuit

23‧‧‧Power inverter

24‧‧‧ upper half protection circuit

25‧‧‧lower half protection circuit

26‧‧‧ load

27‧‧‧The first half of the quasi-phase shifter

28‧‧‧Second phase quasi-phase shifter

29‧‧‧ nodes

30‧‧‧ nodes

31‧‧‧ nodes

32‧‧‧ diode

33‧‧‧resistance

34‧‧‧Zina diode

35‧‧‧ diode

36‧‧‧resistance

37‧‧‧Zina diode

38‧‧‧resistance

39‧‧‧ Capacitance

MP1, MP2‧‧‧P type transistor

VH1‧‧‧ first high end

VH2‧‧‧ second high end

VL1‧‧‧ first low end

VL2‧‧‧ second low end

MN1, MN2, MN3, MP4‧‧‧P type transistor

27-1‧‧‧bit phase shifter and delay circuit

28-1‧‧‧Phase phase shifter and delay circuit

Claims (12)

An output stage circuit includes: a power inverter coupled to a signal terminal; and a dynamic bias circuit electrically coupled to a system voltage terminal and the power phase Between the devices, the dynamic bias circuit includes at least one Zener diode for maintaining a voltage across a first absolute value between a gate and a source of at least one transistor of the power inverter The cross-voltage between the gate and the drain, the drain between the drain and the source is within a second absolute value range, wherein the dynamic bias circuit further includes at least one resistor and the At least one Zener diode is connected in parallel. The output stage circuit of claim 1, wherein the at least one Zener diode is connected between the gate of the at least one transistor and the source, and the anode of the at least one Zener diode Connecting the gate, a cathode of the at least one Zener diode is connected to the source. The output stage circuit of claim 1, wherein the at least one Zener diode is connected between the gate of the at least one transistor and the source, and the anode of the at least one Zener diode Connected to the source, a cathode of the at least one Zener diode is connected to the gate. The output stage circuit of claim 1, wherein the dynamic bias circuit comprises: at least one diode is located between the voltage terminal of the system and the gate, and the anode of the at least one diode is connected to the anode a gate, the cathode of the at least one diode is connected to the voltage terminal of the system. The output stage circuit of claim 1, wherein the dynamic bias circuit comprises: At least one diode is located between the voltage terminal of the system and the gate, an anode of the at least one diode is connected to the voltage end of the system, and a cathode of the at least one diode is connected to the gate. The output stage circuit of claim 1, wherein the power inverter comprises at least two pairs of stacked complementary metal oxide half field effect transistors. The output stage circuit of claim 1, wherein the output stage circuit further comprises: a protection circuit connected to the power inverter for guiding an instantaneous overvoltage, the protection circuit comprising at least one transistor, a gate of the at least one transistor is coupled to the signal terminal, and a source of the at least one transistor is grounded, and a drain of the at least one transistor of the protection circuit is connected to the source of the at least one transistor of the power inverter . The output stage circuit of claim 1, wherein the output stage circuit further comprises: a protection circuit connected to the power inverter for guiding an instantaneous overvoltage, the protection circuit comprising at least one transistor, a gate of the at least one transistor is coupled to the signal terminal, and a source of the at least one transistor is grounded, and a drain of the at least one transistor of the protection circuit is connected to the source of the at least one transistor of the power inverter . The output stage circuit of claim 1, wherein the output stage circuit comprises: at least one quasi-phase shifter, wherein the input end of the at least one quasi-phase shifter is respectively connected to the signal end and the voltage end of the system, An output of the at least one quasi-phase shifter is coupled to one of the gates of the power inverter. The output stage circuit of claim 1, wherein the voltage terminal of the system comprises: a first high voltage end electrically connected to one source of the power inverter; and a second high voltage end The output voltage of the first high voltage end is greater than the output voltage of the second high voltage end, and the output voltages of the first and second high voltage ends are positive values; and the first low voltage end is electrically connected to the first low voltage end Connecting a source of the power inverter; and a second low voltage end, the output voltage of the first low voltage end is configured to be smaller than the output voltage of the second low voltage end, and the output voltages of the first and second low voltage ends are Is a negative value. A signal processing method for an output stage circuit is adapted to control a power inverter, the method comprising: receiving a first level signal to turn on a P-type transistor of the power inverter and turning off the power inverter An N-type transistor; maintaining a span between the gate and the source of the P-type transistor within a first absolute value range by a first Zener diode connected in parallel with a first resistor, The voltage across the P-type transistor operates in a linear region when turned on; outputs a drain voltage when the P-type transistor operates in a linear region; receives a second level signal to turn on the N-type transistor and cuts off The P-type transistor; maintaining a span between the gate and the source of the N-type transistor in a second absolute value range by a second Zener diode connected in parallel with a second resistor, The voltage across the N-type transistor is applied to the linear region when turned on; and a drain voltage when the N-type transistor operates in the linear region. The method for processing a signal according to claim 11, wherein the method includes: closing a protection circuit coupled to the P-type transistor according to the first level signal, and opening a protection coupled to the N-type transistor And the protecting circuit coupled to the N-type transistor is turned off according to the second level signal, and the protection circuit coupled to the P-type transistor is turned on.