TWI590252B - Non-volatile memory device metod for fabricatin the same and applications thereof - Google Patents

Description

Non-volatile memory component and manufacturing method and application thereof

Embodiments of the present invention are directed to a non-volatile memory device. In particular, it relates to a high density non-volatile memory element having a three-dimension 3D array internally composed of multiple planes of memory cells.

Semiconductor components can generally be classified into volatile semiconductor components that require electrical storage of stored materials, as well as non-volatile semiconductor components that retain data after power removal. Flash memory components are a case of non-volatile semiconductor components. It generally includes a matrix of memory cells arranged by rows and columns. Each of the memory cells in the matrix contains a transistor structure having a gate, a drain and a source, and a channel defined between the drain and the source. Each memory cell is formed at an intersection of a word line and a bit line. Wherein, the gate is connected to the word line; the drain is connected to the bit line; and the source is connected to the source line of the subsequent ground. The gate of a conventional flash memory cell typically includes a dual-gate structure with control gates and floating gates. The floating gate is suspended (suspense) in two oxide layers Between, to capture the electrons written into the memory cell.

The flash memory component can be further divided into a reverse gate (hereinafter referred to as NAND) and an inverse or gate (hereinafter referred to as NOR) flash memory component. Among them, the anti-gate flash memory components generally provide faster writing and erasing speeds. A large part of this is due to his serialized structure, which allows write and erase operations to be performed on the entire memory string.

However, as the use of anti-gate flash memory components has increased dramatically, high performance read operations and data retention have become more important in some markets than write performance. For example, in addition to these markets, game cards and automated global positioning (GPS) systems require high read cycles and better data retention performance. Therefore, there is a growing demand for gate flash memory components that exhibit better data retention and read performance while maintaining faster write and erase speeds.

The inverse flash memory device uses Fowler-Nordheim tunneling for memory cell writing by high voltage (or potential) between the substrate and the word line. Dropping electrons from the substrate into the floating gate and filling them into traps. When electrons fill these traps, the potential barrier between the oxide layer and the floating gate increases. When a further write operation continues, as the previous write operation applies the same charge to the memory cell, the increased oxide barrier reduces the amount of charge added to the floating gate during the write operation, thus causing the memory The component has a higher threshold voltage.

Some attempts to improve performance have been directed to prevent the direction of memory cell interference. Start. In particular, the memory for the flash memory component is easily damaged by an increase in time due to repeated write erase operations, thereby disturbing the memory cells that have not been written to the erase operation. For example, when a memory cell is written in a selected word line, a write voltage (Vpgm) is applied to the selected word line, and a pass voltage (Vpass) is applied to the unselected word. Yuan line. Wherein, the pass voltage Vpass applied to the unselected word line must be high enough that the boost is also high enough to sustain the entire write operation. At the same time, because of too high, the probability of multiple memory cells in the selected memory cell string being simultaneously subjected to the write operation is increased.

Therefore, in order to prevent the occurrence of interference. There have been some attempts to adjust the operating conditions of non-volatile memory components by reducing the pass voltage to a level that is less likely to cause read disturb. However, to reduce the path voltage, the program verify (PV) voltage threshold must be lowered to maintain a similar pass voltage window (a range of path voltage drops that prevents most read writes from interfering). Reducing the pass voltage will hinder the memory operating window of the non-volatile memory component.

Therefore, there is a need to increase the write operation efficiency of non-volatile memory elements in the technical field.

In accordance with an embodiment of the present invention, a non-volatile memory element is provided that prevents write disturb from occurring and increases memory operation margin. Wherein, the non-volatile memory component comprises a plurality of string selection lines.

As described above, in the write operation, the gate flash memory component In the unselected bit line of the common word line, unintended electrons are simultaneously pulled into the floating gate. And when the electrons fill these traps, the energy barrier of the oxide layer will increase, and the last write operation will cause the memory cell with the state "1" to have a higher threshold voltage. To counteract this effect, the embodiments disclosed herein exert a coupling effect on the memory cells to increase the potential of the substrate of the selected memory cell. By offsetting the high write voltage (Vpgm) applied to the word line during the write operation, this mechanism can increase the duration of memory cell data retention and continue to provide accurate read performance.

In some embodiments, a means of controlling a non-volatile memory element can be provided. The device includes a stereoscopic array of a plurality of non-volatile memory cells. The stereoscopic array includes a plurality of stacks, each stack comprising (1) a plurality of NAND non-volatile memory strings; each NAND non-volatile memory string is coupled to a bit line. (2) A plurality of string select lines (SSL) and one or more word lines. The plurality of series of select lines and the one or more word lines are orthogonally aligned with the plurality of NAND non-volatile memory strings. The aforementioned one or more word lines construct a plurality of non-volatile memory cells as described above at intersections between the surface of the plurality of layers and the one or more word lines. Each string select line includes a plurality of serial select line (SSL) transistors for coupling the string select lines to corresponding NAND non-volatile memory strings. Wherein at least one first serial select line is constructed to receive the first voltage and a second serial select line is constructed to receive the second voltage, and the second serial select line is closer to the one or more words yuan line.

In some embodiments, the apparatus further includes a control circuit configured to write (suppress) the memory cells of the common word line but not the bit lines, by using the first string The column select line applies a first voltage and the second string select line applies a second voltage when the bit lines have different bias voltages. The second string selection line is closer to the foregoing word line; the first voltage is 0; the second voltage is lower than the operating voltage (VDD) and greater than 0.

In some embodiments, the apparatus further includes a control circuit configured to write (suppress) the common word line and share the memory cell of the bit line by applying the first string select line transistor The first voltage applies a second voltage to the second series select line when the bit line has an operating voltage VDD. The second string selection line is closer to the aforementioned word line; the first voltage is the operating voltage VDD; and the second voltage is lower than the operating voltage VDD and greater than zero.

In some embodiments, the apparatus further includes a control circuit configured to write (suppress) the common word line and share the memory cell of the bit line by applying the first string select line transistor The first voltage applies a second voltage to the second series select line when the voltage of the bit line is zero. The second string selection line is closer to the aforementioned word line; the first voltage is 0; the second voltage is lower than the operating voltage VDD and greater than 0.

In some embodiments, the non-volatile memory component may be a vertical channel-type three-dimensional semiconductor memory device including a substrate and a plurality of through holes. Device).

In some embodiments, each NAND non-volatile memory string is tied associated with an even bit line or an odd bit line. And each of the NAND non-volatile memory strings connected to the even bit lines can be written independently of the NAND non-volatile memory strings connected with the odd bit lines.

In some embodiments, the non-volatile memory component comprises a flash memory. In some embodiments, the non-volatile memory component comprises a NAND flash memory. In some embodiments, the device further includes a stereo NAND element. The stereo NAND device includes at least one of an n-type doped substrate, a p-type doped substrate, and an undoped substrate formed by implanting an n-type dopant.

In some embodiments, a non-volatile memory component can be provided. The non-volatile memory component includes a stereoscopic array of a plurality of non-volatile memory cells. The stereoscopic array includes a plurality of stacks, each stack comprising (1) a plurality of NAND non-volatile memory cell strings; each NAND non-volatile memory cell string is coupled to a bit line. (2) A plurality of string selection lines and one or more word lines. The plurality of series of select lines and the one or more word lines are arranged orthogonally to the plurality of NAND non-volatile memory strings. The one or more word lines may construct the plurality of non-volatile memory cells as described above at an intersection between the surface of the plurality of layers and the one or more word lines. Each of the serial select lines includes a plurality of serial select line transistors for coupling the series select lines to the corresponding NAND non-volatile memory strings. Among them, at least one first series The select line is configured to receive the first voltage and a second string select line is configured to receive the second voltage, and the second string select line is closer to the one or more word lines.

In some embodiments, the non-volatile memory component further includes a control circuit configured to write (suppress) the memory cells of the common word line but not the bit lines, by selecting the first string The line applies a first voltage and a second voltage is applied to the second series of select lines when the bit lines have different bias voltages. The second string selection line is closer to the aforementioned word line; the first voltage is 0; the second voltage is lower than the operating voltage VDD and greater than 0.

In some embodiments, the non-volatile memory component further includes a control circuit configured to write (suppress) the common word line and share the memory cell of the bit line by selecting the line for the first string The transistor applies a first voltage and applies a second voltage to the second series of select lines when the bit line has an operating voltage VDD. The second string selection line is closer to the aforementioned word line; the first voltage is the operating voltage VDD; and the second voltage is lower than the operating voltage VDD and greater than zero.

In some embodiments, the non-volatile memory component further includes a control circuit configured to write (suppress) the common word line and share the memory cell of the bit line by selecting the line for the first string The transistor applies a first voltage and applies a second voltage to the second series of select lines when the voltage of the bit line is zero. The second string selection line is closer to the aforementioned word line; the first voltage is 0; the second voltage is lower than the operating voltage VDD and greater than 0.

In some embodiments, the non-volatile memory component can be a package A vertical channel type three-dimensional semiconductor memory element including a substrate and a plurality of through holes.

In some embodiments, each NAND non-volatile memory string is coupled to an even bit line or an odd bit line. And each of the NAND non-volatile memory strings connected to the even bit lines can be written independently of the NAND non-volatile memory strings connected with the odd bit lines.

In some embodiments, the non-volatile memory component comprises a flash memory. In some embodiments, the non-volatile memory component comprises a NAND flash memory. In some embodiments, the device further includes a stereo NAND element. The stereo NAND device includes at least one of an n-type doped substrate, a p-type doped substrate, or an undoped substrate formed by implanting an n-type dopant.

In some embodiments, a method of controlling non-volatile memory components can be provided. The method includes providing a non-volatile memory component comprising a stereoscopic array of a plurality of non-volatile memory cells. The stereoscopic array includes a plurality of stacks, each stack comprising (1) a plurality of NAND non-volatile memory cell strings; each NAND non-volatile memory cell string is coupled to a bit line. (2) A plurality of string selection lines and one or more word lines. The plurality of series of select lines and the one or more word lines are arranged orthogonally to the plurality of NAND non-volatile memory strings. The one or more word lines may construct the plurality of non-volatile memory cells as described above at an intersection between the surface of the plurality of layers and the one or more word lines. Each of the serial select lines further includes a plurality of serial select line transistors for coupling the series select lines to the corresponding NAND non-volatile memory strings. Wherein at least one first serial selection line is constructed to receive the first voltage And a second string select line is constructed to receive the second voltage, and the second string select line is closer to the one or more word lines.

In some embodiments, a memory cell is provided that provides a control circuit to write (suppress) the common word lines but not the bit lines. The second voltage is applied to the second series of select lines by applying a first voltage to the first series of select lines, and the bit lines have different bias voltages. The second string selection line is closer to the aforementioned word line; the first voltage is 0; the second voltage is lower than the operating voltage VDD and greater than 0.

In some embodiments, further comprising providing a control circuit to write (suppress) the common word line and share the bit line of the memory cell by applying a first voltage to the first string select line transistor, A second voltage is applied to the second string select line when the bit line has an operating voltage VDD. The second string selection line is closer to the aforementioned word line; the first voltage is the operating voltage VDD; and the second voltage is lower than the operating voltage VDD and greater than zero.

In some embodiments, further comprising providing a control circuit to write (suppress) the common word line and share the bit line of the memory cell by applying a first voltage to the first string select line transistor, A second voltage is applied to the second string select line when the voltage of the bit line is zero. The second string selection line is closer to the aforementioned word line; the first voltage is 0; the second voltage is lower than the operating voltage VDD and greater than 0.

In some embodiments, providing a non-volatile memory element further comprises providing a stereo NAND element. The stereo NAND device includes at least one of an n-type doped substrate, a p-type doped substrate, or an undoped substrate formed by implanting an n-type dopant.

The summary above is merely a summary of some embodiments to provide a basic understanding of the invention. Therefore, it is to be understood that the above-described embodiments are merely illustrative and are not intended to limit the scope of the invention to any one of the embodiments. It should be understood that the scope of the present invention includes other embodiments not disclosed in the above embodiments. Some of them will be further detailed below.

100‧‧‧Semiconductor components

102‧‧‧Control circuit

104‧‧‧Non-volatile memory unit

605, 610, 615, 620, 810, 815, 820, 1205, 1210, 1215, 1305, 1310, 1315, 1405, 1410, 1415‧‧ ‧ memory cells

1805‧‧‧ Conductive layer

1805a‧‧‧Top conductive layer

1805b‧‧‧ bottom conductive layer

1810‧‧‧Isolation

1815‧‧‧ incision

1820p‧‧‧ type doped substrate

1825‧‧‧n type doped substrate

WL0...WL23, WL...WLn-1, WL _n ‧‧‧ character lines

BLn, BLn+1, BL<p>...BL<q>, ‧‧‧ bit line

BL _o ‧‧‧ odd bit line

BL _e ‧‧‧ even bit line

MGSL‧‧‧ Grounding selection line

MSSL, SSL(n), SSL(n-1), SSL<0>, SSL<1>, SSL<7>‧‧‧ Serial selection line

VDD, VDD'‧‧‧ working voltage

Vpass‧‧‧ channel voltage

Vpgm‧‧‧ write voltage

The foregoing embodiments will be described in detail with reference to the accompanying drawings. The drawings are not shown in the same scale, wherein: FIG. 1 is a block diagram showing a semiconductor device including a control circuit and a plurality of serial memory units according to an embodiment of the invention; FIG. 2A is a schematic diagram A circuit diagram of a conventional two-dimensional NAND structure; FIG. 2B is a schematic circuit diagram of a conventional three-dimensional NAND structure constructed using the two-dimensional NAND structure of FIG. 2A; FIG. 3 is a schematic diagram of an embodiment of the present invention according to an embodiment of the present invention; A schematic diagram of a circuit of a two-dimensional NAND structure; FIG. 4 is a circuit diagram of a three-dimensional NAND structure according to an embodiment of the invention; FIG. 5A is a top view of a substrate according to an embodiment of the invention, which is identifiable A separation state between even and odd bit lines and a vertical channel array.

5B is a vertical channel series corresponding to FIG. 5A; FIG. 6 is a diagram showing a single serial selection line according to an embodiment of the invention. a write operation performed on the selected memory cell by the structure; FIG. 7 illustrates a write operation performed on the selected memory cell using a single serial select line structure according to an embodiment of the present invention; 8 is a diagram of another write operation performed on a selected memory cell using a single serial select line structure according to an embodiment of the present invention; FIG. 9 is a diagram showing another use of a single according to an embodiment of the present invention. The serial selection line structure performs a write operation on the selected memory cell; FIG. 10 illustrates another write of the selected memory cell using a single serial selection line structure according to an embodiment of the present invention. 11A is a diagram showing an application of a transient pulse according to an embodiment of the present invention; FIG. 11B is a diagram showing a relationship between time and lateral effect of leakage according to an embodiment of the present invention; FIG. 12 is a diagram showing a write operation on a selected memory cell using a plurality of serial select line structures according to an embodiment of the present invention; FIG. 13 is a view showing another use according to an embodiment of the present invention; The column string selection line structure performs a write (suppression) operation on the selected memory cell; and FIG. 14 illustrates another memory cell selected using a plurality of series selection line pairs according to an embodiment of the present invention. Write (suppression) operation performed; Fig. 15 is a diagram showing application of transient pulses according to an embodiment of the present invention; and Fig. 16A is a top view showing layout of different vertical channel holes according to an embodiment of the present invention ; 16B is a diagram illustrating various different shapes of vertical channel apertures according to an embodiment of the present invention; and FIG. 17 is a circuit diagram showing a two-dimensional NAND structure according to an embodiment of the present invention; and FIGS. 18A and 18B The drawings illustrate schematic cross-sectional views of alternative structures embodying embodiments of the present invention.

Some embodiments of the invention are further described below with reference to the drawings. Only some, but not all, of the embodiments are described. In fact, the present invention may be embodied by many different structural embodiments and should not be construed as being limited to the disclosed embodiments. Rather, these embodiments are provided only to comply with the provisions of the specification. In the different embodiments, the same elements will be denoted by the same element symbols.

The term "non-volatile memory component" as used herein refers to a semiconductor component that still stores information when power is removed. Non-volatile memory components include, but are not limited to, Mask Read-Only Memory, Programmable Read-Only Memory, and Erasable Rewritable Read-Only Memory (Erasable Programmable Read-Only Memory), Electronically Erasable Programmable Read-Only Memory, and Flash Memory.

The term "substrate" as used herein refers to any material located below, or used to form a circuit, epitaxial layer or semiconductor thereon. material. In general, a substrate can be defined as one or more layers underlying a semiconductor component, or even one or more layers used to form a substrate layer of a semiconductor component. The substrate can comprise one or any combination of germanium, germanium, antimony, bismuth, semiconductor composite or other semiconductor materials.

Referring to FIG. 1, a block diagram of a semiconductor device 109 is provided. The semiconductor component 100 includes a control circuit 102 and a plurality of serially coupled non-volatile memory cells 104. The control circuit 102 is in communication with each of the serially connected memory cells 104 and is configured to dominate read, write erase, and other operations applied to the memory cells 104. Each memory unit 104 may include a matrix of memory cells arranged in a matrix. For example, a schematic diagram of a conventional two-dimensional NAND structure is shown in FIG. 2A.

Each of the memory cells in the matrix includes a transistor structure having a gate, a drain, a source, and a channel defined between the drain and the source. Each memory cell is located at an overlapping position between a word line and a bit line. The gate is connected to the word line; the drain is connected to the bit line; and the source is connected to the source line of the subsequent ground. The gate of a conventional flash memory cell typically includes a dual gate structure with a control gate and a floating gate. The floating gate is suspended between the two oxide layers to capture electrons written into the memory cells. In some embodiments, each memory unit 104 can include a stereo memory. 2B is a circuit diagram showing a conventional stereo NAND structure constructed using the two-dimensional NAND structure of FIG. 2A. FIG. 3 is a circuit diagram showing a two-dimensional NAND structure according to an embodiment of the invention. 4 is a perspective view of a stereo NAND structure according to an embodiment of the present invention. Circuit diagram.

Traditional structure

As depicted in FIG. 2A, in conventional NAND flash memory, memory cells are connected in series with one another (eg, typically 6 or 32 groups). For example, the memory cell matrix as shown. The memory cell matrix is part of a block in a non-volatile memory component (such as one of the memory cells 104 depicted in FIG. 1). Each of the non-volatile memory elements includes a plurality of word lines (such as WL... and WL _n depicted in FIG. 2A) and intersects with a plurality of sequentially arranged even and odd bit lines. . In Figure 2A, the illustrated block portion depicts one odd bit line (BL _o ) and two even bit lines (BL _e ). The memory cell is located at each intersection of the word line and the bit line. Since FIG. 2A shows n word lines and 3 bit lines. So there will be a total of 3 n memory cells.

Two select transistors are placed at the edge of the stack to ensure (via ground selection line MGSL) connections to ground and (via serial select line MSSL) to the bit lines. When the memory cell is read, the gate voltage is set to 0V, and a bias voltage of a high voltage (typically 4-5V) is applied to the other gates of the stacked structure, so that it becomes a via transistor regardless of the threshold voltage ( Pass-transistor). The NAND flash memory after being erased has a negative voltage of a negative value. Conversely, the NAND flash memory after being written has a positive value of the forward voltage. But regardless of which embodiment, the voltage value is less than 4V. In fact, the selection gate is driven at 0V, and if the addressed memory cell is erased, all connected memory cells will sink current. The opposite of, When the addressed memory cell is in the write state, there is no memory cell sink current.

2B is a circuit diagram showing a conventional stereo NAND structure constructed using the two-dimensional NAND structure of FIG. 2A. As shown, each NAND layer (one of which is shown in Figure 2A) contains a plurality of word lines (such as WL0... and WL23 as depicted in Figure 2B), and an even number of multiple ordered orders. The odd bit lines (such as BL<p>...BL<q> depicted in FIG. 2B) intersect. In addition, each NAND layer contains a single serial selection line (such as SSL<0>, SSL<1>, and SSL<7> as depicted in FIG. 2B).

Multiple serial selection lines

FIG. 3 is a circuit diagram showing a two-dimensional NAND structure according to an embodiment of the invention. As shown in the figure, according to an embodiment of the invention, the NAND structure may include a plurality of word lines (such as WLn-1... and WLn as shown in FIG. 3), and a plurality of even numbers arranged in sequence. Intersect with odd bit lines (BLe and BLo as depicted in Figure 3).

In some embodiments, a plurality of string selection lines can be provided. The plurality of bars (2) as shown in FIG. 3 are serially selected by the lines SSL(n) and SSL(n-1).

4 is a circuit diagram showing a stereo NAND structure according to another embodiment of the present invention.

Here, each NAND layer includes a plurality of word lines (such as WLn-1... and WLn as shown), and a plurality of sequentially arranged bit lines (such as BLe and BLo as shown). cross. In addition, each NAND layer includes a plurality of string select lines. The plurality of strings select lines SSL(n) and SSL(n-1) as shown in the figure. its The word lines in each NAND layer are electrically connected to each other (that is, the word lines WLn in each individual NAND layer have the same voltage); the serial selection lines in each NAND layer are not electrically connected to each other. Sexual connection (that is, the serial selection lines SSL(n) and SSL(n-1) are not electrically connected to each other).

Write

The "write operation" phase information is written into the memory cell, which is typically performed by transferring electrons from the memory cell substrate to its floating gate. The NAND flash memory component is written into the memory cell using a Fourer-Nordham tunneling method. During the writing process, the amount of electrons passing through the tunneling oxide layer depends on the electric field strength: the greater the electric field strength, the greater the probability of electron injection.

In NAND memory, a memory cell is part of a memory cell string, and this memory cell can be selected by a drain and source selector. 5A is a top view of a substrate that identifies a separation state between even and odd bit lines and a vertical channel array, in accordance with an embodiment of the present invention. Figure 5B is a vertical channel series corresponding to Figure 5A. The even bit lines can be connected to each of the vertical channel strings identified as even; the odd bit lines are connected to each of the vertical channel strings identified as odd. Therefore, the odd channel and the corresponding memory cell string share the odd bit line and thus have the same bias condition; the even channel and the corresponding memory cell share the even bit line, and thus have the same Biased state.

Figure 6 illustrates a write operation performed on a selected memory cell using a single serial select line, in accordance with an embodiment of the present invention. In order to be selected The memory cell (for example, the memory cell 605) performs a write operation, and applies a bias voltage to the corresponding drain selector to the operating voltage VDD; the voltage of the memory cell string that should not be written is set to the path voltage Vpass (ie, 8-10V); the gate voltage of the source selector is 0V; the bias voltage of 0V is applied to the bit line. The gate voltage of the written memory cell is set to the write voltage Vpgm (ie, 20V). That is to say, the written memory cell has a 0V drain voltage; the source remains in a floating state; and a high voltage is applied to its gate. The bit line voltage of the selected memory cell is set to 0V or ground.

Here, the memory cells sharing the same gate and bit lines with the written memory cells are all written (for example, the memory cells 610, 615, and 620 are all written). In order to avoid unintended writing operations on the memory cells sharing the same gate with the memory cells that are written but not sharing the bit lines, the voltage of the corresponding bit line is set to 0V; corresponding to the string selection line The voltage is set to 0V to shut down these memory cells.

Figure 7 illustrates an alternative write operation to a selected memory cell using a single serial select line in accordance with an embodiment of the present invention. Here, in order to avoid an unexpected write operation to the memory cell sharing the same gate and bit line with the memory cell being written, the voltage of the corresponding bit line is set to the operating voltage VDD; The voltage of the selection line is set to the operating voltage VDD, thereby disconnecting these memory cells. In order to avoid unintended writing operations on the memory cells sharing the same gate with the memory cells that are written but not sharing the bit lines, the voltage of the corresponding bit line is set to 0V; corresponding to the string selection line The voltage is set to 0V to disconnect these memory cells.

Figure 8 illustrates yet another write operation performed on a selected memory cell using a single serial select line, in accordance with an embodiment of the present invention. Memory cells sharing the same gate and bit lines with the written memory cells are written (eg, memory cells 810, 815, and 820 are all written). In order to avoid unintended writing operations on the memory cells sharing the same gate with the memory cells that are written but not sharing the bit lines, the voltage of the corresponding bit line is set to 0V; corresponding to the string selection line The voltage is set to 0V to disconnect these memory cells.

Figure 9 is a diagram showing another write operation performed on a selected memory cell using a single serial select line in accordance with an embodiment of the present invention. Here, in order to avoid an unexpected write operation to the memory cell sharing the same gate and bit line with the memory cell being written, the voltage of the corresponding bit line is set to the operating voltage VDD; The voltage of the selection line is set to the operating voltage VDD, thereby disconnecting these memory cells. In order to avoid unintended writing operations on the memory cells sharing the same gate with the memory cells that are written but not sharing the bit lines, the voltage of the corresponding bit line is set to 0V; corresponding to the string selection line The voltage is set to 0V to disconnect these memory cells.

Figure 10 is a diagram showing another write operation performed on a selected memory cell using a single serial select line structure in accordance with an embodiment of the present invention; and an embodiment providing the present invention (especially having many Example of a column string selection line) A background for operational improvement. The structure shown in FIG. 10 is the same as that in FIG. 7. Figure 10 illustrates that the bit lines in the same block have different bias voltages. That is, different bias voltages are applied to the bit lines BLn and BLn+1, respectively (for example, BLn=0V and BLn+1 = operating voltage VDD). The write operation is as described above, and thus problems associated with write and path interference may be encountered.

Write disturb occurs in memory cells that share the same gate but do not share bit lines. Write disturb can be reduced by increasing the pass voltage Vpass at the expense of increased path interference. Path interference occurs in memory cells that are on the same NAND string as the selected memory cell. In this embodiment, the channel potential can be set to ground, and the voltage of the gate nod is set to the path voltage Vpass. The write voltage that is effective for these memory cells is the path voltage Vpass. Write (suppression) reduces the electric field of the tunneling dielectric (TD) and prevents charge injection by boosting the floating channel to a higher voltage (ie, higher than the pass voltage Vpass). However, the weakness of this method is the resistance to leakage.

Therefore, a compromise can usually be achieved, such as applying a voltage to a gate of an unselected memory cell, such as between 8V and 10V. The channel boost is directly proportional to this voltage value: the higher the voltage value, the larger the channel boost value and the longer the duration. However, this voltage selection is a key point: a voltage that is too high increases the probability that a memory cell that is in series with the selected memory cell will be subjected to an unintended write operation (ie, so-called channel interference); if the voltage is too low, the channel cannot be guaranteed. The boost value amplitude is high enough for the entire write operation to write to the selected memory cell located in the same row (ie, so-called write disturb).

Figure 11A is a diagram showing the application of a transient pulse in accordance with an embodiment of the present invention. Fig. 11B is a graph showing the relationship between the gate bias voltage (path voltage Vpass and write voltage Vpgm) of the word line and time. As can be seen from the figure, the electrostatic potential is low. Starting at 1E-6, the channel voltage Vpass at 3E-6 is applied corresponding to the application of the transient pulse to 10V. When a transient pulse is applied to the path voltage Vpass of 4E-6, the electrostatic potential is maintained at 10V. When the transient pulse is at 1E-5, leakage occurs and the electrostatic potential drops below 10V. When the transient pulse is at 1E-4 and the pass voltage Vpass is still applied, the electrostatic potential is lowered to 6V. That is, the leakage conducts to a decaying voltage and, in some embodiments, causes an unexpected write operation.

Traditionally, the pass voltage Vpass is maintained at a low level to prevent channel interference. However, the lower path voltage Vpass leads to a low boost potential. In addition, leakage during write (suppression) reduces the channel potential, causing unexpected write operations. There is a need to provide a way to maintain high channel potential.

Write with multiple serial select lines

In general, a non-volatile memory element having a plurality of series select lines can be provided. In the process of writing (suppressing), by giving a plurality of serial selection line structures, a relatively low leakage effect can be achieved, and the boosting can be maintained at a preset level without causing a voltage drop. It is possible to prevent unselected memory cells from being written. In addition, improving the boost condition can reduce write disturb and increase memory operation margin.

More specifically, a non-volatile memory element comprising a non-volatile memory stereo array can be provided. In some embodiments, the stereoscopic array includes a plurality of stacks, each stack including a plurality of NAND non-volatile memory strings, a plurality of string select lines, and one or more word lines. Each NAND non-volatile memory cell is coupled in series to a bit line. In some embodiments, the plurality of series of select lines and word lines and the plurality of NAND non-volatile memories described above The cells are arranged in a straight line. The aforementioned one or more word lines construct the aforementioned plurality of non-volatile memory cells at the intersection between the surface of the plurality of layers and the one or more word lines. Each of the serial select lines includes a plurality of serial select line transistors for coupling the series select lines to the corresponding NAND non-volatile memory strings. In some embodiments, at least one first string select line is configured to receive the first voltage and a second string select line is configured to receive the second voltage, and the second string select line is closer to the aforementioned one Or multiple word lines.

A. The bit lines in the same block have different bias voltages

Figure 12 illustrates a write operation to a selected memory cell using a plurality of serial select line structures in accordance with an embodiment of the present invention. In order to perform a write operation on the selected memory cell (for example, the memory cell 1205), the corresponding drain selector is biased to the operating voltage VDD; the voltage of the memory cell string that should not be written is set to The path voltage Vpass (ie, 8-10V); the gate voltage of the source selector is 0V; a bias voltage of 0V is applied to the bit line. The gate voltage of the written memory cell is set to the write voltage Vpgm (ie, 20V). The bit line voltage of the selected memory cell is set to 0V or ground.

Here, in order to avoid an unexpected write operation to the memory cell sharing the same gate and bit line with the memory cell being written, the voltage of the corresponding bit line is set to the operating voltage VDD; The voltage of the column select line is set to the operating voltage VDD, thereby disconnecting these memory cells (see memory cells 1210 and 1215). In order to avoid an unexpected write operation to a memory cell that shares the same gate with the memory cell being written but does not share the bit line, the voltage of the corresponding bit line is set to 0V; The voltage of the corresponding serial selection line is set to 0V, thereby disconnecting these memory cells. In some embodiments, as with conventional non-volatile memory components, the voltage of the second series select line can also be set to 0V (as previously described, this can lead to write or path interference).

In order to prevent leakage (to improve the operating margin of the memory and reduce write disturbance), the voltage of the second series select line can also be set to the drain voltage operating voltage VDD' (hereinafter referred to as the operating voltage VDD'), wherein the operating voltage VDD 'greater than 0 but less than the operating voltage VDD. By setting the voltage of the second string selection line to the operating voltage VDD', the potential of the floating channel in the second series selection line can be made not equal to 0V (e.g., 3.3V, 5V, etc.). This reduces the channel potential gradient between the string select line and the bit line and reduces leakage due to steep channel potential gradients and unexpected write operations.

Therefore, the leakage will be maintained at a lower level, and the boosting potential can be at a preset level (for example, 10V) without causing a voltage drop. You can increase the memory operation margin.

B. The bit line in the same block has the same bias voltage as the working voltage VDD

Figure 13 illustrates another write (suppression) operation performed on a selected memory cell using a plurality of serial select line structures in accordance with an embodiment of the present invention. In order to perform a write operation on the selected memory cell (eg, memory cell 1305), a bias voltage of the operating voltage VDD is applied to the corresponding drain selector; the voltage setting of the memory cell string that should not be written is set. It is the pass voltage Vpass (for example, 8-10V); the gate voltage of the source selector is 0V; a bias voltage of 0V is applied to the bit line. Written The gate voltage of the cell is set to the write voltage Vpgm (for example, 20V). The bit line voltage of the selected memory cell is set to 0V or ground.

Here, in order to avoid sharing the same gate with the memory cells being written but not sharing the bit line, the voltage of the corresponding bit line is set to 0V; and the voltage of the bit line of the selected memory cell is also selected. Set to 0V) to perform an unexpected write operation, the voltage of the corresponding serial select line is set to a voltage that can realize the write operation of the selected memory cell, such as the operating voltage VDD, and these unselected memory cells are simultaneously selected. (See memory cells 1310 and 1315) disconnected. In some embodiments, the voltage of the first series select line can be set to the operating voltage VDD; the voltage of the second series select line can be set to be less than the operating voltage VDD and greater than 0V. Therefore, the source can be floated at a voltage higher than zero (for example, 3.3V). In some embodiments, the voltage of the first series select line can be set to the operating voltage VDD; the voltage of the second series select line can also be set to the operating voltage VDD. In some embodiments, the voltage of the first series select line can be set to the operating voltage VDD'; the voltage of the second series select line can also be set to the operating voltage VDD'.

C. The bit line in the same block has a bias voltage of the same 0V

Figure 14 illustrates another write (suppression) operation performed on a selected memory cell using a plurality of serial select lines, in accordance with an embodiment of the present invention. In order to perform a write operation on the selected memory cell (for example, memory cell 1405), a bias voltage of the operating voltage VDD is applied to the corresponding drain selector; the voltage setting of the memory cell string that should not be written is set. It is the pass voltage Vpass (for example, 8-10V); the gate voltage of the source selector is 0V; a bias voltage of 0V is applied to the bit line. Memory cell The gate voltage is set to the write voltage Vpgm (for example, 20V). The ground selection line on the bit line is written.

Here, in order to avoid an undesired write operation for a memory cell that shares the same gate with the memory cell being written but does not share the bit line (the voltage of the corresponding bit line is set to 0 V), the corresponding string is arranged. The voltage of the select line must be set to a voltage that enables the write operation of the selected memory cell, such as the operating voltage VDD, while disconnecting these unselected memory cells (see memory cells 1410 and 1415). In some embodiments, the voltage of the first series select line can be set to 0V; the voltage of the second string select line can also be set to 0V. In some embodiments, the voltage of the first series select line can be set to 0V; the voltage of the second series select line can also be set to be less than the operating voltage VDD and greater than 0V. Therefore, the source can be floated at a voltage higher than zero (for example, 3.3V).

Figure 15 is a diagram showing the application of a transient pulse in accordance with an embodiment of the present invention. The left diagram of Fig. 15 particularly shows the lateral leakage relationship diagram, as shown in Fig. 11A for the relationship between time and lateral leakage. As can be seen from the left figure, the electrostatic potential starts to drop after the application of the path voltage Vpass (which is 1E-5), and a leakage phenomenon occurs; and an unexpected write is caused. In some embodiments, when the electrostatic potential is maintained at a high level, embodiments with multiple series select lines have a larger boost potential, which in turn results in less write disturb.

alternative plan

It must be understood that the vertical channel aperture array illustrated in Figure 5A is only used to clearly describe the present invention. Non-volatile in non-volatile memory components The memory element can comprise any number of vertical channel aperture arrays of other structures or shapes. Figure 16A is a top view showing the layout of different vertical channel apertures in accordance with an embodiment of the present invention. Figure 16B illustrates various different shapes of vertical channel apertures in accordance with an embodiment of the present invention. Additionally, although in some embodiments of the invention, one NAND flash memory component includes or uses two serial select lines. In some embodiments, any number (eg, 3, 4, 5) of string selection lines may still be included or used. For example, FIG. 17 illustrates an embodiment including two serial selection lines, three serial selection lines, and four serial selection lines, respectively. Additionally, some embodiments of the invention include or use NAND flash memory components. In some embodiments of the invention, other non-volatile semiconductor components, such as NOR flash memory components or other similar components, may still be included or used.

Additionally, some embodiments of the invention may be implemented in a structure as depicted in Figure 18A or Figure 18B. That is, some embodiments of the invention may be provided using a device comprising a non-volatile memory cell stereoscopic array. The stereoscopic array includes a plurality of conductive layers 1805 that are isolated from one another by a plurality of isolation layers 1810. The plurality of conductive layers 1805 include one or more top conductive layers 1805a and one or more bottom conductive layers 1805b. This or more of the top conductive layer 1805a includes n series select lines. This or more of the top conductive layer 1805a further includes n-1 slits 1815 filled with insulating material. Each of the slits 1815 can electrically separate the two series of selection lines. Each of the slits 1815 cuts into the top conductive layer 1805a to a certain depth, but does not extend into the bottom conductive layer 1805b. In some embodiments, the device further includes a stereo NAND element. This stereo NAND component package At least one of an n-type doped substrate, a p-type doped substrate, or an undoped substrate formed by implanting an n-type dopant. For example, the embodiment illustrated in FIG. 18A includes a p-type doped substrate 1820. The embodiment illustrated in FIG. 18B includes at least one n-type doped substrate 1825 formed by implanting an n-type dopant. The illustrations of Figures 18A and 18B are merely examples of the invention.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. The process steps and structures described herein do not encompass the complete fabrication process for making a full volume circuit. The present invention can be implemented in conjunction with a number of different integrated circuit fabrication techniques currently known or developed in the future. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

WL(n-1), WL(n)‧‧‧ character lines

BL _o ‧‧‧ odd bit line

BL _e ‧‧‧ even bit line

SSLn, SSLn-1‧‧‧ serial selection line

Claims (23)

An apparatus for controlling a non-volatile memory component, comprising: a stereoscopic array comprising a plurality of non-volatile memory cells; the stereoscopic array comprising: a plurality of stacks, each of the stacks comprising (1 a plurality of NAND non-volatile memory cells; each of the NAND non-volatile memory cells is coupled to a bit line; (2) a plurality of string select lines (SSL) and a Or a plurality of word lines; the string selection lines and the one or more word lines are orthogonally aligned with the NAND non-volatile memory strings; the one or more word lines will be Constructing the non-volatile memory cells at a plurality of cross points between the plurality of surfaces of the plurality of layers and the one or more word lines; each of the series of select lines includes a plurality Serialized select line (SSL) transistors for coupling the series select lines to the corresponding NAND non-volatile memory strings; wherein at least one of the first select lines is constructed to receive a first voltage and a second serial selection line are constructed to receive a second And wherein the second series select line is closer to the one or more word lines, and the second voltage is applied to the second string select line to have the plurality of different biases The second voltage is lower than an operating voltage (VDD) and greater than 0V. The device of claim 1, further comprising: a control circuit configured to write/suppress a plurality of memory cells sharing a word line but not sharing a bit line, The first voltage is applied to the first series select line; the first voltage is zero. The device of claim 1, further comprising: a control circuit configured to write/suppress a plurality of memory cells sharing a word line and sharing a bit line, by using the first The serial select line transistor applies the first voltage, the bit line having the operating voltage; wherein the first voltage is the operating voltage. The device of claim 1, further comprising: a control circuit configured to write/suppress a plurality of memory cells sharing a word line and sharing a bit line, by using the first string The first voltage is applied to the select line transistor, and the voltage of the bit line is 0; wherein the first voltage is zero. The device of claim 1, wherein the non-volatile memory component is a vertical channel-type three-dimensional semiconductor memory device comprising a substrate and a plurality of through holes. ). The device of claim 1, wherein each of the NANDs The non-volatile memory cell string is connected to an odd bit line of an even bit line; and each of the NAND non-volatile memory cell strings connected to the even bit line is independent of the odd bit The lines of the NAND non-volatile memory cells connected in series are written in addition to the line. The device of claim 1, wherein the non-volatile memory component comprises a flash memory. The device of claim 1, wherein the non-volatile memory component comprises a NAND flash memory. The device of claim 1, further comprising a stereo NAND device; the stereo NAND device comprises an n-type doped substrate and a p-type doped substrate formed by implanting an n-type dopant. At least one of a material and an undoped substrate. A non-volatile memory component, comprising: a stereoscopic array, consisting of a plurality of non-volatile memory cells; the stereoscopic array comprising: a plurality of stacks, each of the stacks comprising (1) a plurality of NAND non-volatile a string of memory cells; each of the NAND non-volatile memory cells is coupled to a bit line; (2) a plurality of string selection lines and one or more words a plurality of string selection lines and the one or more word lines are orthogonally arranged with the NAND non-volatile memory cells; the one or more word lines are on a plurality of surfaces of the plurality of layers Constructing the non-volatile memory cells at a plurality of intersections with the one or more word lines; each of the series selection lines includes a plurality of serial selection line transistors for The serial select lines are coupled to the corresponding NAND non-volatile memory strings; wherein at least one first serial select line is configured to receive a first voltage and a second serial select line is constructed Receiving a second voltage; and wherein the second series select line is closer to the one or more word lines, applying the second voltage to the second string select line to have the plurality of different bit lines The bias voltage; the second voltage is lower than an operating voltage and greater than 0V. The non-volatile memory component of claim 10, further comprising: a control circuit configured to write/suppress a plurality of memory cells sharing a word line but not sharing a bit line, The first voltage is applied to the first series select line transistor; wherein the first voltage is zero. The non-volatile memory component as described in claim 10, further comprising: a control circuit configured to write/suppress a plurality of memory cells sharing a word line and sharing one bit line, The first voltage is applied to the first string select line transistor, the bit line having the operating voltage; wherein the first voltage is the operating voltage. The non-volatile memory component as described in claim 10, further comprising: a control circuit configured to write/suppress a plurality of memory cells sharing a word line and sharing one bit line, The first voltage is applied to the first series select line transistor, and a voltage of the bit line is 0V; wherein the first voltage is 0V. The non-volatile memory component of claim 10, wherein the non-volatile memory component is a vertical channel type three-dimensional semiconductor memory component including a substrate and a plurality of through holes. The non-volatile memory component of claim 10, wherein each of the NAND non-volatile memory cell strings is connected to an odd bit line of an even bit line; and each of the even bits The NAND non-volatile memory cells connected by the line may be independent of the odd bit line The connected NAND non-volatile memory cells are externally written for writing. The non-volatile memory component of claim 10, wherein the non-volatile memory component comprises a flash memory. The non-volatile memory component of claim 10, wherein the non-volatile memory component comprises a NAND flash memory. The non-volatile memory device according to claim 10, further comprising a stereo NAND device; the stereo NAND device comprises an n-type doped substrate formed by implanting an n-type dopant, At least one of a p-type doped substrate and an undoped substrate. A method for fabricating a non-volatile memory device, comprising: providing a stereoscopic array of a plurality of non-volatile memory cells; the stereoscopic array comprising: a plurality of stacks, each of the stacks comprising (1) a plurality of NAND non-volatile memory cells; each of the NAND non-volatile memory cells is coupled to a bit line; (2) a plurality of string selection lines and one or more word lines; The serial selection lines and the one or more word lines are orthogonally arranged with the NAND non-volatile memory strings; the one or more word lines may be on the plurality of surfaces of the plurality of layers and the one or Between multiple word lines Constructing the non-volatile memory cells at a plurality of intersections; each of the series selection lines includes a plurality of serial selection line transistors for coupling the series selection lines to the corresponding ones NAND non-volatile memory cell strings; wherein at least one first string select line is configured to receive a first voltage and a second string select line is configured to receive a second voltage; and wherein the second The serial select line is closer to the one or more word lines, and the second voltage is applied to the second string select line to cause the bit line to have a plurality of different bias voltages; the second voltage is lower than one Operating voltage is greater than 0V. The method for fabricating a non-volatile memory device according to claim 19, further comprising: providing a control circuit for constructing/suppressing a plurality of memories sharing a word line but not sharing a bit line And applying the first voltage to the first series of select line transistors, wherein the first voltage is zero. The method for fabricating a non-volatile memory device according to claim 19, further comprising: providing a control circuit for constructing/suppressing a plurality of memory cells sharing a word line and sharing one bit line By selecting the first series The first line voltage is applied to the line selection transistor, the bit line having an operating voltage; wherein the first voltage is the operating voltage. The method for fabricating a non-volatile memory device according to claim 19, further comprising: providing a control circuit for constructing/suppressing a plurality of memory cells sharing a word line and sharing one bit line The first voltage is applied to the first series select line transistor, and a voltage of the bit line is 0V; wherein the first voltage is 0V. The method for fabricating a non-volatile memory device according to claim 19, further comprising: providing a stereo NAND device; and causing the stereo NAND device to include an n-type formed by implanting an n-type dopant At least one of a doped substrate, a p-type doped substrate, and an undoped substrate.