TWI590053B - Selective prefetching of physically sequential cache line to cache line that includes loaded page table - Google Patents

Description

Selective prefetch entity to connect the cache line to the cache line containing the paged table loaded

This invention relates to microprocessors, and more particularly to methods for prefetching data from microprocessors.

Many microprocessors today have the ability to use virtual memory, particularly the ability to utilize a memory paging mechanism. Those skilled in the art will appreciate that the page tables established by the operating system in system memory are used to translate virtual addresses into physical addresses. The x86 architecture processor technology described in the IA-32 Intel® Architecture Software Developer's Manual, Volume 3A: System Programming Guide, Part 1, June 2006 (the full reference is cited by reference) Incorporated herein, the pagination table can be arranged in a hierarchical fashion. Specifically, the paging table includes page table entries (PTE), and each page table item stores an attribute of an entity paged address and a physical memory page of a physical memory page. The so-called pagewalk refers to extracting a virtual memory paging address and using the virtual memory paging address to traverse the paging table hierarchy for obtaining the paging corresponding to the virtual memory paging address. table Project to translate virtual addresses into physical addresses.

Since the delay time of physical memory access is relatively long, and the physical memory may be accessed multiple times during the paging table search, it is time consuming to perform paging table search. In order to avoid the time consumption caused by the execution of the paging table search, the processor usually includes a Translation Lookaside Buffer (TLB) for storing the virtual address and the physical address translated by the virtual address. However, the size of the translation query buffer is limited, and a page table lookup is still required when the translation buffer is missed. Therefore, we need a way to shorten the execution time of page table lookups.

In one embodiment, the present invention provides a microprocessor including a translation query buffer, a first requirement, hardware logic, and a second requirement. The first request loads a page table entry to the microprocessor in response to not finding a virtual address in the translation query buffer, the requested page table entry being included in a page table, the page table including a plurality of cache lines, The cache lines include a first cache line, and the first cache line includes the requested page table items. The hardware logic determines whether the entity is connected to a second cache line of the first cache line whether it is outside the page break table. The second requirement prefetches the second cache line to the microprocessor, and the second requirement is selectively generated based at least on the decision made by the hardware logic.

In another embodiment, the present invention provides a method comprising generating a first request to load a page table entry to a microprocessor in response to not finding a virtual address in a query buffer of one of the microprocessors The requested page table item is included in a page table, the page table includes a plurality of cache lines, the cache lines include a first cache line, and the first cache line includes the requested page table items; Determining whether the entity continues with a second cache line of the first cache line outside of the page break table; and selectively generating a second request based on the decision to prefetch the second cache line to the microprocessor.

In another embodiment, the present invention provides a computer program product for use in at least one non-transitory computer medium and for use in an computing device, the computer program product including computer code built into the media To confirm a microprocessor. The computer program code includes a first code for confirming a translation query buffer, and a second code for confirming a first request to load a page table item to a microprocessor in response to not being One of the microprocessors translates the query buffer to find a virtual address, and the requested page table entry is included in a page table, the page table includes a plurality of cache lines, and the cache lines include a first cache line. The first cache line includes the requested page table item; a third code is used to confirm a hardware logic, and the hardware logic determines whether the entity is connected to a second cache line of the first cache line in the page table. And a fourth code for confirming a second request to prefetch the second cache line to the microprocessor, the second requirement being selectively generated based at least on the decision.

The above and other objects, features, and advantages of the present invention will become more apparent and understood by the appended claims appended claims

100‧‧‧Microprocessor

102‧‧‧ instruction cache

104‧‧‧Instruction Translator

106‧‧‧Command Dispenser

108‧‧‧Loading unit

112‧‧‧Information cache

114‧‧‧ Busbar interface unit

116‧‧‧Translated query buffer

118‧‧‧Page Table Search Engine

122‧‧‧Prefetching unit

124‧‧‧First cache line

126‧‧‧Second Cache Line

128‧‧‧ physical memory

132‧‧‧virtual address

134‧‧‧ Lost signal

136‧‧‧Page Table Item Loading Request Signal

138‧‧‧Confirmation signal

142‧‧‧Prefetch request signal

144‧‧‧ physical address

396‧‧‧ final flag

396‧‧‧Page Table Project Entity Address

502‧‧‧Page Table Item Address

504‧‧‧ Cacheline Index

506‧‧‧page table address

508‧‧‧page table

1 is a block diagram of a microprocessor according to an embodiment of the present invention; FIG. 2 is a flowchart of operation of the microprocessor in FIG. 1; and FIG. 3 is a block diagram of a microprocessor according to an embodiment of the present invention; Figure Figure 4 is a flow chart of the operation of the microprocessor in Figure 3; Figure 5 is a block diagram of the paging table search engine forming the physical address of the page table item; Figure 6 is a page table table searching engine forming a page table Block diagram of the project entity address; Figures 7 through 10 are block diagrams of embodiments for determining whether the second cache line is outside the page break table; Figures 11 through 13 are micro-processes according to other embodiments Block diagram of the device.

In order to make the objects, features and advantages of the present invention more comprehensible, the specific embodiments of the invention are set forth in the accompanying drawings. The intention is to illustrate the spirit of the invention and not to limit the scope of the invention, it being understood that the following embodiments can be implemented by software, hardware, firmware, or any combination of the above.

Please refer to FIG. 1. FIG. 1 is a block diagram of a microprocessor 100 according to an embodiment of the present invention. The microprocessor 100 is a pipelined microprocessor. Microprocessor 100 includes an instruction cache 102 for providing a plurality of instructions to an instruction translator 104, and instruction translator 104 translates the received instructions and provides the translated instructions to an instruction dispatcher 106. . The instruction dispatcher 106 provides instructions to a load unit 108, wherein the instructions may include memory access instructions (eg, load instructions or store instructions). The load unit 108 provides the virtual address 132 specified by a memory access instruction to a translation query buffer 116, and the translation query buffer 116 looks up the virtual address 132. If the virtual address 132 appears in In the translation query buffer 116, the translation query buffer 116 transmits the translated physical address 144 of the virtual address 132 back to the loading unit 108. If the virtual address 132 does not appear in the translation query buffer 116, the translation query buffer 116 generates a miss signal 134 and transmits it to a page table engine 118. The page table search engine 118 is coupled to the load unit 108 and the translation query buffer 116.

As shown in FIG. 1 , the prefetch unit 122 and the data cache 112 are also coupled to the load unit 108 , and the bus interface unit 114 is coupled to the data cache 112 . The bus interface unit 114 couples the microprocessor 100 to a processor bus, and the processor bus is coupled to the physical memory 128 in the computer system having the microprocessor 100. Specifically, the physical memory 128 stores a plurality of page break tables, wherein a page break table includes a first cache line 124 located at one of the physical addresses P and a second cache line 126 located at one of the physical addresses P+64, and A cache line 124 and a second cache line 126 store eight page table items, respectively. In this embodiment, the size of one cache line is 64 bytes, and the size of one page table item is 8 bytes, so each cache line can store eight page table items.

Please refer to FIG. 2, which is a flowchart of the operation of the microprocessor 100 in FIG. 1 for explaining how to prefetch the next cache line, wherein the cache line and one load to the load unit Related to the pagination table item. The process begins in step 202.

In step 202, when the virtual address 132 does not appear in the translation query buffer 116, the translation query buffer 116 generates a missing signal 134 and transmits it to the page table search engine 118. The page table search engine 118 performs a page table lookup after receiving the lost signal 134 to obtain the missing in the translation query buffer 116. The physical address translated into the virtual address 132 in the medium. The page table search engine 118 performs a page table lookup action by generating a page table entry request signal (PTE load request) 136, wherein the page table table search engine 118 transmits the page table entry load request signal 136 to the load unit 108. Used to load the paging table items needed to perform address translation. Flow proceeds to step 204.

In step 204, the load unit 108 detects the page table entry load request signal 136 and loads the page table entry located in the entity memory 128. In addition, the loading unit 108 informs the prefetch unit 122 via a confirmation signal 138 that the page table entry request signal 136 has been spotted, and provides the physical address of the first cache line 124 to the translation query buffer 116. In the embodiment of FIG. 1, the physical address is P, and the first cache line 124 has a page table entry loaded by the loading unit 108. Flow proceeds to step 206.

In step 206, prefetch unit 122 generates a prefetch request signal 142 and transmits it to load unit 108. The prefetch request signal 142 commands the load unit 108 to prefetch the second cache line 126 located at the physical address P+64 to the data cache 112. In other words, the loading unit 108 prefetches the next cache line (second cache line 126) located after the first cache line 124 (having the page table entry loaded to the load unit 108) to the data cache 112. . Flow proceeds to step 208.

In step 208, the load unit 108 prefetches the next cache line (second cache line 126) to the data cache 112 based on the prefetch request signal 142. In some cases, however, the load unit 108 in the microprocessor 100 does not perform the act of loading the second cache line 126. For example, the above situation may be a functional requirement situation, such as a cache line falling in a non-cacheable memory region. The above situation can also be a microprocessor 100 is to perform non-speculative allocations. If the load unit 108 decides to load the second cache line 126 from the physical memory 128, the load unit 108 commands the bus interface unit 114 to perform this load action. The process ends at step 208.

Although the embodiment of the present invention describes prefetching the next cache line, in other embodiments, the prefetch unit 122 generates a request signal for instructing the load unit 108 to prefetch the last cache line, or the command load. The ingress unit 108 prefetches the next and previous cache lines. This embodiment is suitable for situations where the program travels in the other direction in the memory page.

In addition, although the embodiment of the present invention describes prefetching a cache line below the page table entry, in other embodiments, the prefetch unit 122 generates a request signal for instructing the load unit 108 to prefetch with other levels. (level) A cache line below the paging information hierarchy, such as Page Descriptor Entries (PDE). It's worth noting that although access patterns for some programs using this method are helpful, it is not common to place a large amount of physical memory under a single paged descriptor item, and the program is searched. The speed of the memory can become very slow, so the above methods are not only inefficient but also bring risks. In addition, in other embodiments, the prefetch unit 122 generates a request signal for instructing the loading unit 108 to prefetch another subpage table hierarchy (unlike the above-mentioned paging descriptor item/page table item hierarchy). Take the line.

As described above, the prefetch unit 122 generates a request signal for instructing the load unit 108 to prefetch the next cache line to the cache line having the page table entry that needs to complete the page table lookup. Suppose each page table is 4 kilobytes in size. Group (KB), the size of each page table item is octet, and the size of each cache line is 64 bytes, so there will be 64 caches with eight page table items in one page table. line. Therefore, it is highly probable that the next cache line in the next hop line has the next eight page table entries in the next page, in particular in the operating system, the paging table is configured as a physical continuous page table. in the case of.

In the case of small page breaks (usually 4 kilobytes), the program will eventually access several of the eight pages of memory, and these accessed pages have a high probability of exceeding The page accessed by the query buffer 116 is translated in step 202. In another embodiment, additional logic circuitry can be added to the prefetch unit 122 and the load unit 108 such that the prefetch unit 122 generates a request signal to command the load unit 108 to prefetch eight page table entries. The clock cycle required to perform a page table lookup to store eight memory pages to the translation query buffer 116 is greatly reduced, wherein the eight memory paged physical address locations are stored in eight page table entries. in. In particular, when the page table search engine 118 must perform a page table lookup (including loading any of the eight page table items located in the second cache line 126), the loaded page table items will be located. The data cache 112 (unless they are removed from the data cache 112 in sequence) will reduce the delay time required to read the physical memory 128 to obtain the page table entry.

The conventional prefetch mechanism is used to detect memory access patterns (ie, load instructions and store instructions) for program memory access. If the program detected by the prefetcher accesses the memory by the same way, the prefetcher expects to load the address of the instruction or the store instruction and perform the prefetch action from the address. If When the program accesses the memory sequentially, the prefetcher usually prefetches the next cache line based on the virtual address of the load instruction or the store instruction. In a processor architecture that performs paging page lookup in an operating system, a program load/store-based prefetcher based on a load instruction or a store instruction prefetches the next cache after loading the page table entry. line. However, in processors that perform paged table searches in hardware rather than software for load or store instructions, prefetchers based on load or store instructions do not trigger off the page table entry. The load action (because this is not a load instruction), and therefore does not prefetch the next cache line after loading the page table entry. Conversely, in the processor of the present invention that performs the paging table search in a hardware manner, the prefetch unit 122 may trigger an unprogrammed paging table item loading action, that is, triggered by the paging table search engine 118. Physical memory access action. Therefore, unlike the mechanism based on the load instruction or the store instruction, the prefetch unit 122 of the present invention instructs the load unit 108 to prefetch the next cache line, and the cache line may contain several of the page break tables. Pagination table item.

Selective prefetch

The paging table item prefetching mechanism described in Figures 1 and 2 has the advantage of reducing the paging table browsing time. As mentioned above, it is likely that the next prefetched entity cache line will contain the next few pagination table items in the pagination table. The possibility is particularly high when the operating system sets the paging table to be physically adjacent. The advantage of the above approach is that the translation query buffer is lost because there is a relatively high probability that the program may access at least some of the memory beyond the next few pages of the virtual access current page. However, if the operating system does not set the paging table to be physically adjacent, or at least not some of them, prefetch A cache line may result in a faster cache line from the cache memory hierarchy (evict) than the prefetch cache line. The following embodiments are related to this and improve the cache efficiency.

vocabulary

The page table entry (PTE) stores the physical page address of the physical memory and the attributes of the physical memory page. The paging table entry is included in the paging table of the memory paging mechanism of the microprocessor. The physical memory address of the paging table item essentially corresponds to the size of a paging table item. The page table entry is 4 bytes in some embodiments, and the page table entry is 8 bytes in other examples, but other embodiments are also contemplated for use in the present invention.

A page table is a set of contiguous page table items on a solid basis. The physical memory address of the paging table essentially corresponds to the address boundary, and the address boundary is the size of the paging table. In one embodiment, for example, the page break table is a 4K byte, and the page break table includes 1024 4-bit page break table entries, or 512 8-bit page break table entries. However, other embodiments have considered paging tables of different sizes. Each page table entry in the pagination table has an index that determines a portion of the bits from the virtual address to be translated. For example, in the case of a 4K-bit component page table and a 4-bit component page table entry, bits 21:12 of the virtual address calibrate the items of the page table entry to the page table. In another embodiment, in the case of a 4K-bit component page table and an 8-bit component page table entry, bits 20:12 of the virtual address calibrate the items of the page table entry to the page table.

The paging table includes a plurality of cache lines whose physical addresses essentially correspond to the size of a cache line. In one embodiment, the size of the cache line is 64 bytes, but other embodiments are contemplated for use in the present invention. Because the cache line is large For paged table items, each cache line includes multiple page table items. Each cache line included in the paging table has an index that determines a portion of the bits from the virtual address to be translated. For example, in the case of a 4K-bit component page table and a 64-bit component page table entry, bits 21:16 of the virtual address calibrate the index of the cache line among the page break tables.

The last cache line of the page break table is the cache line with the largest index among the cache lines contained in the page break table. For example, in the case of a 4K-bit component page table and a 64-bit group cache line and a 4-bit component page table entry, the index of the last cache line of the page table (bit 21:16 of the virtual address) ) is 0x3F (or binary 111111). In another embodiment, in the case of a 4K-bit component page table and a 64-bit group cache line and an 8-bit component page table entry, the index of the last cache line of the page table (bits of the virtual address) 20:15) is 0x3F (or binary 111111).

Reference is now made to the schematic diagram of the microprocessor 100 shown in FIG. The microprocessor 100 of Figure 3 is similar in many respects to the microprocessor 100 of Figure 1. If not specifically indicated, similarly labeled elements are similar. The difference between Fig. 1 and Fig. 3 is that the load unit 308, the page table search engine 318, and the page table entry load request 336 are modified (therefore, the above correction has a different label than the first figure). In detail, the PTE load request 336 includes a final flag 396 in addition to the requested page table entry address 398 (located within the physical address P, the cache line). In addition, the page table search engine 318 then determines if the cache line containing the page table entry is the last cache line that contains the page table entry and fills in the page table of the last flag 396. Finally, the load unit 308 checks the last flag 396 to determine whether to provide the physical address 138 of the cache line to the prefetch unit 122. More details will be described in Figures 4 through 8.

Reference is now made to the flowchart of the microprocessor 100 of Fig. 3, which is shown in Fig. 4. The flowchart begins at step 402.

In step 402, when the virtual address 132 is not found in the translation query buffer 116, the translation query buffer 116 generates a missing signal 134 to the page table search engine 318, and the page table search engine 318 performs a page table search to obtain a translation. The physical address translation of the virtual address 132 not found in the buffer 116 is queried. The page table lookup includes a page table lookup engine 318 to determine the physical address of the page table entry for which address translation needs to be performed. The paging table lookup may include accessing other structures of the paging mechanism of the microprocessor 100 to determine the physical address of the paging table entry. For example, in an embodiment of the x86 architecture, the paging table is based on the 32-bit, PAE, or IA-32e page mode of the microprocessor 100 to search for access to PML4 projects (PML4E), PDPT projects (PDPTE), And/or page directory entry (PDE). All or part of these structures may be cached in a cache structure of the microprocessor 100 having a paging mechanism, such as a PML4 cache, a PDPTE cache or a PDE cache, or a microprocessor including a data cache 112. The cache of the device 100 is among various levels of the memory. Other embodiments include other processor architectures with virtual memory capabilities, as well as other processor architectures that implement paging table lookups and other split architectures in their memory paging mechanisms, such as SPARC architecture, ARM architecture, PowerPC architecture, and other conventional processing. The architecture can also be used in the present invention. The flow proceeds to step 404.

At step 404, the page table search engine 318 determines whether the cache line (first cache line) including the page table entry of step 402 is the last cache line in the page table including the page table entry. This means that the second cache line entity is connected to the first cache line (that is, the second cache line has a physical address equal to the first cache line). The physical address that is incremented by the cache line size). Preferably, the page lookup engine 318 detects the predetermined bits of the virtual address 132 not found by the translation query buffer 116 in step 402 to make a decision. Details of the operation of step 404 will be described in Figures 5 and 6. Flow proceeds to decision step 406.

In decision step 406, if the decision of step 404 is true, the flow proceeds to step 408; otherwise, the flow proceeds to step 412.

In decision 408, the page table search engine 318 sets the last flag 396 of the request 336 generated by step 414 to be true. The flow proceeds to step 414.

In step 412, the page table search engine 318 sets the last flag 396 of the request 336 generated by step 414 to be false. The flow proceeds to step 414.

In step 414, the page table search engine 318 generates a request 336 to load the page table entry and transfer the request 336 to the load unit 308, the physical address of which is determined in step 402. Requirement 336 includes the value of the last flag 396 generated by step 408 or step 412. When the page table entry is subsequently obtained, the page table search engine 318 uses the page table entry to translate the virtual address 132 and updates the translation query buffer 116 with the physical address translated by the virtual address 132 to complete the page table lookup. Flow proceeds to decision step 416.

In decision step 416, the load unit 308 determines if the last flag 396 is true. If so, the flow proceeds to step 418; otherwise, the flow proceeds to step 422.

At step 418, the load unit 308 does not provide the physical address 138 of the first cache line to the prefetch unit 122, and the flow ends.

At step 422, the load unit 308 provides the physical address 138 of the first cache line to the prefetch unit 122. The flow proceeds to step 424.

At step 424, prefetch unit 122 increments the physical address of first cache line 138 by the size of the cache line (e.g., 64 bytes) and transmits request 142 to load unit 308 to prefetch in incremented address. Two quick lines. The flow proceeds to step 426.

At step 426, the load unit 308 uses the prefetch request 142 as an indication to prefetch the second cache line to the microprocessor 100. The process ends at step 426.

Referring now to the block diagram shown in FIG. 5, the paged table entry address 502 formed by the page lookup engine 318 is illustrated. The paging table item address 502 is a physical address. In the embodiment of generating the paging table entry address 502 described in FIG. 5, the size of the paging table entry is 4 bytes, and the paging table is 4K bytes. Figure 5 also shows the bits of the page table entry address 502, and the page break table entry address 502 constitutes the index 504 of the cache line included in the page break table 508 of the page break table entry for the page break table entry. The paging table entry address 401 is formed by the microprocessor 100 architecture.

The page table search engine 318 forms a page table entry address 502 from the virtual address 132 and the page table address 506. In other words, the PDE includes a pointer to the pager table 508, that is, the physical memory address of the paged table 508 as shown. In general, the pagination table address 506 is obtained from a page roster item (PDE), however in some paging modes (eg, only a first order pagination structure), the pagination table item address 502 can be obtained directly from the microprocessor 100. The scratchpad (such as the CR3 scratchpad in the x86 architecture).

In the embodiment shown in FIG. 5, since the page table item is a 4-byte group and the 4-bit group is used, the value of the lower two bits is filled with 0. Virtual The bit [21:12] of the pseudo address 132 becomes the bit [11:2] of the paging table item address 502, and the bit [N:12] of the paging table address 506 forms the paging table item address 502. Bits [N:12], where N is the most significant bit of the page table address 506 and the page table entry address 502 (eg, 31 bits in a 32-bit entity address, 36-bit entity address) 35 bits, 39 bits in a 40-bit entity address). The pagination table item address 502 points to the pagination table item in the pagination table 508, which is the physical memory address of the pagination table item, as shown. In the embodiment of Figure 5, the page break table entry address 502 points to the page break table entry 13 in the cache line of the 16 page table entries.

As shown, cache line index 504 is a bit [11:6] of paged table entry address 502, corresponding to bit [21:16] of virtual address 132. Thus, the cache line index 504 can be determined from the virtual address 132 or the formed page table entry address 502 (i.e., by the load unit 1108 of the embodiment of FIG. 11). In the embodiment of FIG. 5, the cache line index 504 of the cache line contains the page table entry pointed to by the page break table entry address 502, and the value of the cache line index 504 is 0x3C. As described above, because the page break table 508 contains 64 cache lines (i.e., in the embodiment where the cache line is 64 bytes and the page break table is 4K bytes), the largest cache line index 504 is 0x3F.

Referring now to the block diagram shown in FIG. 6, the paged table entry address 502 formed by the page lookup engine 318 is illustrated. In one embodiment, the page break table entry is an 8-bit tuple (not a 4-byte tuple as shown in FIG. 5). Figure 6 is similar to Figure 5 except as described below. First, since the paging table entry in the embodiment is an 8-bit group and is based on an 8-bit group, the value of the lower 3 bits is filled with 0 (instead of the lower 2 shown in FIG. 5). One bit). Furthermore, the bits [20:12] of the virtual address 132 become the bits [11:3] of the page table entry address 502 (instead of Figure 5). The bit [21:12] of the virtual address 132 shown becomes the bit [11:2] of the page table entry address 502. In the embodiment shown in FIG. 6, the page table entry address 502 points to the page table entry 5 in the cache line of the eight page table entries (rather than to the 16 page table entries shown in FIG. 5). Take the line). As described above, the cache line index 504 is the bit [11:6] of the page table entry address 502, corresponding to the bit [20:15] of the virtual address 132 of the embodiment of FIG. 6 (instead of the fifth Figure bit [21:16]). In the embodiment of FIG. 5, the cache line index 504 of the cache line contains the page table entry pointed to by the page break table entry address 502, and the value of the cache line index 504 is 0x04.

Referring now to Figure 7, the block diagram shows the decision to determine the second cache line (i.e., the cache line of the contiguous cache line (the first cache line) and includes the requirements for the translation buffer not found. The paging table entry) is a first embodiment other than the paging table 508, such as the paging table search engine 318 by step 404 of FIG. The above decision is made by examining the cache line index 504 of the first cache line and comparing whether it is equal to the value of the maximum cache line index 504 (eg, 0x3F), that is, the last cache line included in the page table 508. Cache line index 504. In detail, if the first cache line is the last cache line included in the page break table 508 (that is, at the end of the page break table 508), then the entity succeeds the cache line (the second cache line) in the page break table. Outside 508. If the cache line index 504 of the first cache line is equal to the maximum cache line index value, the decision is true, that is, the second cache line is outside the page break table 508. Otherwise, this decision is false.

In the embodiment of Figure 7, virtual address 132 has a value of 0x12345678. As a result, 0x34 is the bit [21:16] of the virtual address 132, which is the bit [11:6] of the page table entry address 502, and is the first cache line index 504. Therefore, since the value 0x34 of the first cache line index 504 is less than the highest cache The value of line index 504 is 0x3F, this decision is false, and the last flag 396 is set to false. As described above, the second cache line is included in the page break table 508, not outside the page break table 508.

Referring now to Figure 8, a block diagram showing a second embodiment of determining whether the second cache line is outside of the page break table 508. Figure 8 is similar to Figure 7, except that the value of virtual address 132 is different. In the embodiment of Figure 8, virtual address 132 has a value of 0x123F5678. As a result, 0x34 is the bit [21:16] of the virtual address 132, which is the bit [11:6] of the page table entry address 502, and is the first cache line index 504. Thus, since the value 0x3F of the first cache line index 504 is equal to the value 0x3F of the highest cache line index 504, this decision is true and the last flag 396 is set to true. As noted above, the second cache line is outside of the page break table 508 and is not included in the page break table 508. As a result, the second cache line may or may not include the cache line of the page table entry. Even if it contains, it may not include the pagination table item of the pagination table, which is the next pagination table pointed to by the next PDE in the pagination structure. Thus, the embodiments described herein selectively prefetch the second cache line, which has the advantage of reducing the pollution of the cache hierarchy of the microprocessor 100 described above.

Referring now to Figure 9, a block diagram shows a third embodiment of the formation decision. Fig. 9 is similar to Fig. 7, except that in the embodiment of Fig. 9, an 8-byte page table entry is used, so each cache line includes only 8 page table items. As shown in FIG. 7, the above decision is made by examining the cache line index 504 of the first cache line and comparing whether it is equal to the value of the maximum cache line index 504 (for example, 0x3F), that is, the page table 508. The cache line index 504 of the last cache line included. However, in Figure 9, the formation decision is made by examining the virtual address 132. Bits [20:15] (instead of bits [21:16] of virtual address 132 in Figure 7), which in both cases are the bits of the page table entry address 502 [11:6] ].

In the embodiment of Figure 9, virtual address 132 has a value of 0x12345678. Thus, 0x28 is the bit [20:15] of the virtual address 132, which is the bit [11:6] of the page table entry address 502, and is the first cache line index 504. Therefore, since the value 0x28 of the first cache line index 504 is less than the value 0x3F of the highest cache line index 504, this decision is false, and the last flag 396 is set to false. As described above, the second cache line is included in the page break table 508, not outside the page break table 508.

Referring now to Figure 10, a block diagram shows a fourth embodiment for determining whether the second cache line is outside of the page break table 508. Figure 10 is similar to Figure 9, except that the value of virtual address 132 is different. In the embodiment of FIG. 10, virtual address 132 has a value of 0x123FD678. Thus, 0x3F is the bit [20:15] of the virtual address 132, which is the bit [11:6] of the page table entry address 502, and is the first cache line index 504. Thus, since the value 0x3F of the first cache line index 504 is equal to the value 0x3F of the highest cache line index 504, this decision is true and the last flag 396 is set to true. As noted above, the second cache line is outside of the page break table 508 and is not included in the page break table 508. As a result, the embodiments described herein selectively prefetch the second cache line, which has the advantage of reducing contamination of the cache hierarchy of the microprocessor 100 described above.

It should be understood that although Figures 7 through 10 depict the formation of a decision regarding the embodiment of step 404 of Figure 4 (i.e., by paging table search engine 318 and setting the final flag 396), the above decision is also made. It can be formed by other units of the microprocessor 100 (e.g., by the loading unit 1108 of the embodiment of Fig. 11), And in some embodiments the final flag 396 (i.e., the embodiment of Figures 11 through 13) is not used. Preferably, the decision is made by hardware logic, such as combinatorial logic in the associated unit, such as the paging table search engine 318/1218/1318, or the appropriate bit of the virtual address 132. The entry unit 1108 is either a paged table entry address 502 having a predetermined maximum cache line index value.

Referring now to Figure 11, a block diagram of another embodiment of a microprocessor 100 is shown. The microprocessor 100 of Figure 11 is similar in many respects to the microprocessor 100 of Figure 1. Like referenced elements are similar unless specifically indicated. The difference between FIG. 11 and FIG. 1 is that the loading unit 1108 is modified. The load unit 1108 of FIG. 11 is modified to include hardware logic to determine if the second cache line is outside of the page break table 508. Thus, in the embodiment of FIG. 11, the pagination table item load request 136 does not include the last flag 396. The operation of the microprocessor 100 of FIG. 11 is similar to that described in FIG. 4 except that the paging table search engine 118 does not make a decision (eg, step 404), but instead is determined by the loading unit 1108 (similar to step 416). It is decided that after the page table search engine 118 described in step 414 transmits the page table entry request 136), and if the decision is true, the entity address 138 of the first cache line is not provided to the cache unit 122.

Referring now to Figure 12, a block diagram of another embodiment of a microprocessor 100 is shown. The microprocessor 100 of Fig. 12 is similar in many respects to the microprocessor 100 of Fig. 11. Like referenced elements are similar unless specifically indicated. The difference between FIG. 12 and FIG. 11 is that the paging table search engine 1218, the loading unit 1208, and the prefetch unit 1222 are modified. The load unit 1208 of FIG. 12 is modified to not provide the physical address 138 of the first cache line to the prefetch unit 122. If decided to Falsely, the page table lookup engine 1218 forms a decision and generates a physical address 1238 to the prefetch unit 1222 that directly provides the first cache line. The operation of the microprocessor 100 of Fig. 12 is similar to that described in Fig. 4 except that if the decision in step 406 is true, the flow proceeds to step 418 (prefetching of the second cache line is not performed). If the decision is false, the flow proceeds to step 414 and then directly to the modified step 422, the page table search engine 1218 provides the entity address 1238 of the first cache line to the prefetch unit 1222.

Referring now to Figure 13, a block diagram of another embodiment of a microprocessor 100 is shown. The microprocessor 100 of Figure 13 is similar in many respects to the microprocessor 100 of Figure 12. Like referenced elements are similar unless specifically indicated. The difference between the 13th and 12th figures is that the paging table search engine 1318 and the prefetch unit 1322 are modified. The page table search engine 1318 of FIG. 13 increments the physical address of the first cache line to generate the physical address 1338 of the second cache line (rather than being executed by the prefetch unit 1322), and if the decision is false, It is provided to the prefetch unit 1322. The operation of the microprocessor 100 of Fig. 13 is similar to that of Fig. 4 except that if the decision in step 406 is true, the flow proceeds to step 418 (prefetching of the second cache line is not performed). If the decision is false, the flow proceeds to step 414 and then directly to the modified step 422, the page table search engine 1218 provides the physical address 1338 of the first cache line to the prefetch unit 1222. Then, in a modified step 424, the prefetch unit 1322 does not need to perform an increment, but instead uses the received physical address 1338 of the second cache line in its request 142 to the load unit 1208.

In another embodiment (not shown), the load unit receives a page table entry load request from the page table lookup engine, calculates a physical address of the second cache line, and generates a prefetch for the second cache line Claim. In this embodiment, the prefetch order The yuan can be non-existent.

Although the embodiments have described the general vocabulary of x86 architecture processors used by the memory paging mechanism, it should be understood that the above embodiments include other processor architectures that include virtual memory capabilities and use paging tables in memory page mechanisms, such as SPARC architecture. , ARM architecture, PowerPC architecture, and other conventional processor architectures.

Furthermore, although the embodiment has described that the second cache line is the cache line of the next entity connection, and by determining whether the first cache line is at the end of the page table, it is determined whether the second cache line is in the page table. In addition, other embodiments may also be that the second cache line is a cache line connected by the previous entity, and is determined by determining whether the first cache line is at the beginning of the page break table, and includes multiple memory The page executes the program in other directions.

The present invention has been described in terms of various embodiments, which are intended to be illustrative only and not to limit the scope of the present invention, and those skilled in the art can make a few changes without departing from the spirit and scope of the invention. With retouching. For example, software may be used to implement the functions, construction, modules, simulations, descriptions, and/or tests of the devices and methods described herein. This can be achieved by using a general programming language (eg C, C++), a hardware description language (including Verilog or VHDL hardware description language, etc.), or other available programs. The software can be placed in any computer-usable medium such as a semiconductor, a disk, a compact disc (such as a CD-ROM, a DVD-ROM, etc.). The apparatus and method described in the embodiments of the present invention may be included in a semiconductor intellectual property core, such as a microprocessor core implemented in a hardware description language (HDL), and converted into a hardware. Type integrated circuit products. Further, the present invention The devices and methods described can be implemented by combining hardware and software. Therefore, the present invention should not be limited by any of the embodiments herein, and the scope of the appended claims and their equivalents. In particular, the present invention is embodied in a microprocessor device for a general purpose computer. In the final analysis, the scope of the present invention is defined by the scope of the appended claims.

Claims (21)

A microprocessor comprising: a translation query buffer; a first request to load a page table entry to the microprocessor in response to not finding a virtual address in the translation query buffer, the requested page break The table item is included in a page table, the page table includes a plurality of cache lines, the cache line includes a first cache line, the first cache line includes the requested page table item; hardware logic Determining whether a second cache line of the first cache line is outside the page table; a second request prefetching the second cache line to the microprocessor, the second requirement being at least Selectively generated based on the decision made by the hardware logic; determining whether the second cache line is outside the page table, the hardware logic determining whether the first cache line is the last included in the page table a cache line; and determining whether the first cache line is the last cache line included in the page table, and the hardware logic determines whether the value of the plurality of predetermined bits of the virtual address is one. The microprocessor of claim 1, further comprising: the predetermined bit of the virtual address being a higher M bit of N bits and determining the page table entry in the page table An index, where NM is the logarithm (log2) of the byte size of the page table entry. The microprocessor of claim 1, further comprising: when the decision is false, generating the second request; and when the decision is true, the second request is not generated. The microprocessor of claim 1, further comprising: a load unit; and a page table search engine that generates the first request to the load unit. The microprocessor of claim 4, further comprising: the first requirement includes a flag, the flag including a decision made by the paging table search engine; a prefetch unit; if the flag indicates The decision is false, the loading unit provides the physical address of the first cache line to the prefetch unit; and the prefetch unit generates the second request in response to the first received from the loading unit The physical address of a cache line. The microprocessor of claim 4, further comprising: the loading unit making the decision; a prefetching unit; if the decision is false, the loading unit provides the entity of the first cache line Addressing the prefetch unit; and the prefetch unit generates the second request in response to the physical address of the first cache line received from the load unit. The microprocessor of claim 4, further comprising: the paging table search engine making the decision; a prefetching unit; if the decision is false, the paging table searching engine provides the first cache line The physical address is addressed to the prefetch unit; and the prefetch unit generates the second request in response to the paging table search engine The physical address of the first cache line received. The microprocessor of claim 4, further comprising: the paging table search engine making the decision; a prefetching unit; if the decision is false, the paging table searching engine provides the second cache line The entity address is addressed to the prefetch unit; and the prefetch unit generates the second request in response to the physical address of the second cache line received by the paging table search engine. The microprocessor of claim 4, further comprising: the loading unit making the decision; and if the decision is false, the loading unit generates the second request. The microprocessor of claim 1, further comprising: a cache memory; and the second requirement includes a request to prefetch the second cache line to the cache memory. A method comprising: generating a first request to load a page table entry to a microprocessor in response to finding a virtual address in a query buffer not translated in the microprocessor, the requested page table The item is included in a page table, the page table includes a plurality of cache lines, the cache line includes a first cache line, the first cache line includes the requested page table item; Whether a second cache line of the first cache line is outside the page table; at least based on the decision, selectively generating a second request to prefetch the second fast Taking a line to the microprocessor; determining whether the second cache line is outside the page table includes determining whether the first cache line is the last cache line included in the page table; and determining the first cache Whether the line is the last cache line included in the page table includes whether the value of the plurality of predetermined bits determining the virtual address is one. The method of claim 11, further comprising: the predetermined bit of the virtual address being a higher M bit of N bits and determining an index of the page table entry in the page table , where NM is the logarithm (log2) of the byte size of the page table entry. The method of claim 11, further comprising: selectively generating the second requirement comprises: generating the second request when the decision is false; and not generating the second when the decision is true Claim. The method of claim 11, further comprising: the paging table search engine of the microprocessor generating the first request to one of the microprocessor loading units. The method of claim 11, further comprising: the first requirement includes a flag to indicate the decision made by the paging table search engine; if the flag indicates that the decision is false, the loading unit Providing the physical address of the first cache line to a prefetch unit of the microprocessor; and the prefetch unit generates the second request in response to the first cache line received from the load unit The physical address of the entity. For example, the method described in claim 14 of the patent scope further includes: The loading unit makes the decision; if the decision is false, the loading unit provides the physical address of the first cache line to one of the prefetch units of the microprocessor; and the prefetch unit generates the second Requiring to respond to the physical address of the first cache line received from the loading unit. The method of claim 14, further comprising: the paging table search engine making the decision; if the decision is false, the paging table search engine provides the physical address of the first cache line to the micro a prefetch unit of the processor; and the prefetch unit generates the second request in response to the physical address of the first cache line received by the paging table search engine. The method of claim 14, further comprising: the paging table search engine making the decision; if the decision is false, the paging table search engine provides the physical address of the second cache line to the micro a prefetch unit of the processor; and the prefetch unit generates the second request in response to the physical address of the second cache line received by the paging table search engine. The method of claim 14, further comprising: the loading unit making the decision; and if the decision is false, the loading unit generates the second request. The method of claim 11, further comprising: the second requirement comprising a request to prefetch the second cache line to one of the microprocessor cache memories. One encoded in at least one non-transitory computer medium and A computer program product for use in an arithmetic device, the computer program product comprising: a computer program code built into the media for confirming a microprocessor, the computer program code comprising: a first code for confirming Translating a query buffer; a second code for confirming a first request to load a page table entry to a microprocessor in response to not finding a dummy bit in a translation buffer of one of the microprocessors Address, the requested page table item is included in a page table, the page table includes a plurality of cache lines, the cache line includes a first cache line, and the first cache line includes the requested line a page table item; a third code for confirming a hardware logic, the hardware logic determining whether a second cache line connecting the first cache line is outside the page table; and a fourth a code for confirming a second request to prefetch the second cache line to the microprocessor, the second request being selectively generated based at least on the determining, determining whether the second cache line is in the Outside the pagination table includes the decision of the first Whether the line fetch is the last cache line included in the page table; and determining whether the first cache line is the last cache line included in the page table includes determining whether the value of the plurality of predetermined bits of the virtual address is All are one.