TWI587624B - Front-end amplifier circuit - Google Patents

Description

Front end amplifier circuit

The present invention relates to a front-end amplifier circuit suitable for use in the field of biomedical electronics, and more particularly to a current mode front-end amplifier circuit suitable for use in the field of biomedical electronics.

When detecting EEG signals in the field of biomedical electronics, the front-end amplifier circuit has a pivotal role. Because of the low frequency and low amplitude of the physiological signal, a front-end circuit that properly amplifies the physiological signal must have low noise and high frequency. Magnification. In addition to this, the power consumption needs to be as small as possible for long-term measurement on a wearable device.

In view of this, the present invention provides a front end amplifier circuit for receiving a biosignal, including: a signal path. The signal channel amplifies the biosignal to generate a detection current. The signal path includes a capacitively coupled transconductance amplifier. The capacitive coupling transduction amplifier amplifies the biological signal by a transduction gain and outputs a first current.

According to an embodiment of the invention, the capacitive coupling transduction amplifier comprises: a first input capacitor, a second input capacitor, a first common mode P-type transistor, a second common mode P-type transistor, and a first a current source, a second current source, a first transmissive P-type transistor, a second transmissive P-type transistor, a linear resistor, a third transconductance P-type transistor, and a fourth transconductance P Type transistor, a first turn An N-type transistor, a second transmissive N-type transistor, a third transconductance N-type transistor, and a fourth transconductance N-type transistor. The first input capacitor is coupled between an input negative terminal and a first node. The second input capacitor is coupled between an input positive terminal and a second node, wherein the first input capacitor and the second input capacitor ac-couple the biosignal in a differential mode. The first common mode P-type transistor is configured to provide a common mode voltage to the first node. The second common mode P-type transistor is configured to provide the common mode voltage to the second node. The first current source is configured to provide a first transducing bias current. The second current source is configured to provide a second transducing bias current. The source terminal of the first transducing P-type transistor receives the first transducing bias current, and the gate terminal is coupled to the second node. The source terminal of the second transducing P-type transistor receives the second transducing bias current, and the gate terminal is coupled to the first node, wherein the first transducing P-type transistor and the second transducing P-type A transistor is used to generate the above-described transduction gain. The linear resistor is coupled between the source terminal of the first transducing P-type transistor and the source terminal of the second transducing P-type transistor, wherein the linear resistor is used to increase linearity of the transduction gain. The source terminal of the third transduction P-type transistor is coupled to the first terminal of the first transmissive P-type transistor, and the gate terminal is coupled to a transconductance bias voltage. The source terminal of the fourth transducing P-type transistor is coupled to the 汲 terminal of the second transmissive P-type transistor, the gate terminal is coupled to the transimpedance bias voltage, and the 汲 terminal is coupled to a transconductance output terminal. The transduction output terminal outputs the first current. The 汲 terminal and the gate terminal of the first transducing N-type transistor are coupled to the 汲 terminal of the third transducing P-type transistor. The second transducing N-type transistor is coupled to the transduction output terminal, and the gate terminal is coupled to the gate terminal of the first transducing N-type transistor. The third transduction N-type transistor The extreme terminal and the gate terminal are all coupled to the source terminal of the first transduction N-type transistor, and the source terminal is coupled to a ground terminal. The 转 terminal of the fourth transduction N-type transistor is extremely coupled to the source terminal of the second transduction N-type transistor, and the gate terminal is coupled to the gate terminal of the third transduction N-type transistor, and the source terminal is coupled To the above ground terminal.

According to an embodiment of the invention, the signal channel further includes: a band pass filter amplifier, an adjustable gain amplifier, and an offset cancellation circuit. The band pass filter amplifier filters the first current out of noise outside the frequency band and amplifies a first current gain, and outputs a second current. The adjustable gain amplifier amplifies the second current to a second current gain and outputs the detected current at an adjusted gain output, wherein the second current gain is adjustable. The offset cancellation circuit is configured to eliminate the output offset current of the capacitive coupling transduction amplifier, the band pass filter amplifier, and the adjustable gain amplifier.

According to an embodiment of the invention, the front end amplifier circuit further includes a transimpedance amplifier. The transimpedance amplifier is configured to convert the detection current into a voltage signal via a resistance gain, and provide a driving capability to the coupling measurement system, wherein the magnification of the biological signal to the voltage signal is The product of the transconductance gain, the first current gain, the second current gain, and the transimpedance gain.

According to an embodiment of the invention, the band pass filter amplifier includes a band pass main current path, a band pass filter, and a band pass sub current path. The bandpass main current path has a bandpass main bias current and is configured to receive the first current. The band pass filter is AC coupled to the band pass main current path, and the first current is filtered to remove noise outside the frequency band to generate a filter. signal. The band pass sub current path has a band pass sub-bias current and generates the second current according to the filtered signal, wherein the first current gain is a ratio of the band pass sub-bias current to the band pass main bias current .

According to an embodiment of the invention, the band pass main current path includes: a first main P type transistor, a second main P type transistor, a first main N type transistor, and a second main N type electric Crystal. The source terminal of the first main P-type transistor is coupled to a supply voltage, and the gate terminal is coupled to the 汲 terminal. The source terminal of the second main P-type transistor is coupled to the 汲 terminal of the first main P-type transistor, and the gate terminal and the 汲 terminal receive the first current. The gate terminal and the 汲 terminal of the first main N-type transistor are coupled to the 汲 terminal of the first main P-type transistor. The gate terminal and the drain terminal of the second main N-type transistor are coupled to the source terminal of the first main N-type transistor, and the source terminal is coupled to the ground terminal.

According to an embodiment of the invention, the first main P-type transistor, the second main P-type transistor, the first main N-type transistor, and the second main N-type electro-crystal system are all operated in a sub-critical ( Sub-threshold) area to reduce power loss.

According to an embodiment of the invention, the band pass sub current path includes: a first sub P type transistor, a second sub P type transistor, a first sub N type transistor, and a second sub N type electric Crystal. The source terminal of the first sub-P-type transistor is coupled to the supply voltage, and the gate terminal is coupled to the 汲 terminal. The source terminal of the second sub-P-type transistor is coupled to the 汲 terminal of the first sub-P-type transistor, and the 汲 terminal is coupled to a band-pass output terminal. The gate terminal of the first sub-N-type transistor is coupled to the gate terminal of the second sub-P-type transistor, and the 汲 terminal is coupled to the band-pass output terminal, wherein the gate terminal of the first sub-N-type transistor receives Filter letter No. The above band pass output terminal outputs the second current. The gate terminal of the second sub-N-type transistor and the 汲 terminal are coupled to the source terminal of the first sub-N-type transistor, and the source terminal is coupled to the ground terminal, wherein the size of the transistor of the band-pass sub-current path The ratio of the size of the transistor to the bandpass main current path is the first current gain described above.

According to an embodiment of the present invention, the first sub-P-type transistor, the second sub-P-type transistor, the first sub-N-type transistor, and the second sub-N-type electro-crystal system are all operated in a subcritical region To reduce power loss.

According to an embodiment of the invention, the band pass filter includes: a first differential input amplifier, a first coupling capacitor, a first bias P-type transistor, a low-pass capacitor, and a second differential input. An amplifier, a third differential input amplifier, a second coupling capacitor, and a second bias P-type transistor. The first differential input amplifier is configured to generate a transfer conductance, and includes a first negative input terminal, a first positive input terminal, and a first output terminal, wherein the first negative input terminal is coupled to the first output terminal end. The first coupling capacitor is coupled between the gate terminal of the second main P-type transistor and the first positive input terminal. The first bias P-type transistor has a channel resistance, the source terminal is coupled to the common mode voltage, and the drain terminal is coupled to the first positive input terminal, and the gate terminal is coupled to a first band pass bias voltage. The low-pass capacitor is coupled between the first output end and the ground end. The second differential input amplifier includes a second negative input terminal, a second positive input terminal, and a second output terminal, wherein the second negative input terminal is coupled to the second output terminal, and the second positive input terminal The first output end is coupled to the first output end. The third differential input amplifier includes a third negative input terminal, a third positive input terminal, and a third output terminal, wherein the third negative input terminal is coupled to the above The third output end outputs the filtered signal. The second coupling capacitor is coupled between the second output terminal and the third positive input terminal for isolating the second differential input amplifier and the third differential input amplifier. The second bias P-type transistor is configured to provide a DC bias voltage to the third positive input terminal, such that the gate terminal of the second sub-P-type transistor and the gate of the first sub-N-type transistor are extremely biased Pressed to the above DC bias.

According to an embodiment of the invention, the frequency bandwidth includes a low pass cutoff frequency and a high pass cutoff frequency, wherein the transfer conductance and the low pass capacitance determine the low pass cutoff frequency, wherein the first coupling capacitor and the channel resistance determine The above high pass cutoff frequency.

According to another embodiment of the present invention, the first bias P-type electro-emissive system operates in a cut-off region such that the channel resistance is high impedance.

According to an embodiment of the invention, the offset cancellation circuit includes: a digital controller, a virtual resistance reset module, an offset detection circuit, a first current digital analog converter, and a second current digital analogy. A converter, a third current digital analog converter, and a register. The digital controller generates a first reset signal, a second reset signal, and a selection signal. The virtual resistance reset module shorts the first node and the second node to the common mode voltage according to the first reset signal, and shorts the first positive input terminal to the total according to the second reset signal The mode voltage and shorting the third positive input terminal to the DC bias voltage. The offset detecting circuit sequentially detects the first current, the second current, and the detecting current according to the selection signal, and generates a first compensation current code, a second compensation current code, and a third compensation. Current code. The first current digital analog converter is configured according to the first compensation described above The current code extracts or provides a first compensation current to the transduction output. The second current digital analog converter extracts or supplies a second compensation current to the band pass output according to the second compensation current code. The third current digital analog conversion, according to the third compensation current code, extracts or provides a third compensation current to the adjusted gain output. The register is configured to store the first compensation current code, the second compensation current code, and the third compensation current code.

According to an embodiment of the invention, the signal channel further includes: a first switch and a second switch. The first switch is coupled between the capacitive coupling transduction amplifier and the band pass filter amplifier, and is not turned on according to the first open circuit signal of one of the digital controllers. The second switch is coupled between the band pass filter amplifier and the adjustable gain amplifier, and is not turned on according to the second open signal of one of the digital controllers.

According to an embodiment of the present invention, when the first switch and the second switch are not turned on, the offset detecting circuit generates the first compensation current code according to the selection signal to detect the first current; When the first switch is turned on and the second switch is not turned on, the first current digital analog converter extracts or supplies the first compensation current to the transduction output end, and the offset detecting circuit detects the above according to the selection signal. The second current generates the second compensation current code; when the first switch and the second switch are both turned on, the first current digital analog converter extracts or supplies the first compensation current to the transduction output end, The second current digital analog converter extracts or supplies the second compensation current to the band-pass output terminal, and the offset detecting circuit detects the detection current according to the selection signal to generate the third compensation current code.

According to an embodiment of the invention, the offset detecting circuit further includes: a sampling amplifier, a selection switch, and a comparator. The sampling amplifier is used to convert an input current into a comparison voltage. The selection switch sequentially selects one of the first current, the second current, and the detected current as the input current according to the selection signal. The comparator compares the comparison voltage and a reference voltage to generate an output signal, wherein the digital controller determines the first compensation current code, the second compensation current code, and the third compensation current code according to the output signal.

According to an embodiment of the invention, the front end amplifier circuit further includes: another signal path and a multiplexer. The other signal channel receives and amplifies another biosignal to generate another detected current. The multiplexer supplies one of the detected current and the other detected current to the transimpedance amplifier.

100, 200‧‧‧ front-end amplifier circuit

110, 210_1~210_N‧‧‧ signal channel

111‧‧‧Capacitively Coupled Transduction Amplifier

112,400‧‧‧Bandpass Filter Amplifier

113, 600‧‧‧ adjustable gain amplifier

114,800‧‧‧Offset elimination circuit

120, 220, 700‧‧‧transistor amplifier

230‧‧‧Multiplexer

410‧‧‧Bandpass main current path

411‧‧‧First main P-type transistor

412‧‧‧Second main P-type transistor

413‧‧‧First main N-type transistor

414‧‧‧Second main N-type transistor

420‧‧‧ bandpass filter

430‧‧‧Bandpass secondary current path

431‧‧‧First P-type transistor

432‧‧‧Second pair of P-type transistors

433‧‧‧First N-type transistor

434‧‧‧Second pair of N-type transistors

610‧‧‧Adjustable gain main current path

630‧‧‧Adjustable gain secondary current path

701‧‧‧fourth differential input amplifier

810‧‧‧Digital Controller

820‧‧‧Virtual Resistance Reset Module

830, 900‧‧‧ offset detection circuit

840‧‧‧First current digital analog converter

850‧‧‧Second current digital analog converter

860‧‧‧ Third current digital analog converter

910‧‧‧Selector

920‧‧‧Signal Conversion Circuit

921‧‧Amplifier

922‧‧‧negative feedback resistor

930‧‧‧ Comparator

10‧‧‧First switch

20‧‧‧second switch

30‧‧‧third switch

SB, SB1~SBN‧‧‧ biosignal

VOUT‧‧‧ voltage signal

ID, ID1~IDN‧‧‧Detection current

I1‧‧‧First current

I2‧‧‧second current

IS‧‧‧Select current

NIP‧‧‧ input positive terminal

NIN‧‧‧ input negative terminal

NOGM‧‧‧Transfer output

NOBP‧‧‧ bandpass output

NOPG‧‧‧ adjustable gain output

GM‧‧‧transduction gain

GI1‧‧‧First current gain

GI2‧‧‧second current gain

GTI‧‧‧ resistance gain

N1‧‧‧ first node

N2‧‧‧ second node

VCM‧‧‧ Common mode voltage

VCMC‧‧‧ Common Mode Control Voltage

CI1‧‧‧first input capacitor

CI2‧‧‧Second input capacitor

MPCM1‧‧‧First Common Mode P-type transistor

MPCM2‧‧‧Second common mode P-type transistor

IS1‧‧‧ first current source

IS2‧‧‧second current source

MPGM1‧‧‧First Transduction P-type transistor

MPGM2‧‧‧Second Transduction P-type transistor

RG‧‧‧linear resistance

MPGM3‧‧‧ third transduction P-type transistor

MPGM4‧‧‧fourth transduction P-type transistor

MNGM1‧‧‧First Transduction N-Type Transistor

MNGM2‧‧‧Second transduction N-type transistor

MNGM3‧‧‧ third transduction N-type transistor

MNGM4‧‧‧fourth transduction N-type transistor

VBGM‧‧‧Transfer bias voltage

GND‧‧‧ ground terminal

OP1‧‧‧First Differential Input Amplifier

OP2‧‧‧Second Differential Input Amplifier

OP3‧‧‧ third differential input amplifier

CC1‧‧‧First Coupling Capacitor

CC2‧‧‧Second coupling capacitor

CLP‧‧‧ low-pass capacitor

MPB1‧‧‧First bias P-type transistor

MPB2‧‧‧Second bias P-type transistor

g _m ‧‧‧Transfer conductance

INN1‧‧‧ first negative input

INP1‧‧‧ first positive input

NO1‧‧‧ first output

INN2‧‧‧ second negative input

INP2‧‧‧ second positive input

NO2‧‧‧ second output

INN3‧‧‧ third negative input

INP3‧‧‧ third positive input

NO3‧‧‧ third output

VDC‧‧‧ DC bias

VBPB1‧‧‧First Bandpass Bias Voltage

VBPB2‧‧‧Second bandpass bias voltage

IBPBM‧‧‧Bandpass main bias current

IBPBS‧‧‧Banding Sub-Bias Current

SF‧‧‧ filtered signal

VS‧‧‧ supply voltage

MPB3‧‧‧third bias P-type transistor

MPB4‧‧‧4th Bias P-type transistor

MNB1‧‧‧First bias N-type transistor

MNB2‧‧‧Second bias N-type transistor

S1‧‧‧First adjustment switch

S2‧‧‧Second adjustment switch

S3‧‧‧ third adjustment switch

S4‧‧‧fourth adjustment switch

IPGABM‧‧‧Adjustable Gain Main Bias Current

IPGABS‧‧‧Adjustable gain secondary bias current

RT‧‧‧Restoring resistor

IIN‧‧‧Input current

SR1‧‧‧First reset signal

SR2‧‧‧Second reset signal

SS‧‧‧Selection signal

SDC‧‧‧ digital compensation signal

S1~S11‧‧‧Step process

1 is a block diagram showing a front-end amplifier circuit according to an embodiment of the present invention; FIG. 2 is a block diagram showing a front-end amplifier circuit according to another embodiment of the present invention; A circuit diagram of a capacitively coupled transconductance amplifier according to an embodiment of the present invention; FIG. 4 is a circuit diagram showing a bandpass filter according to an embodiment of the present invention; and FIG. 5 is a diagram showing one of the present invention. A circuit diagram of a DC bias generating circuit according to an embodiment; 6 is a circuit diagram showing an adjustable gain amplifier according to an embodiment of the present invention; FIG. 7 is a circuit diagram showing a transimpedance amplifier according to an embodiment of the present invention; and FIG. 8 is a diagram showing Circuit diagram of an offset cancellation circuit according to an embodiment of the invention; FIG. 9 is a circuit diagram showing an offset detection circuit of FIG. 8 according to an embodiment of the present invention; and FIG. 10 is a diagram showing A flow chart of the offset detection process described in one embodiment of the invention.

The above described objects, features, and advantages of the present invention will become more apparent from the description of the appended claims appended claims A good example. It is to be understood that the invention is not limited to the scope of the invention.

1 is a block diagram showing a front end amplifier circuit according to an embodiment of the present invention. As shown in FIG. 1, the front-end amplifier circuit 100 is configured to amplify the input positive terminal NIP and the biological signal SB received by the input negative terminal NIN to generate an amplified voltage signal VOUT, which can be converted into digital data by a digital analog converter. Analyzed by a digital signal processor to instantly know the state of the body, it can be used for immediate monitoring or treatment.

According to an embodiment of the invention, the biosignal SB is an Electroencephalography (EEG) signal. According to another embodiment of the invention, the biosignal SB is a cerebral cortical electroencephalography (ECoG) signal. According to another embodiment of the invention, the biosignal SB is a local field potential (LFP) signal. According to another embodiment of the invention, the biosignal SB is an Electrocardiography (ECG) signal. According to another embodiment of the invention, the biosignal SB is an Electromymography (EMG) signal. According to other embodiments of the invention, the biosignal SB can be any known or unknown bioelectrical signal.

The front-end amplifier circuit 100 includes a signal channel 110 and a transimpedance amplifier 120. The signal channel 110 generates a detection current ID by receiving the biosignal SB through the input positive terminal NIP and the input negative terminal NIN, and the transimpedance amplifier 120 detects the current ID. The voltage signal VOUT is generated via the resistance gain GTI.

The signal path 110 includes a capacitively coupled transconductance amplifier 111, a bandpass filter amplifier 112, an adjustable gain amplifier 113, and an offset cancellation circuit 114, wherein the capacitively coupled transconductance amplifier 111 converts the received biosignal SB via the transduction gain GM The output terminal NOGM generates a first current I1. The band pass filter amplifier 112 filters the first current I1 from noise outside the frequency bandwidth BW and amplifies the first current gain GI1, and generates a second current I2 at the band pass output terminal NOBP.

The adjustable gain amplifier 113 amplifies the second current I2 by the second current gain GI2 and generates a detection current ID at the adjustable gain output terminal NOPG, wherein the second current gain GI2 is adjustable. The offset cancellation circuit 114 is configured to eliminate the capacitively coupled transconductance amplifier 111, the bandpass filter amplifier 112, and the adjustable gain amplification The output current of the device 113 is offset current, and the detailed operation will be described later.

Fig. 2 is a block diagram showing a front end amplifier circuit according to another embodiment of the present invention. As shown in FIG. 2, the front end amplifier circuit 200 includes a plurality of signal channels 210_1 210 210_N, a transimpedance amplifier 220, and a multiplexer 230. The complex signal channels 210_1~210_N receive the complex biosignals SB1~SBN, respectively, and generate complex detection currents ID1~IDN. The multiplexer 230 selects one of the complex detection currents ID1 to IDN as the selection current IS, and the transimpedance amplifier 220 converts the selection current IS into the voltage signal VOUT by using the resistance gain GTI.

According to an embodiment of the invention, the plurality of signal channels 210_1~210_N are all signal channels 110 of FIG. According to another embodiment of the present invention, the circuit of the plurality of signal channels 210_1~210_N is the signal channel 110 of FIG. 1, and the plurality of signal channels 210_1~210_N may also be different from the signal channel 110 of FIG. the same.

Figure 3 is a circuit diagram showing a capacitively coupled transconductance amplifier according to an embodiment of the present invention. As shown in FIG. 3, the capacitive coupling transduction amplifier 300 includes a first input capacitor CI1, a second input capacitor CI2, a first common mode P-type transistor MPCM1, a second common mode P-type transistor MPCM2, and a first current source. IS1, second current source IS2, first transmissive P-type transistor MPGM1, second transmissive P-type transistor MPGM2, linear resistor RG, third transmissive P-type transistor MPGM3, fourth transduced P-type transistor The MPGM4, the first transducing N-type transistor MNGM1, the second transducing N-type transistor MNGM2, the third transducing N-type transistor MNGM3, and the fourth transducing N-type transistor MNGM4.

The first input capacitor CI1 is coupled between the input negative terminal NIN and the first node N1, and the second input capacitor CI2 is coupled to the input positive terminal NIP and the second Between the nodes N2, the first input capacitor CI1 and the second input capacitor CI2 receive the biosignal SB in an alternating current mode in a differential mode. The first common mode P-type transistor MPCM1 is used to supply the common mode voltage VCM to the first node N1 according to the common mode control voltage VCMC; the second common mode P type transistor MPCM2 is used to control the voltage VCMC according to the common mode. The mode voltage VCM is supplied to the second node N2.

According to an embodiment of the invention, the first common mode P-type transistor MPCM1 and the second common mode P-type transistor MPCM2 are both operated in a cut-off region for generating a high impedance channel resistance. According to another embodiment of the present invention, the first common mode P-type transistor MPCM1 and the second common mode P-type transistor MPCM2 are operable in a triode region.

The source terminal of the first transducing P-type transistor MPGM1 receives the first transconductance bias current provided by the first current source IS1, the gate terminal is coupled to the second node N2; and the source of the second transducing P-type transistor MPGM2 Extremely receiving the second transducing bias current of the second current source IS2, the gate terminal is coupled to the first node N1, wherein the first transducing P-type transistor MPGM1 and the second transducing P-type transistor MPGM2 are used to generate the revolving The gain is GM. The linear resistor RG is coupled between the source terminal of the first transducing P-type transistor MPGM1 and the source terminal of the second transducing P-type transistor MPGM2, wherein the linear resistor RG is used to increase the linearity of the transduction gain GM.

The source of the third transducing P-type transistor MPGM3 is coupled to the 汲 terminal of the first transducing P-type transistor MPGM1, and the gate terminal of the third transducing P-type transistor MPGM3 is coupled to the transconductance bias voltage VBGM; The source of the fourth transducing P-type transistor MPGM4 is coupled to the 汲 terminal of the second transmissive P-type transistor MPGM2, and the gate of the fourth transducing P-type transistor MPGM4 is coupled to the transimpedance bias voltage VBGM. The fourth transconductance P-type transistor MPGM4 is extremely coupled to the transconductance output The terminal NOGM, wherein the transconductance output terminal NOGM outputs the first current I1.

The 汲 extreme and the gate terminal of the first transduction N-type transistor MNGM1 are coupled to the 汲 terminal of the third transconductance P-type transistor MPGM3; the second transduction N-type transistor MNGM2 is coupled to the 汲 terminal The gate terminal of the second transducing N-type transistor MNGM2 is coupled to the gate terminal of the first transmissive N-type transistor MNGM1.

The 汲 terminal of the third transduction N-type transistor MNGM3 and the gate extremity are all coupled to the source terminal of the first transconductance N-type transistor MNGM1, and the source terminal of the third transduction N-type transistor MNGM3 is coupled to the ground terminal. GND; the fourth transconductance N-type transistor MNGM4 is extremely coupled to the source terminal of the second transduction N-type transistor MNGM2, and the gate terminal of the fourth transduction N-type transistor MNGM4 is coupled to the third transduction N The gate terminal of the type transistor MNGM3, the source terminal of the fourth transconductance N-type transistor MNGM4 is coupled to the ground terminal GND.

Fig. 4 is a circuit diagram showing a band pass filter according to an embodiment of the present invention. As shown in FIG. 4, the bandpass filter amplifier 400 includes a bandpass main current path 410, a bandpass filter 420, and a bandpass secondary current path 430. The band pass main current path 410 has a band pass main bias current IBPBM for receiving the first current I1; the band pass sub current path 430 has a band pass sub buck current IBPBS, and the second current I2 is generated according to the filtered signal SF The first current gain GI1 is a ratio of the band pass sub-bias current IBPBS to the band pass main bias current IBPBM.

The bandpass filter 420 is AC coupled to the bandpass main current path 410 for filtering the noise outside the frequency bandwidth BW by the first current I1 to produce the filtered signal SF to the bandpass secondary current path 430. The functions of the band pass main current path 410, the band pass filter 420, and the band pass sub current path 430 will be described in detail below.

According to an embodiment of the invention, the bandpass main current path 410 includes a first main P-type transistor 411, a second main P-type transistor 412, a first main N-type transistor 413, and a second main N-type transistor 414. . The source terminal of the first main P-type transistor 411 is coupled to the supply voltage VS, and the gate terminal of the first main P-type transistor 411 is coupled to the 汲 terminal. The source terminal of the second main P-type transistor 412 is coupled to the 汲 terminal of the first main P-type transistor 411, and the gate terminal and the 汲 terminal of the second main P-type transistor 412 receive the capacitive coupling transfer shown in FIG. The pilot amplifier 111 and the capacitively coupled transconductance amplifier 300 shown in FIG. 3 have a first current I1.

The gate terminal and the 汲 terminal of the first main N-type transistor 413 are coupled to the 汲 terminal of the first main P-type transistor 412 and the gate terminal. The gate terminal of the second main N-type transistor 414 and the drain terminal are coupled to the source terminal of the first main N-type transistor 413, and the source terminal of the second main N-type transistor 414 is coupled to the ground GND.

According to an embodiment of the present invention, the first main P-type transistor 411, the second main P-type transistor 412, the first main N-type transistor 413, and the second main N-type transistor 414 are all operated in the subcritical region. To reduce power loss. According to another embodiment of the present invention, the band pass main current path 410 may also be composed of the second main P-type transistor 412 and the first main N-type transistor 413, but cause the second main P-type transistor 412 and the The gate-to-source voltage across the main N-type transistor 413 increases to increase the bandpass main bias current IBPBM, resulting in increased power loss.

Similarly, the band pass secondary current path 430 includes a first secondary P-type transistor 431, a second secondary P-type transistor 432, a first secondary N-type transistor 433, and a second secondary N-type transistor 434. The source terminal of the first sub-P-type transistor 431 is coupled to the supply voltage VS, and the gate terminal and the 汲 terminal of the first sub-P-type transistor 431 are coupled together. The source of the second sub-P transistor 432 is coupled to the first sub-P-type transistor 431 At the 汲 extreme, the second sub-P-type transistor 432 is coupled to the band-pass output terminal NOBP.

The gate of the first sub-N-type transistor 433 is coupled to the gate terminal of the second sub-P transistor 432. The first sub-N-type transistor 433 is coupled to the band-pass output terminal NOBP to output a second current. I2, the gate terminal of the first sub N-type transistor receives the filtered signal SF. The gate terminal of the second sub-N-type transistor 434 and the NMOS terminal are coupled to the source terminal of the first sub-N-type transistor 433, and the source terminal of the second sub-N-type transistor 434 is coupled to the ground GND.

According to an embodiment of the present invention, the first sub-P-type transistor 431, the second sub-P-type transistor 432, the first sub-N-type transistor 433, and the second sub-N-type transistor 434 are all operating in the subcritical region. To reduce power loss. According to another embodiment of the present invention, the band pass sub current path 430 is the same as the band pass main current path 410, and may also be composed of the second sub P type transistor 432 and the first sub N type transistor 433, but The second sub-P transistor 432 and the first sub N-type transistor 433 increase the gate-to-source terminal voltage increase to increase the band-pass sub-bias current IBPBS, so that the power loss increases.

According to an embodiment of the invention, the ratio of the size of the transistor of the band pass sub-current path 430 to the size of the transistor of the band pass main current path 410 is the band pass sub-bias current IBPBS and the band pass main bias current The ratio of IBPBM is also the first current gain GI1.

According to an embodiment of the present invention, the band pass filter 420 includes a first differential input amplifier OP1, a first coupling capacitor CC1, a first bias P-type transistor MPB1, a low-pass capacitor CLP, and a second differential input amplifier OP2. a third differential input amplifier OP3, a second coupling capacitor CC2, and a second bias P-type transistor MPB2.

The first differential input amplifier OP1 is configured to generate a transfer conductance g _m and includes a first negative input terminal INN1, a first positive input terminal INP1, and a first output terminal NO1, wherein the first negative input terminal INN1 is coupled to the first output terminal End NO1. The first coupling capacitor CC1 is coupled between the gate terminal of the second main P-type transistor 412 and the first positive input terminal INP1; the first bias P-type transistor MPB1 has a channel resistance, and the source terminal is coupled to the common mode. The voltage VCM, 汲 is extremely coupled to the first positive input terminal INP1, and the gate terminal is coupled to the first bandpass bias voltage VBPB1.

The low-pass capacitor CLP is coupled between the first output terminal NO1 and the ground GND; the second differential input amplifier OP2 includes a second negative input terminal INN2, a second positive input terminal INP2, and a second output terminal NO2, wherein the second The negative input terminal INN2 is coupled to the second output terminal NO2, and the second positive input terminal INP2 is coupled to the first output terminal NO1. The third differential input amplifier OP3 includes a third negative input terminal INN3, a third positive input terminal INP3, and a third output terminal NO3, wherein the third negative input terminal INN3 is coupled to the third output terminal NO3, and the third output terminal NO3 is output. Filter signal SF.

The second coupling capacitor CC2 is coupled between the second output terminal NO2 and the third positive input terminal INP3 for isolating the second differential input amplifier OP2 and the third differential input amplifier OP3. The second bias P-type transistor MPB2 is controlled according to the second band-pass bias voltage VBPB2 for supplying the DC bias voltage VDC to the third positive input terminal INP3 such that the gate terminal of the second sub-P-type transistor 432 and The bias of the gate terminal of the first sub-type N-type transistor 433 is the same as the gate terminal of the second main-type transistor 412 and the gate terminal of the first main N-type transistor 413.

Figure 5 is a diagram showing a direct current according to an embodiment of the present invention. A circuit diagram of a bias generating circuit. As shown in FIG. 5, the DC bias generating circuit 500 includes a third bias P-type transistor MPB3, a fourth bias P-type transistor MPB4, a first bias N-type transistor MNB1, and a second bias N-type. Transistor MNB2.

According to an embodiment of the present invention, the size of the third bias P-type transistor MPB3, the fourth bias P-type transistor MPB4, the first bias N-type transistor MNB1, and the second bias N-type transistor MNB2, The size of the first main P-type transistor 411, the second main P-type transistor 412, the first main N-type transistor 413, and the second main N-type transistor 414 is reduced by a predetermined ratio, so that the generated DC bias The voltage values of the gate terminals of the voltage VDC system and the second main P-type transistor 412 are very close.

Referring to FIG. 4, according to an embodiment of the present invention, the first bias P-type transistor MPB1 and the second bias P-type transistor MPB2 are operated in the cut-off region such that their channel resistance is high impedance. According to an embodiment of the present invention, the frequency bandwidth BW of the band pass filter 420 includes a low pass cutoff frequency and a high pass cutoff frequency, wherein the transfer conductance g _m and the low pass capacitance CLP generated by the first differential input amplifier OP1 are used to determine The low-pass cutoff frequency, the first coupling capacitor CC1 and the channel resistance of the first bias P-type transistor MPB1 are used to determine the high-pass cutoff frequency.

Figure 6 is a circuit diagram showing an adjustable gain amplifier in accordance with an embodiment of the present invention. The adjustable gain amplifier 600 includes an adjustable gain main current path 610 and an adjustable gain sub current path 630 for amplifying the second current I2 and generating a detection current ID at the adjustment gain output terminal NOPG.

As shown in FIG. 6, the adjustable gain main current path 610 is similar to the band pass main current path 410, and the adjustable gain sub current path 630 is similar to the band pass sub current path 430. Therefore, the gain main current path 610 can be adjusted. And the operating principle of the adjustable gain secondary current path 630 is coupled to the bandpass main current path 410. The operation principle of the band pass sub current path 430 is the same, and will not be described herein.

The adjustable gain secondary current path 630 can increase the adjustable gain secondary bias current IPGABS by using the first adjustment switch S1, the second adjustment switch S2, the third adjustment switch S3, and the fourth adjustment switch S4, resulting in an adjustable gain secondary bias The ratio of the voltage current IPGABS to the adjustable gain main bias current IPGABM is increased or decreased, and the second current gain GI2 is adjusted.

Figure 7 is a circuit diagram showing a transimpedance amplifier according to an embodiment of the present invention. As shown in FIG. 7, the transimpedance amplifier 700 includes a fourth differential input amplifier 701 and a feedback resistor RT for converting the input current IIN into a voltage signal VOUT. The fourth differential input amplifier 701 includes a positive input terminal, a negative input terminal, and an output terminal. The feedback resistor RT is coupled between the negative input terminal and the output terminal of the fourth differential input amplifier 701.

The positive input terminal of the fourth differential input amplifier 701 is coupled to the common mode voltage VCM, and the negative input terminal receives the input current IIN. According to an embodiment of the invention, the input current IIN is the detection current ID of FIG. 1 or the selection current IS of FIG. 2, and the resistance gain GTI is determined by the feedback resistor RT.

Figure 8 is a circuit diagram showing an offset cancellation circuit in accordance with an embodiment of the present invention. As shown in FIG. 8 , the offset cancellation circuit 800 includes a digital controller 810 , a virtual resistance reset module 820 , an offset detection circuit 830 , a first current digital analog converter 840 , and a second current digital analog converter 850 . The third current digital analog converter 860, the first switch 10, the second switch 20, and the third switch 30, wherein the offset cancel circuit 800 is an embodiment of the offset cancel circuit 114 of FIG. According to an embodiment of the invention, the virtual resistance reset module 820 utilizes a voltage level that couples the common mode control voltage VCMC to the ground GND. The first node N1 and the second node N2 are short-circuited to the common mode voltage VCM.

The digital controller 810 controls the virtual resistance reset module 820 to short the first node N1 and the second node N2 of FIG. 3 to the common mode voltage VCM by using the first reset signal SR1 to test the output of the capacitive coupling transduction amplifier 300. Offset current. In addition, the digital controller 810 further controls the virtual resistance reset module 820 by using the second reset signal SR2, short-circuiting the first positive input terminal INP1 of FIG. 4 to the common mode voltage VCM and short-circuiting the third positive input terminal INP3 to The DC bias is VDC to test the output offset current of the bandpass filter amplifier 400.

According to an embodiment of the invention, the virtual resistance reset module 820 is coupled to the voltage level of the ground GND by the first band-pass bias voltage VBPB1 and the second band-pass bias voltage VBPB2, and the first positive The input terminal INP1 is shorted to the common mode voltage VCM and the third positive input terminal INP3 is shorted to the DC bias voltage VDC.

The offset detecting circuit 830 sequentially selects one of the first current I1, the second current I2, and the detected current ID according to the selection signal SS sent by the digital controller 810 to generate a digital compensation signal SDC, wherein the digital compensation signal SDC The first compensation code, the second compensation code, and the third compensation code respectively corresponding to the first current I1, the second current I2, and the detection current ID are respectively used to respectively control the first current digital analog converter 840 and the second current digital position. The analog converter 850 and the third current digital analog converter 860, and the digital controller 810 stores the digital compensation signal SDC in the register 870.

Figure 9 is a circuit diagram showing an offset detecting circuit of Figure 8 according to an embodiment of the present invention. As shown in FIG. 9, the offset detection circuit 900 includes a selector 910, a signal conversion circuit 920, and a comparator 930 for sequentially selecting the first current I1, the second current I2, and the detection current ID to generate digital compensation. letter The first compensation code, the second compensation code, and the third compensation code of the SDC.

The selector 910 is configured to sequentially select the first current I1, the second current I2, and the detection current ID according to the selection signal SS, and provide the signal to the signal conversion circuit 920. The signal conversion circuit 920 includes an amplifier 921 and a negative feedback resistor 922 for converting one of the first current I1, the second current I2 and the detection current ID selected by the selector 910 into an offset voltage VOS. The comparator 930 compares the common mode voltage VCM and the offset voltage VOS to generate a digital compensation signal SDC.

The digital controller 810 of FIG. 8 determines the first compensation code, the second compensation code, and the third compensation code according to the digital compensation signal SDC generated by the sequence, and the control is provided to the transduction output terminal NOGM, the band-pass output terminal NOBP, and the adjustable gain. The compensation current of the output NOPG.

Referring to FIG. 8, according to an embodiment of the present invention, the digital controller 810 controls the first switch 10, the second switch 20, and the third switch 30 to be turned on and off, for individually testing the capacitive coupling transduction amplifier 111 and the band pass. The filter amplifier 112 and the output offset current of the adjustable gain amplifier 113, the detailed actions will be described below. According to another embodiment of the present invention, in the front-end amplifier circuit 200 of FIG. 2, the third switch 30 can be replaced with the multiplexer 230.

Figure 10 is a flow chart showing the offset detection process according to an embodiment of the present invention. The flow chart shown in Fig. 10 will be described below in conjunction with the first, third, fourth, and eighth drawings.

First, the digital controller 810 of FIG. 8 disables the first switch 10, the second switch 20, and the third switch 30 for isolating the capacitive coupling transduction amplifier 111, the band pass filter amplifier 112, and the adjustable gain amplifier 113. The coupling relationship between the steps (step S1). And using the first reset signal SR1 to control the virtual resistor The first node N1 and the second node N2 of the capacitively coupled transconductance amplifier 300 of FIG. 3 are short-circuited to the common mode voltage VCM for resetting the input of the capacitively coupled transconductance amplifier 111 of FIG. A signal is detected to detect an output offset current of the capacitively coupled transconductance amplifier 111 (step S2).

The offset detecting circuit 830 detects the first current I1 according to the selection signal SS to generate a first compensation code of the digital compensation signal SDC and stores it in the temporary register 870 (step S3). The digital controller 810 further controls the first current digital analog converter 840 to output a compensation current to the transconductance output terminal NOGM according to the first compensation code (step S4).

Next, the digital controller 810 turns on the first switch 10 to couple the capacitive coupling transduction amplifier 111 to the band pass filter amplifier 112 (step S5), and controls the virtual resistance reset module by using the second reset signal SR2. 820, shorting the first positive input terminal INP1 of the band pass filter amplifier 400 of FIG. 4 to the common mode voltage VCM and shorting the third positive input terminal INP3 to the DC bias voltage VDC for returning the band pass of FIG. The input signal of the amplifier 112 is filtered to detect the output offset current of the band pass filter amplifier 112 (step S6). The offset detecting circuit 830 detects the second current I2 according to the selection signal SS to generate a second compensation code of the digital compensation signal SDC and stores it in the register 870 (step S7). The digital controller 810 further controls the second current digital analog converter 850 to output a compensation current to the band pass output terminal NOBP according to the second compensation code (step S8).

Then, the digital controller 810 turns on the second switch 20, and then couples the band pass filter amplifier 112 to the adjustable gain amplifier 113 (step S9); the offset detecting circuit 830 detects the detected current according to the selection signal SS. The third compensation code of the digital compensation signal SDC is generated by the ID and stored in the register 870 (step S10). The digital controller 810 further controls the third current digital analog converter 860 to output a compensation current to the adjustable gain output terminal NOPG according to the third compensation code (step S11).

The features of many embodiments are described above to enable those of ordinary skill in the art to clearly understand the form of the specification. Those having ordinary skill in the art will appreciate that the objectives of the above-described embodiments and/or advantages consistent with the above-described embodiments can be accomplished by designing or modifying other processes and structures based on the present disclosure. It is also to be understood by those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

100‧‧‧ front-end amplifier circuit

110‧‧‧Signal channel

111‧‧‧Capacitively Coupled Transduction Amplifier

112‧‧‧Bandpass Filter Amplifier

113‧‧‧Adjustable Gain Amplifier

114‧‧‧Offset elimination circuit

120‧‧‧Transistor Amplifier

GM‧‧‧transduction gain

GI1‧‧‧First current gain

GI2‧‧‧second current gain

GTI‧‧‧ resistance gain

NIP‧‧‧ input positive terminal

NIN‧‧‧ input negative terminal

NOGM‧‧‧Transfer output

NOBP‧‧‧ bandpass output

NOPG‧‧‧ adjustable gain output

I1‧‧‧First current

I2‧‧‧second current

ID‧‧‧Detecting current

SB‧‧ biosignal

VOUT‧‧‧ voltage signal

Claims (17)

A front-end amplifier circuit for receiving a biological signal, comprising: a signal channel for amplifying the biological signal to generate a detection current, wherein the signal channel comprises: a capacitive coupling transduction amplifier, the biological signal is amplified and transduced Gain, and outputting a first current; and a bandpass filter amplifier, filtering the first current to noise outside the frequency band and amplifying a first current gain, and outputting a second current. The front-end amplifier circuit of claim 1, wherein the capacitive coupling transduction amplifier comprises: a first input capacitor coupled between an input negative terminal and a first node; and a second input capacitor, The first input capacitor and the second input capacitor are in a differential mode to AC-couple the biosignal; and the first common mode P-type transistor is coupled to the first input capacitor and the second node. Providing a common mode voltage to the first node; a second common mode P-type transistor for supplying the common mode voltage to the second node; and a first current source for providing a first transducing a bias current; a second current source for providing a second transducing bias current; a first transducing P-type transistor, the source terminal receiving the first transducing bias current, and the gate terminal coupled to the a second node; a second transducing P-type transistor, the source terminal receiving the second transducing bias voltage And the first terminal is coupled to the first node, wherein the first transducing P-type transistor and the second transmissive P-type transistor are used to generate the transduction gain; a linear resistor coupled to the first Transducing a source terminal of the P-type transistor and a source terminal of the second transducing P-type transistor, wherein the linear resistor is used to increase linearity of the transduction gain; and a third transducing P-type transistor The source terminal is coupled to the first terminal of the first transmissive P-type transistor, the gate terminal is coupled to a transconductance bias voltage, and the fourth transconductance P-type transistor is coupled to the second transistor. The first terminal is coupled to the transconductance bias voltage, and the transconductance output terminal outputs the first current; the first transduction N The transistor, the 汲 terminal and the gate terminal are all coupled to the 汲 terminal of the third transducing P-type transistor; a second transducing N-type transistor, the 汲 is extremely coupled to the transconductance output terminal, and the gate is extremely coupled Connected to the gate terminal of the first transduction N-type transistor; a third transduction N-type transistor The 汲 extreme and the gate terminal are all coupled to the source terminal of the first transduction N-type transistor, the source terminal is coupled to a ground terminal, and a fourth transconductance N-type transistor, the 汲 terminal is coupled to the second Transducing the source terminal of the N-type transistor, the gate terminal is coupled to the gate terminal of the third transducing N-type transistor, and the source terminal is coupled to the ground terminal. The front-end amplifier circuit of claim 2, wherein the signal channel further comprises: an adjustable gain amplifier, wherein the second current is amplified by a second current Advantageously, the output current is outputted by an adjustment gain output, wherein the second current gain is adjustable; and an offset cancellation circuit for eliminating the capacitive coupling transduction amplifier, the band pass filter amplifier, and the Adjust the output offset current of the gain amplifier. The front-end amplifier circuit as described in claim 3, further comprising: a transimpedance amplifier for converting the detected current into a voltage signal via a resistance gain, and providing a driving capability to the coupling The measurement system, wherein the magnification of the biosignal to the voltage signal is a product of the transduction gain, the first current gain, the second current gain, and the transimpedance gain. The front-end amplifier circuit as described in claim 3, wherein the band-pass filter amplifier comprises: a band-pass main current path having a band-pass main bias current for receiving the first current; a band pass filter, alternating current Coupling to the band pass main current path, filtering the noise from the first current to generate a filtered signal: and a band pass sub current path having a band pass sub-bias current and according to the filtered signal The second current is generated, wherein the first current gain is a ratio of the band pass sub-bias current to the band pass main bias current. The front-end amplifier circuit as described in claim 5, wherein the band-pass main current path comprises: a first main P-type transistor, the source terminal is coupled to a supply voltage, and the gate terminal Coupling to the 汲 terminal; a second main P-type transistor, the source terminal is coupled to the 汲 terminal of the first main P-type transistor, the gate terminal and the 汲 terminal receiving the first current; and a first main N-type battery a crystal, a gate terminal and a 汲 terminal are coupled to the 汲 terminal of the first main P-type transistor; and a second main N-type transistor, the gate terminal and the 汲 terminal are coupled to the source of the first main N-type transistor Extremely, the source is extremely coupled to the ground terminal. The front-end amplifier circuit according to claim 6, wherein the first main P-type transistor, the second main P-type transistor, the first main N-type transistor, and the second main N-type transistor The system operates in the subcritical region to reduce power loss. The front-end amplifier circuit of claim 6, wherein the band-pass sub-current path comprises: a first sub-P-type transistor, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the 汲 terminal; a second sub-P transistor, the source terminal is coupled to the first terminal of the first sub-P-type transistor, and the 汲 terminal is coupled to a band-pass output terminal; a first sub-N-type transistor, the gate terminal is coupled to the above a gate terminal of the second sub-P transistor, the 汲 terminal is coupled to the band-pass output terminal, wherein the gate terminal of the first sub-N-type transistor receives the filtered signal, and the band-pass output terminal outputs the second current; And a second sub-N-type transistor, the gate terminal and the 汲 terminal are coupled to the source terminal of the first sub-N-type transistor, and the source terminal is coupled to the ground terminal, wherein the transistor of the band-pass sub-current path is Dimensions and the above-mentioned bandpass main current path The ratio of the size of the transistor to the diameter is the first current gain described above. The front-end amplifier circuit according to claim 8, wherein the first sub-P-type transistor, the second sub-P-type transistor, the first sub-N-type transistor, and the second sub-N-type transistor The system operates in the subcritical region to reduce power loss. The front-end amplifier circuit of claim 8, wherein the band-pass filter comprises: a first differential input amplifier for generating a transfer conductance, comprising a first negative input terminal and a first positive input terminal; And a first output terminal, wherein the first negative input terminal is coupled to the first output terminal; a first coupling capacitor coupled to the gate terminal of the second main P-type transistor and the first positive input Between the terminals; a first bias P-type transistor having a channel resistance, the source terminal is coupled to the common mode voltage, the 汲 terminal is coupled to the first positive input terminal, and the gate terminal is coupled to a first band a bias voltage; a low-pass capacitor coupled between the first output terminal and the ground terminal; a second differential input amplifier comprising a second negative input terminal, a second positive input terminal, and a first a second output terminal, wherein the second negative input terminal is coupled to the second output terminal, the second positive input terminal is coupled to the first output terminal; and a third differential input amplifier includes a third negative input terminal a third positive input and A third output terminal, wherein said third negative input terminal coupled to the third output terminal, the third signal output terminal of said filter; a second coupling capacitor coupled to the second output terminal and said third n Between the input terminals for isolating the second differential input amplifier and the third differential input amplifier; and a second bias P-type transistor for providing a DC bias voltage to the third positive input terminal The gate terminal of the second sub-P transistor and the gate terminal of the first sub N-type transistor are biased to the DC bias. The front-end amplifier circuit of claim 10, wherein the frequency bandwidth comprises a low-pass cutoff frequency and a high-pass cutoff frequency, wherein the transfer conductance and the low-pass capacitance determine the low-pass cutoff frequency, wherein the first The coupling capacitor and the above-mentioned channel resistance determine the above-mentioned high-pass cutoff frequency. The front-end amplifier circuit of claim 10, wherein the first bias P-type electro-emissive system operates in a cut-off region such that the channel resistance is high impedance. The front end amplifier circuit of claim 10, wherein the offset cancellation circuit comprises: a digital controller, generating a first reset signal, a second reset signal, and a selection signal; And setting a module, shorting the first node and the second node to the common mode voltage according to the first reset signal, and shorting the first positive input terminal to the common mode voltage according to the second reset signal and Shorting the third positive input terminal to the DC bias voltage; an offset detecting circuit sequentially detecting the first current, the second current, and the detecting current according to the selection signal to generate a first a compensation current code, a second compensation current code, and a third compensation current code; a first current digital analog converter, according to the first compensation current code, extracting or providing a first compensation current to the transduction output end; a second current digital analog converter, according to the second compensation current code, The band pass output terminal extracts or provides a second compensation current; a third current digital analog converter, extracts or supplies a third compensation current to the adjusted gain output terminal according to the third compensation current code; and temporarily stores And storing the first compensation current code, the second compensation current code, and the third compensation current code. The front-end amplifier circuit of claim 13, wherein the signal path further comprises: a first switch coupled between the capacitive coupling transduction amplifier and the band-pass filter amplifier, and according to the digital controller One of the first open circuit signals is not turned on; and a second switch is coupled between the band pass filter amplifier and the adjustable gain amplifier, and is not turned on according to the second open circuit signal of one of the digital controllers. The front-end amplifier circuit of claim 14, wherein when the first switch and the second switch are not turned on, the offset detecting circuit generates the first current according to the selection signal to generate the first a compensation current code, wherein when the first switch is turned on and the second switch is not turned on, the first current digital analog converter extracts or supplies the first compensation current to the transduction output, and the offset detection The circuit detects the second current according to the selection signal to generate the second compensation current code, wherein When the first switch and the second switch are both turned on, the first current digital analog converter extracts or supplies the first compensation current to the transduction output end, and the second current digital analog converter outputs the band pass output. And extracting or providing the second compensation current, and the offset detecting circuit detects the detection current according to the selection signal to generate the third compensation current code. The front end amplifier circuit of claim 14, wherein the offset detecting circuit further comprises: a sampling amplifier for converting an input current into a comparison voltage; and a selection switch according to the selection signal And selecting, as the input current, one of the first current, the second current, and the detecting current; and a comparator, comparing the comparison voltage and a reference voltage to generate an output signal, wherein the digital controller is configured according to the foregoing And outputting the signal to determine the first compensation current code, the second compensation current code, and the third compensation current code. The front-end amplifier circuit as described in claim 4, further comprising: another signal channel, receiving and amplifying another bio-signal to generate another detecting current; and a multiplexer for detecting the current and the above One of the other detection currents is supplied to the above-described transimpedance amplifier.