TWI584562B - Semiconductor device - Google Patents

Description

Semiconductor device

Embodiments of the invention relate to semiconductor devices.

As a material for a new generation of power semiconductor devices, a group III nitride such as a GaN (gallium nitride) semiconductor is expected. The GaN-based semiconductor system has a wide band gap as compared with Si. Therefore, the GaN-based semiconductor device can achieve high withstand voltage and low loss as compared with a Si (cerium) semiconductor device.

In a GaN-based transistor, a HEMT (High Electron Mobility Transistor) structure using a binary electron gas (2DEG) as a carrier is generally applied. A normal HEMT is a normally-on transistor that conducts electricity even when no voltage is applied to the gate. Therefore, it is a problem that a transistor that realizes a normally-off transistor in which no voltage is applied to the gate and is not turned on is difficult.

In a power supply circuit that handles a large amount of power of several hundred to one thousand V, the safety surface is emphasized and a normally-off operation is required. Therefore, it is proposed to splicing a normally-connected GaN-based transistor with a normally-off Si transistor, and The circuit structure that realizes the normally-off operation.

However, in such a circuit configuration, it is a problem that destruction or deterioration of characteristics of an element having an overvoltage condition occurs in a connection portion between two transistors.

[Previous Technical Literature] [Patent Document]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2014-187726

As a subject to be solved by the present invention, there is provided a semiconductor device in which a normally-off transistor connected in series and a reliability of a normally-on crystal are improved.

The semiconductor device according to the embodiment includes: a normally-off transistor having a first source, a first drain, and a first gate, and a second source electrically connected to the first drain, and a second drain a second-gate normally-on crystal, and a capacitor having a first end portion and a second end portion, wherein the second end portion is electrically connected to the second gate electrode, and electrically connected to the first portion a first anode between the end portion 2 and the second gate electrode, and a first diode having a first cathode electrically connected to the second source, and the first end portion and the first end portion a first impedance between the first gates and a second anode electrically connected to the first end portion, and A second diode that is electrically connected to the second cathode of the first gate and is provided in parallel with the first impedance.

10‧‧‧Normally broken crystal

11‧‧‧1st source

12‧‧‧1st bungee

13‧‧‧1st gate

20‧‧‧Normally energized crystal

21‧‧‧2nd source

22‧‧‧2nd bungee

23‧‧‧2nd gate

30‧‧‧ Capacitors

31‧‧‧1st end

32‧‧‧2nd end

40‧‧‧1st dipole

41‧‧‧1st anode

42‧‧‧1st cathode

50‧‧‧1st impedance

55‧‧‧3rd impedance

60‧‧‧2nd diode

61‧‧‧2nd anode

62‧‧‧2nd cathode

70‧‧‧2nd impedance

80‧‧‧Schottky barrier diode

81‧‧‧3rd anode

82‧‧‧3rd cathode

85‧‧‧Jenner diode

86‧‧‧4th anode

87‧‧‧4th cathode

90‧‧‧5th dipole

91‧‧‧5th anode

92‧‧‧5th cathode

100‧‧‧ source terminal

200‧‧‧汲 extremes

300‧‧ ‧ gate terminal

Fig. 1 is a circuit diagram of a semiconductor device according to a first embodiment.

2 is a circuit diagram of a semiconductor device of a comparative form.

Fig. 3 is a circuit diagram of a semiconductor device according to a second embodiment.

Fig. 4 is a circuit diagram of a semiconductor device according to a third embodiment.

Fig. 5 is a circuit diagram of a semiconductor device of a fourth embodiment.

Fig. 6 is a circuit diagram of a semiconductor device of a fifth embodiment.

Fig. 7 is a circuit diagram of a semiconductor device according to a sixth embodiment.

Fig. 8 is a circuit diagram of a semiconductor device according to a seventh embodiment.

Fig. 9 is a circuit diagram of a semiconductor device of an eighth embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, in the following description, the same or similar components are attached with the same symbols. In addition, the description of the member and the like which have been described above is appropriately omitted.

Further, in the present specification, the semiconductor device includes a power module in which a plurality of components such as a discrete semiconductor are combined, or a driver circuit or a self-protection function for driving a component such as a discrete semiconductor or the like. Power module, or with power module or The concept of the entire system of intelligent power modules.

In addition, in the present specification, the "GaN-based semiconductor" includes a general term for GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), and the like.

(First embodiment)

The semiconductor device of the present embodiment includes a normally-off transistor having a first source, a first drain, and a first gate, and a second source electrically connected to the first drain, and a second drain a second-gate normally-on crystal, and a capacitor having a first end and a second end, and a second end electrically connected to the second gate, and having a capacitor electrically connected to the capacitor a first anode between the gates, a first diode electrically connected to the first cathode of the second source, and a first impedance provided between the first end and the first gate And a second diode having a second anode electrically connected to the first end and a second cathode electrically connected to the first gate, and being provided in parallel with the first impedance.

Fig. 1 is a circuit diagram of a semiconductor device of the embodiment. The semiconductor device of the present embodiment is, for example, a power module having a rated voltage of 600 V or 1200 V.

The semiconductor device of the present embodiment includes a normally-off transistor 10, a normally-on crystal 20, a capacitor 30, a first diode 40, a first impedance 50, and a second diode 60. Further, the semiconductor device includes a source terminal 100, a gate terminal 200, and a gate terminal 300.

The semiconductor device of this embodiment is connected in series The power transistor 10 and the normally energized crystal 20 form a power module.

The normally-off transistor 10 is a transistor in which a voltage is not applied to the gate and is not turned on. The normally-off transistor 10 is, for example, a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using Si (矽) semiconductor.

Further, the normally-on crystal 20 is a transistor that is turned on even if no voltage is applied to the gate. The normally-on crystal 20 is, for example, a HEMT using a GaN (gallium nitride)-based semiconductor. The normally-on crystal 20 has a gate insulating film.

However, the normally-off transistor 10 includes a parasitic body diode (not shown).

The normally-off transistor 10 is compared to the normally-on crystal 20, and the component withstand voltage is low. The component withstand voltage of the normally-off transistor 10 is, for example, 10 to 30V. Further, the component withstand voltage of the normally-on crystal 20 is, for example, 600 to 1200V.

The normally-off transistor 10 has a first source 11, a first drain 12, and a first gate 13. The normally-on crystal 20 has a second source 21, a second drain 22, and a second gate 23.

The first source 11 is electrically connected to the source terminal 100. The first drain 12 is electrically connected to the second source 21. The first gate 13 is electrically connected to the gate terminal 300.

The second source 21 is electrically connected to the first drain 12 . The second drain 22 is electrically connected to the 汲 terminal 200. The second gate 23 is electrically connected to the gate terminal 300. Following, will be connected The range of the first drain 12 and the second source 21 is referred to as a connection portion.

The capacitor 30 has a first end portion 31 and a second end portion 32. The capacitor 30 is provided between the gate terminal 300 and the second gate 23. The first end portion 31 is electrically connected to the gate terminal 300. Further, the second end portion 32 is electrically connected to the second gate electrode 23.

The first diode 40 has a first anode 41 and a first cathode 42. The first anode 41 is electrically connected between the second end portion 32 of the capacitor 30 and the second gate 23. Further, the first cathode 42 is electrically connected to the second source electrode 21.

The first diode 40 is, for example, a PiN diode or a Schottky barrier diode.

The first impedance 50 is provided between the first end portion 31 of the capacitor 30 and the first gate 13. One end of the first impedance 50 is electrically connected to the gate terminal 300. The other end of the first impedance 50 is electrically connected to the first gate 13.

The second diode 60 has a second anode 61 and a second cathode 62. The second anode 61 is electrically connected to the first end portion 31 of the capacitor 30. The second cathode 62 is electrically connected to the first gate 13. The second diode 60 is connected in parallel to the first impedance 50.

The second diode 60 is, for example, a PiN diode or a Schottky barrier diode.

Next, the operation and effects of the semiconductor device of the present embodiment will be described. The semiconductor device of the present embodiment includes the source terminal 100, the gate terminal 200, and the gate terminal via the above configuration. The sub-300 normally breaks the transistor and functions. Hereinafter, the operation of the semiconductor device of the present embodiment will be described.

The connection between the normally-off transistor 10 and the normally-on crystal 20, that is, the first drain 12 of the normally-off transistor 10, or the second source 21 of the normally-on crystal 20, has an overvoltage generated during the operation of the device. Hey. The overvoltage is, for example, a transition current generated when the semiconductor device transitions from the on state to the off state, and the high voltage applied between the source terminal 100 and the gate terminal 200 is via the normally-off transistor 10 It is obtained when the ratio of the parasitic capacitance of the normally charged crystal 20 is divided.

When an overvoltage is generated, a high voltage is applied between the second source 21 of the normally-on crystal 20 and the second gate 23. When the overvoltage is equal to or higher than the withstand voltage of the gate insulating film, the leakage current of the gate insulating film of the normally-on crystal 20 is increased, or the gate insulating film is broken. When the leakage current of the gate insulating film of the normally-on crystal 20 is increased or the gate insulating film is broken, the semiconductor device is not operated well. Therefore, the reliability of the semiconductor device is degraded.

Further, even if there is no problem with the gate insulating film, a high voltage is applied between the second source 21 of the normally-on crystal 20 and the second gate 23, and the transistor 20 can be energized. On the second source 21 side, charges are trapped. Through the trapped charge, there is a ripple of current failure.

When current is depleted, the turn-on current is lowered and the operation is poor. As a result, the reliability of semiconductor devices is still declining. Therefore, it is preferable to suppress occurrence of an overvoltage to the connection portion.

In the semiconductor device of the present embodiment, in the open state, 0 V is applied to the source terminal 100, and a positive voltage is applied to the gate terminal 200, for example, the product of the open impedance and the drain current. Further, a positive voltage, for example, 10 V, is applied to the gate terminal 300.

At this time, a positive voltage is applied to the first gate 13 of the normally-off transistor 10. Therefore, the normally-off transistor 10 is turned on.

The second gate 23 of the normally-on crystal 20 is connected to the connection portion between the second source 21 and the first drain 12 by the first diode 40. When the second source 21 is turned on by the normally-off transistor 10, it becomes a potential near 0V. Accordingly, the second gate 23 is a positive voltage near 0 V, and more accurately, the voltage of the second source 21 is added to the voltage of the forward voltage (Vf) of the first diode 40 in the forward direction. Therefore, the normally energized crystal 20 also becomes an opener. Therefore, between the source terminal 100 and the 汲 terminal 200, a current is turned on.

When the semiconductor device is moved from the off state to the on state, the normally-off transistor 10 is preferably turned on earlier than the current-on transistor 20. It is assumed that when the normally-on transistor 20 is turned on first, a high voltage is applied to the connection portion between the first drain 12 and the second source 21, and the characteristics of the normally-off transistor 10 having a low withstand voltage are deteriorated. Therefore.

In the present embodiment, when the semiconductor device is moved from the off state to the on state, current flows in the second diode 60 connected in parallel to the first impedance 50. Therefore, the charging system of the first gate 13 of the normally-off transistor 10 is not affected by the first impedance 50. Accordingly, the first gate 13 can be quickly charged. Thus, the semiconductor device is turned off When the state transitions to the on state, it becomes possible to surely turn off the normally-off transistor 10, and the more energized crystal 20 is turned on first.

Next, a case where the semiconductor device is turned off from the on state is considered. In this case, the applied voltage of the source terminal 100 and the gate terminal 200 does not change, and the applied voltage of the gate terminal 300 drops from a positive voltage to 0 V, for example, from 10 V to 0 V.

The second gate 23 of the normally-on crystal 20 is such that the capacitor 30 is present, and only the amplitude of the gate terminal 300 is lowered, and the voltage is lowered. For example, the voltage at the time of turning on the second source 21 is assumed to be 0V. In this case, the potential of the second gate 23 decreases only from the forward voltage (Vf) of the first diode 40 to the amplitude of the gate terminal 300, for example, by 10V, and becomes (Vf-10)V. Negative potential.

Further, when the voltage between the second source 21 and the second gate 23 is equal to or lower than the threshold voltage of the normally-on crystal 20, the normally-on crystal 20 is turned off.

0 V is applied to the first gate 13 of the normally-off transistor 10. Therefore, the normally-off transistor 10 is also turned off. Thus, the current between the source terminal 100 and the drain terminal 200 is blocked.

When the first impedance 50 is set, the offset time of the normally-off transistor 10 and the offset time of the normally-on crystal 20 can be delayed by a desired time. Accordingly, when the semiconductor device is moved from the on state to the off state, the normally-on transistor 20 is turned off earlier than the normally-off transistor 10.

When the normally-on transistor 20 is turned off first through the normally-on transistor 20, the overvoltage is suppressed from being applied to the connection portion. Because it is always The transistor 20 is turned off first, and it is assumed that even if the potential of the connection portion rises via the transient current, the charge can be removed from the source terminal 100 by the normally-off transistor 10 that is turned on.

As described above, the semiconductor device of the present embodiment functions as a normally-off transistor including the source terminal 100, the gate terminal 200, and the gate terminal 300.

Further, as described above, in the semiconductor device of the present embodiment, when the semiconductor device is moved from the off state to the on state, the normally-off transistor 10 is turned on earlier than the normally-on transistor 20. In addition, when the semiconductor device is moved from the on state to the off state, the normally-on transistor 20 is turned off earlier than the normally-off transistor 10. However, it is suppressed that a high voltage or an overvoltage is generated in the connection between the normally-off transistor 10 and the normally-energized crystal 20. As a result, the reliability of semiconductor devices has increased.

2 is a circuit diagram of a semiconductor device of a comparative form. The semiconductor device of the comparative embodiment is different from the semiconductor device of the present embodiment in that the first cathode 41 of the first diode 40 is electrically connected to the first source 11 instead of the second source 21. In the comparative embodiment, the first cathode 41 is clamped to the source terminal 100.

In the semiconductor device of the comparative embodiment, similarly to the present embodiment, when the semiconductor device is moved from the on state to the off state, the normally-on transistor 20 is turned off earlier than the normal-off transistor 10. However, it is suppressed that an overvoltage is generated at the connection between the normally-off transistor 10 and the normally-energized crystal 20.

In the semiconductor device of the comparative form, there is a power supply When it enters, an overvoltage is generated at the junction. In the present embodiment, the first diode 40 is connected to the connection portion. However, the parasitic capacitance of the connection portion becomes larger as compared with the comparative form. Therefore, when the input to the power source of the semiconductor device is suppressed, an overvoltage is generated in the connection portion.

Further, in the semiconductor device of the comparative embodiment, a positive boosted voltage (current) is applied to the second gate 23, and a high voltage is applied between the second source 21 and the second gate 23. The ruthenium of the gate insulating film of the normally-on crystal 20 is destroyed. In the semiconductor device of the present embodiment, the positive electric charge that has entered the second gate 23 passes through the first diode 40 and flows directly into the second source electrode 21. Accordingly, it is suppressed that a high voltage is applied between the second source 21 and the second gate 23.

According to the review by the inventors, especially in the HEMT of GaN-based semiconductors, the gate voltage of the gate insulating film is extremely positively biased, and the withstand voltage is generally lower than that of the case where the gate is extremely negatively biased. . Accordingly, the semiconductor device of the present embodiment is particularly effective in the case of a HEMT which is a GaN-based semiconductor.

Further, in the semiconductor device of the present embodiment, unlike the semiconductor device of the comparative embodiment, the wiring connected to the first cathode 42 of the first diode 40 does not cross the other wiring. Accordingly, when the semiconductor device of the present embodiment is mounted on a circuit board or the like, it is easy to mount.

In the semiconductor device of the present embodiment, it is preferable that the avalanche breakdown voltage of the normally-off transistor 10 is lower than the withstand voltage of the gate insulating film of the normally-on transistor 20. Thereby, the withstand voltage between the first source 11 and the first drain 12 when the normally-off transistor is turned off is used as the more constant current crystal The withstand voltage between the second source 21 and the second gate 23 of the body is low.

In this way, for example, even when an overvoltage is generated in the connection portion via boosting or the like, the charge of the connection portion can be removed when the avalanche breakdown voltage of the normally-off transistor 10 is generated. Accordingly, the voltage applied between the second source 21 of the normally-on crystal 20 and the second gate 23 can be made low as the withstand voltage of the gate insulating film of the normally-on crystal 20 .

However, the leakage current of the gate insulating film of the normally-on crystal 20 is prevented from being increased, and the gate insulating film is broken. In addition, it also prevents current from being depleted. As a result, the reliability of semiconductor devices has increased.

However, in general, the withstand voltage of the gate insulating film of the normally-on crystal 20 exceeds the case where the gate exceeds the negative bias by 30V. Accordingly, it is preferable that the avalanche collapse voltage of the normally-off transistor 10 is 30 V or less.

The avalanche collapse voltage of the normally-off transistor 10 is preferably higher than the absolute value of the threshold voltage (Vth) of the normally-on transistor 20. The reason why the normally energized crystal 20 is reliably turned off is as it is. From this point of view, the avalanche collapse voltage of the normally-off transistor 10 is preferably an absolute value of the threshold voltage (Vth) of the normally-on crystal 20 + 5 V or more. It is assumed that, in the case of Vth=-10V, it is preferable that the avalanche collapse voltage of the normally-off transistor 10 is 15V or more.

The capacity of the capacitor 30 is preferably 10 times or more and 100 times or less the input capacitance of the normally-on crystal 20 . The negative voltage applied to the second gate 23 of the normally-on crystal 20 is determined by the ratio of the capacity of the capacitor 30 to the input capacity of the normally-on crystal 20 . Therefore, capacitor 30 The capacity is larger.

The capacity of the capacitor 30 is 10 times or more of the input capacity of the normally-on crystal 20, and can be applied to 90% or more of the amplitude applied to the gate terminal 300. Further, when it exceeds 100 times, the capacitor is too large and there is a concern that the size of the semiconductor device is increased.

However, the input capacitance of the normally-on crystal 20 refers to the capacitance between the second gate 23 and the second source 21 and the second drain 22 . The input capacitance is a value in which the bias voltage between the second source 21 and the second drain 22 is 0 V and is in a pinch-off state.

Further, it is preferable that the first diode 40 is a Schottky barrier diode. When a negative boosted voltage (current) is applied to the second gate 23, the voltage between the second source 21 and the second gate 23 is lower than the threshold voltage of the normally-on crystal 20, and it becomes common. The energized crystal 20 is not turned on.

The path of the negative electric charge from the second gate 23 is only the leakage current of the first diode 40. Accordingly, the leakage current of the first diode 40 is preferably a relatively large Schottky barrier diode.

It is preferable that the impedance value of the first impedance 50 is 1 Ω or more and 100 Ω or less. When it is below this range, there is a delay that is not a deliberate delay. When this range is exceeded, the delay time becomes too long, and the switching speed of the semiconductor device is lowered, which is not preferable.

It is preferable that the input capacitance of the normally-off transistor 10 and the impedance value of the first impedance 50 are larger than 20 nsec. That is, the input capacitance of the normally-off transistor 10 is made C, and the impedance value of the first impedance 50 is taken as In the case of R, it is preferable to satisfy the following formula (1).

CR>20nsec. . . (1)

The semiconductor device is turned off from the on state, and the time until the transistor 20 is turned off is about 20 nsec. Accordingly, in order to turn off the normally-on crystal 20 for the normally-off transistor 10, the normally-off transistor 10 is required to be in an open state for a period longer than 20 nsec.

The switching time of the normally-off transistor 10 is determined by the time constant (CR). Accordingly, it is preferable to satisfy the above formula (1) from the viewpoint of suppressing the overvoltage of the connection portion.

For example, when the input capacitance (C) of the normally-off transistor 10 is 500 pF, the impedance value (R) satisfying the first impedance 50 of the above formula (1) is about 40 Ω.

Further, it is preferable that the input capacitance of the normally-off transistor 10 and the impedance value of the first impedance are larger than 100 nsec. In other words, when the input capacitance of the normally-off transistor 10 is C and the impedance value of the first impedance 50 is R, it is preferable to satisfy the following formula (2).

CR>100nsec. . . (2)

The semiconductor device is preferably used in the case of the operating frequency of the MHz sequence, and it is preferable to keep the normally-off transistor 10 in the on state between the off periods of the semiconductor device during operation. Since the charging and discharging of the normally-off transistor 10 is suppressed, a semiconductor device with low loss can be realized.

In order to keep the normally-off transistor 10 in an open state, For example, the switching period of the normally-off transistor 10 can be lengthened. For example, when the power ratio is turned on and off at 5 MHz, the power-off ratio (duty ratio) of the turn-on and turn-off is 0.5, and the off period of the normally-off transistor 10 is 100 nsec. Accordingly, it is preferable to satisfy the above formula (2) from the viewpoint of reducing the loss.

However, the input capacitance of the normally-off transistor 10 refers to the capacitance between the first gate 13 and the first source 11 and the first drain 12. The input capacitance is a value in which the bias voltage between the first source 11 and the first drain 12 is 0 V and is in a pinch-off state.

According to the semiconductor device of the present embodiment, the reliability of the normally-off transistor 10 and the normally-on transistor 20 that can be connected in series can be improved.

(Second embodiment)

The semiconductor device of the present embodiment is the same as the first embodiment except that a plurality of first diodes are connected in series. Accordingly, the description of the content overlapping with the first embodiment will be omitted.

Fig. 3 is a circuit diagram of a semiconductor device of the embodiment. In the semiconductor device of the present embodiment, two of the first diodes 40 are connected in series.

According to the present embodiment, in the open state of the semiconductor device, the voltage of the voltage of the second source 21 in the forward voltage (Vf) × 2 of the first diode 40 is applied to the voltage of the second source 21. The second gate is 23 . Accordingly, the overspeed driving of the normally energized crystal 20 becomes possible and the opening current can be increased.

However, although the case of connecting the two first diodes 40 in series has been described as an example, the number of the first diodes 40 connected in series may of course be three or more. When n (n is an integer of 2 or more), the voltage of the voltage of the second source 21 in the forward voltage (Vf) × n of the first diode 40 is added to the voltage of the second source 21 2 gate 23.

According to the present embodiment, the effect of the first embodiment is added, and an increase in the on-current can be achieved.

(Third embodiment)

The semiconductor device of the present embodiment is the same as the first embodiment except that the second impedance is electrically connected to the first end between the first end of the capacitor and the first impedance. In other words, it is the same as the first embodiment except that the second impedance is provided between the gate terminal and the capacitor and the first gate. Accordingly, the description of the content overlapping with the first embodiment will be omitted.

Fig. 4 is a circuit diagram of the semiconductor device of the embodiment.

The semiconductor device of the present embodiment includes a second impedance 70 provided between the gate terminal 300 and the capacitor 30 and the first gate 13. One end of the second impedance 70 is electrically connected between the first end portion 31 of the capacitor 30 and the first impedance 50. Further, the other end of the second impedance 70 is connected to the gate terminal 300.

In the circuit design of power electronics, there is a case where adjustment of the operating speed of the transistor is required for noise countermeasures. In this embodiment In the case where the second impedance 70 is provided, the gate voltage applied to the gate terminal 300 can be delayed by the transmission of the first gate 13 and the second gate 23. Accordingly, the operating speed (switching speed) of the semiconductor device can be adjusted.

According to the present embodiment, the effect of the first embodiment is added, and the operating speed (switching speed) of the semiconductor device can be adjusted.

(Fourth embodiment)

The semiconductor device of the present embodiment is similar to the first embodiment except that the third impedance is provided between the second end portion of the capacitor and the second gate. Accordingly, the description of the content overlapping with the first embodiment will be omitted.

Fig. 5 is a circuit diagram of a semiconductor device of the embodiment.

The semiconductor device of the present embodiment is provided between the second end portion 32 of the capacitor 30 and the second gate 23, and includes a third impedance 55.

As described above, in the circuit design of power electronics, there is a case where adjustment of the operating speed of the transistor is required for noise countermeasures. In the present embodiment, by providing the third impedance 55, the delay of the gate voltage applied to the gate terminal 300 to the second gate 23 can be delayed.

The transmission of the first gate 13 of the gate voltage can be independently adjusted by the first impedance 50 or the second diode 60. Accordingly, the operating speed (switching speed) of the semiconductor device can be adjusted.

According to this embodiment, it is added to the first embodiment. The effect is that the operating speed (switching speed) of the semiconductor device can be adjusted.

(Fifth Embodiment)

In the semiconductor device of the present embodiment, the third anode that is electrically connected to the first source and the third cathode that is electrically connected to the first drain are provided, and the voltage is more frequently turned off when the voltage is gradually decreased in the forward direction. The Schottky barrier diode having a lower descending voltage of the parasitic body of the crystal is the same as that of the first embodiment. Accordingly, the description of the content overlapping with the first embodiment will be omitted.

Fig. 6 is a circuit diagram of a semiconductor device of the embodiment. In the semiconductor device of the present embodiment, the Schottky barrier diode 80 is provided in parallel with the normally-off transistor 10.

The Schottky barrier diode 80 has a third anode 81 and a third cathode 82. Further, the third anode 81 is connected to the first source 11 . Further, the third cathode 82 is connected to the first drain 12 and the second source 21.

The forward voltage drop (Vf) of the Schottky barrier diode 80 is lower than the forward voltage (Vf) of the parasitic diode (not shown) of the normally-off transistor.

In the case where the Schottky barrier diode 80 is not provided, when the source terminal 100 becomes a positive voltage reflow mode for the 汲 terminal 200, the current flows in the parasitic body of the normally-off transistor 10. Diode. In this embodiment, a parasitic device having a more normally broken transistor 10 is provided. The forward voltage (Vf) of the body diode is a Schottky barrier diode 80 having a low voltage (Vf) in the forward direction. Thus, in the reflow mode, the current flows in the Schottky barrier diode 80.

The Schottky barrier bipolar system is different from the PiN diode and operates using only a large number of carriers. Accordingly, compared with the PiN diode, the recovery characteristics are superior. As a result, in the present embodiment, the effect of the first embodiment is added, and the recovery characteristic of the reflow mode can be improved. In addition, the forward voltage drop (Vf) is small, and the conduction loss or switching loss in the return mode can also be reduced.

Further, the application of the overvoltage via the boosting of the connection portion or the like is suppressed by the parasitic capacitance of the Schottky barrier diode 80. Further, the leakage current through the Schottky barrier diode 80 can be removed from the connection portion, and the application of the overvoltage of the connection portion can be suppressed. Along with this, semiconductor devices with improved reliability have been realized. Further, the leakage current of the Schottky barrier diode 80 also suppresses the voltage rise of the first drain 12 of the normally-off transistor 10. Therefore, the action of stability is also achieved.

However, the Schottky barrier diode system does not have an avalanche guarantee, and the withstand voltage of the Schottky barrier diode 80 is better than the avalanche collapse voltage of the normally-off transistor 10.

(Sixth embodiment)

The semiconductor device of the present embodiment has a fourth anode electrically connected to the first source and a fourth cathode electrically connected to the first drain Extremely, the more accurate the voltage is, the lower the withstand voltage between the second source and the second gate of the energized crystal is lower, and the sense voltage is lower than the avalanche collapse voltage of the normally-off transistor. Other than the diode, it is the same as that of the first embodiment. Accordingly, the description of the content overlapping with the first embodiment will be omitted.

Fig. 7 is a circuit diagram of a semiconductor device of the embodiment. In the semiconductor device of the present embodiment, the arrester diode 85 is provided in parallel with the normally-off transistor 10.

The arrester diode 85 has a fourth anode 86 and a fourth cathode 87. The fourth anode 86 is electrically connected to the first source 11 . Further, the fourth cathode 87 is electrically connected to the first drain 12 and the second source 21.

The voltage of the arrester diode 85 is set to be lower than the avalanche collapse voltage of the normally-off transistor 10. Further, the sense voltage is set to be lower than the withstand voltage of the gate insulating film of the normally-on crystal 20 . As a result, the withstand voltage between the first source 11 and the first drain 12 when the normally-off transistor 10 is turned off becomes the second source 21 and the second gate 23 of the normally-on transistor 20 . The withstand voltage is low.

In the semiconductor device of the present embodiment, an overvoltage is applied to the connection portion between the normally-off transistor 10 and the normally-on transistor 20 via a boost, and the charge is removed when the overvoltage reaches the threshold voltage. In the Jenus diode 85, exit from the source terminal 100. Accordingly, the voltage rise of the connection portion is suppressed, and the leakage current of the gate insulating film of the normally-on crystal 20 is prevented from increasing, and the gate insulating film is broken. In addition, it also prevents current from being depleted. With that, the reliability of semiconductor devices is Rise.

The voltage of the arrester diode 85 can be controlled more accurately than the avalanche collapse voltage of the normally-off transistor 10. As a result, in the semiconductor device of the present embodiment, when the Zener diode 85 is used, it becomes a person who can more stably control the overvoltage of the connection portion. Further, even if a high voltage is applied to the first drain 12 of the normally-off transistor 10 for unexpected noise or the like, the charge can be removed by the use of the diode 85, and the protection of the normally-off transistor 10 can be performed. Also contributed.

(Seventh embodiment)

The semiconductor device of the present embodiment has the configurations of the first, third, fourth, fifth, and sixth embodiments. Accordingly, the description of the contents overlapping with the first, third, fourth, fifth, and sixth embodiments will be omitted.

Fig. 8 is a circuit diagram of a semiconductor device of the embodiment. The semiconductor device of the present embodiment achieves the effects of combining the embodiments when the configurations of the first, third, fourth, fifth, and sixth embodiments are all provided.

(Eighth embodiment)

The semiconductor device of the present embodiment further includes a fifth diode having a fifth anode electrically connected to the first source and a fifth diode electrically connected to the fifth cathode of the second drain. 1 embodiment is the same. Accordingly, the description of the content overlapping with the first embodiment will be omitted.

Fig. 9 is a circuit diagram of a semiconductor device of the embodiment. The normally-off transistor 10 system includes a body diode (not shown). However, the normally-on crystal 20 does not have a body diode (parasitic diode).

The semiconductor device includes a fifth diode 91 having a fifth anode 91 connected to the first source 11 and a fifth cathode 92 connected to the fifth cathode 92 of the second drain 22 . The voltage of the fifth diode 90 at the source terminal 100 is higher than that of the 汲 terminal 200 (reflow mode), and has a function of flowing a current from the source terminal 100 side to the 汲 terminal 200 side. The so-called reflux diode.

The fifth diode 90 is compared with the body diode of the normally-off transistor 10, and is preferably used for a diode having superior recovery characteristics. It is preferable that the fifth diode 90 has a shorter recovery time than the body diode of the normally-off transistor 10. The fifth diode 90 is, for example, compared with a PIN diode or a PN diode, and is a Schottky barrier diode having a superior recovery property, or a fast recovery diode.

Further, the fifth diode 90 is preferably a diode of a wider energy gap semiconductor having a larger band gap than Si. The use of a two-pole system of a wide-gap semiconductor enables a high voltage with a diode called Si. Examples of the wide band gap semiconductor include GaN-based semiconductors, SiC, diamonds, and the like.

In the semiconductor device of the present embodiment, the return current flowing through the body diode of the normally-off transistor 10 is suppressed in the reflow mode. Further, a return current flows to the current path including the fifth diode 90.

For the fifth diode 90, a body diode of the more normally-off transistor 10 is used, and the diode having a short recovery time and superior recovery characteristics is used. Then, according to the embodiment, the return current is realized in the flow A semiconductor device with improved recovery characteristics during operation. Therefore, for example, when the semiconductor device of the present embodiment is used as a switching element of an inverter circuit of a motor control system, it is possible to suppress switching loss in the reflow mode.

Further, by suppressing the shunt, even if the temperature environment changes, the characteristics in the reflow mode can be suppressed from becoming unstable.

As described above, according to the present embodiment, the effect of the first embodiment is added, and a semiconductor device having improved recovery characteristics is provided.

Although the embodiments of the present invention have been described, the embodiments are presented as examples and are not intended to limit the scope of the invention. The present invention can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. For example, constituent elements of one embodiment may be replaced or changed with constituent elements of other embodiments. The invention and its modifications are intended to be included within the scope of the invention and the scope of the invention.

10‧‧‧Normally broken crystal

11‧‧‧1st source

12‧‧‧1st bungee

13‧‧‧1st gate

20‧‧‧Normally energized crystal

21‧‧‧2nd source

22‧‧‧2nd bungee

23‧‧‧2nd gate

30‧‧‧ Capacitors

31‧‧‧1st end

32‧‧‧2nd end

40‧‧‧1st dipole

41‧‧‧1st anode

42‧‧‧1st cathode

50‧‧‧1st impedance

60‧‧‧2nd diode

61‧‧‧2nd anode

62‧‧‧2nd cathode

100‧‧‧ source terminal

200‧‧‧汲 extremes

300‧‧ ‧ gate terminal

Claims (11)

A semiconductor device comprising: a normally-off transistor having a first source, a first drain, and a first gate; and a second source electrically connected to the first drain, and a second source a second-gate normally-on crystal; and a capacitor having a first end and a second end, wherein the second end is electrically connected to the second gate; and electrically connected to a first anode between the second end portion and the second gate, and a first diode electrically connected to the first cathode of the second source; and the first end portion and the first end portion a first impedance between the first gates; a second anode electrically connected to the first end; and a second cathode electrically connected to the first gate, and the first The impedance is connected to the second diode in parallel. The semiconductor device according to claim 1, wherein the constant current crystal system uses a HEMT of a GaN-based semiconductor. The semiconductor device according to claim 1, wherein the capacitance of the capacitor is 10 times or more of an input capacitance of the normally-on crystal. The semiconductor device according to claim 1, wherein the first dipole system is a Schottky barrier diode. The semiconductor device according to claim 1, wherein the normally-off cell system uses a vertical MOSFET of Si. The semiconductor device according to claim 1, wherein a product of the input capacitance of the normally-off transistor and the impedance value of the first impedance is larger than 20 nsec. The semiconductor device according to claim 1, further comprising a second impedance electrically connected between the first end portion and the first impedance. The semiconductor device according to claim 1, further comprising a third impedance provided between the second end portion and the second gate. The semiconductor device according to claim 1, further comprising: a third anode electrically connected to the first source; and a third cathode electrically connected to the first drain The direction-down voltage is a Schottky barrier diode having a lower voltage lower than the forward direction of the parasitic body diode of the normally-off transistor. The semiconductor device according to claim 1, further comprising a fourth anode electrically connected to the first source and a fourth cathode electrically connected to the first drain The nano voltage is lower than the withstand voltage between the second source and the second gate of the normally-on crystal, and the threshold voltage is lower than the avalanche collapse voltage of the normally-off transistor. Polar body. The semiconductor device according to claim 1, further comprising a fifth anode having a first source electrically connected to the fifth anode and a fifth cathode electrically connected to the second drain Diode.