TWI583006B - Capacitor having a graphene structure, semiconductor device including the capacitor and method of forming the same - Google Patents

Description

Capacitor having graphene structure, semiconductor device including capacitor, and method of forming same

This invention relates to a semiconductor device, and more particularly to a capacitor.

A capacitor containing a metallic electrode, such as a metal oxide metal (MOM) capacitor or a metal insulator metal (MIM) capacitor, uses a metal member such as aluminum or copper to form a capacitor. MOM capacitors have the ability to store less than 10 femto femto (fF/μm ² ) per square micron. MIM capacitors have the ability to store from about 30fF/μm ² to 100fF/μm ² .

In some examples, a dielectric material having a high dielectric constant (ie, a high-k dielectric material) is used to increase the storage capacity per unit area. In some examples, thin electrodes formed by atomic layer deposition (ALD) are used to increase the storage capacity per unit area.

In some embodiments of the present disclosure, a capacitor includes a first graphene structure having a plurality of first graphene layers. The capacitor further includes a dielectric a layer above the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a plurality of second graphene layers.

In some embodiments of the present disclosure, the number of graphene layers in the plurality of first graphene layers ranges from 2 to 20 layers.

In some embodiments of the present disclosure, the number of graphene layers in the second plurality of graphenes is the same as the graphene layer in the first plurality of graphenes.

In some embodiments of the present disclosure, the number of graphene layers in the second plurality of graphenes is different from the graphene layers in the first plurality of graphenes

In some embodiments of the present disclosure, the capacitor further includes a first contact structure for transferring charge carriers into the first graphene structure or transferring charge carriers from the first graphene structure.

In some embodiments of the present disclosure, the first contact structure extends to the first graphene structure to contact the plurality of graphene layers of the plurality of first graphene layers.

In some embodiments of the present disclosure, the first contact structure extends through the dielectric layer to the first graphene structure.

In some embodiments of the present disclosure, the first contact structure includes a conductive material. The first contact structure further includes a barrier layer separating the conductive material from the first graphene structure.

In some embodiments of the present disclosure, the capacitor further includes a second contact structure for transferring charge carriers into the second graphene structure or transferring charge carriers from the second graphene structure.

In some embodiments of the present disclosure, the second contact structure extends to The second graphene structure contacts a plurality of graphene layers of the plurality of second graphene layers.

In some embodiments of the present disclosure, the second contact structure in the second graphene structure has substantially vertical sidewalls.

In some embodiments of the present disclosure, the second contact structure in the second graphene structure has tapered sidewalls.

In some embodiments of the present disclosure, the capacitor further includes a growth layer between the dielectric layer and the second graphene structure.

In some embodiments of the present disclosure, the growth layer comprises at least one of copper, aluminum, and tungsten.

In some embodiments of the present disclosure, a semiconductor device includes a substrate. The semiconductor device further includes an interconnect structure over which the interconnect structure has a plurality of conductive features. The semiconductor device further includes a capacitor in which the capacitor electrically contacts at least one of the conductive features of the conductive features. The capacitor includes a first graphene structure having a plurality of first graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a plurality of second graphene layers.

In some embodiments of the present disclosure, the interconnect structure includes a dielectric material between adjacent conductive features of the conductive features, and the dielectric layer includes the same material as the dielectric material.

In some embodiments of the present disclosure, the interconnect structure includes a dielectric material between adjacent conductive features of the conductive features, and the dielectric layer includes a substance that is different from the dielectric material.

In some embodiments of the present disclosure, the capacitor further includes a growth layer between the dielectric layer and the second graphene layer.

In some embodiments of the present disclosure, the at least one electrically conductive feature of the electrically conductive features is the same material as the growth layer.

In some embodiments of the present disclosure, a method of making a capacitor includes forming a first graphene structure having a plurality of first graphene layers. The method further includes forming a dielectric layer over the first graphene structure. The method further includes forming a second graphene structure over the dielectric layer, wherein the second graphene structure comprises a plurality of second graphene layers.

The technical features and advantages of the present disclosure have been broadly described above, and the detailed description of the present disclosure will be better understood. Other technical features and advantages of the subject matter of the claims of the present disclosure will be described below. It will be appreciated by those skilled in the art that the present invention may be practiced with the same or equivalents. It is also to be understood by those of ordinary skill in the art that this invention is not limited to the spirit and scope of the disclosure as defined by the appended claims.

100‧‧‧Semiconductor device

102‧‧‧Substrate

104‧‧‧Interconnected structure

110‧‧‧Conducting components

150‧‧‧ capacitor

152‧‧‧First graphene structure

154‧‧‧ dielectric layer

156‧‧‧Second graphene structure

158‧‧‧First contact structure

160‧‧‧second junction structure

100’‧‧‧ semiconductor devices

170‧‧‧ growth layer

200‧‧‧contact structure

The technical features and advantages of the present disclosure are fully understood by reference to the foregoing description and the accompanying drawings.

1A is a schematic cross-sectional view of a semiconductor device, in accordance with some embodiments.

FIG. 1B is a schematic cross-sectional view of a semiconductor device, in accordance with some embodiments.

2 is a cross-sectional view of a contact structure of a capacitor, in accordance with some embodiments.

3 is a flow chart of a method of fabricating a semiconductor device, in accordance with some embodiments.

The following invention provides many different embodiments or examples for implementing different features of the subject matter provided. The following describes specific examples of components and arrangements to simplify The invention is embodied. Of course these are merely examples and are not intended to be limiting. For example, embodiments in which the first feature is formed above or above the second feature may include direct contact formation of the first feature and the second feature, and may include forming additional features between the first feature and the second feature, Thus an embodiment in which the first feature and the second feature are not in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and is not intended to define the relationship between the various embodiments and/or configurations discussed.

In addition, spatial relative terms such as "below", "below", "lower", "above", "upper", etc. may be used herein for convenience of description to describe one as illustrated in the figure. The relationship of an element or feature to another element or feature. Spatially relative terms are intended to encompass different orientations of the user or the elements of the operation, in addition to the orientation illustrated. For example, elements in the "a" or "an" or "an" Thus, the exemplary language "below" can encompass the orientations above and below. The elements may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatially used descriptions herein may be interpreted similarly.

FIG. 1A is a schematic cross-sectional view of a semiconductor device 100 in accordance with some embodiments. The semiconductor device 100 includes a substrate 102. An interconnect structure 104 is above the substrate 102. The interconnect structure 104 includes a plurality of conductive elements for active devices that are electrically connected in the substrate. A conductive element 110 is in the metal layer of interconnect structure 104. A capacitor 150 is formed in electrical contact with the conductive element 110. Capacitor 150 includes a first graphene structure 152 in electrical contact with conductive element 110. The first graphene structure 152 includes a plurality of graphene layers. A dielectric layer 154 is on the first graphene structure 152. A second graphene structure 156 is on the dielectric layer 154. The second graphene structure 156 includes a plurality of graphene layers. A dielectric layer 154 is positioned between the first graphene structure 152 and the second graphene structure 156 to form a capacitor structure. A first contact structure 158 is electrically connected to the first graphene structure 152. The first contact structure 158 is used to transfer charge carriers into the first graphene structure 152 or to transfer charge carriers from the first graphene structure 152. The second contact structure 160 is electrically connected to the second graphene structure 156. The second contact structure 160 is used to transfer charge carriers into the second graphene structure 156 or to transfer charge carriers from the second graphene structure 156.

The substrate 102 includes an active device and a passive device. In some embodiments, the active device includes a transistor, a thyristor, or other suitable active device. In some embodiments, the passive device includes a resistor or other suitable passive device. In some embodiments, substrate 102 includes a memory cell or processing circuitry.

The interconnect structure 104 includes a plurality of conductive structures for electrically connecting the active device and the passive device in the substrate 102. In some embodiments, the electrically conductive structure comprises copper, aluminum, tungsten, or other suitable electrically conductive material. The interconnect structure also includes passive devices such as capacitors 150, resistors, or other suitable passive devices. The interconnect structure includes dielectric materials surrounding the conductive structures to help reduce crosstalk interference between adjacent conductive structures. In some embodiments, the dielectric material comprises cerium oxide, cerium nitride, cerium oxynitride, or other suitable dielectric species. In some embodiments, interconnect structure 104 includes contact pads for connecting to other substrates. In some embodiments, the contact pads can be used to form a three dimensional integrated circuit (3DIC).

Conductive element 110 is one of the electrically conductive structures of interconnect structure 104. In some embodiments, conductive element 110 comprises copper, aluminum, tungsten, or other suitable electrically conductive material. Conductive element 110 can be used to connect an active device or a passive device in substrate 102. Conductive element 110 can also be used to transfer charge to one of the first graphene structures 152 that is closest to substrate 102.

Capacitor 150 is on conductive element 110. Capacitor 150 can be used to store the charge in interconnect structure 104. Capacitor 150 can also be used to help reduce cross-connections The fluctuation of the voltage of the structure 104. Capacitor 150 includes a first graphene structure 152 and a second graphene structure 154.

Graphene is a layer of carbon atoms arranged in a two-dimensional array. The carbon atoms are arranged in a hexagonal pattern. A two-dimensional array of carbon atom layers helps reduce charge transfer between separate graphene layers. The use of graphene as an electrode in capacitor 150 can help a large number of charge carriers increase the storage capacity per unit area compared to other electrode materials.

In contrast, the metal electrode has the ability to transfer charge carriers into the direction of the top surface of the parallel substrate 102, as well as the direction of the top surface of the vertical substrate 102. Therefore, the metal electrode stores charge carriers close to the outer surface of the electrode. The storage of charge carriers near the surface of the metal electrode means that the middle portion of the metal electrode is not used to store charge carriers, which reduces the storage of charge carriers per unit area. By increasing the storage capacity per unit charge carrier, the overall area of the electrode can be reduced, but the charge storage capability can also be maintained to help reduce the overall size of the semiconductor device.

The use of graphene electrodes without the use of metal electrodes can also help reduce the use of expensive high-k dielectric materials such as zirconium oxide or hafnium oxide. For graphene electrodes, it is also possible to reduce the slower and more expensive formation techniques, such as atomic layer deposition (ALD). Therefore, the use of graphene electrodes can also help increase productivity and reduce the cost in the manufacturing process compared to metal electrodes. The two-dimensional array structure of graphene also helps to adjust the overall capacitance of capacitor 150 by adjusting the number of layers in the graphene structure.

The first graphene structure 152 includes a plurality of graphene layers. The number of layers in the first graphene structure 152 is selected based on the desired storage capacity of the capacitor 150. In some embodiments, the number of graphene layers in the first graphene structure 152 ranges from about 2 to about 20 layers. In some embodiments, the number of layers is greater than 20 layers to further increase the overall storage capacity of capacitor 150. In the first graphene structure Each of 152 blocks the transfer of charge carriers to adjacent layers in the first graphene structure 152. Even when a charge difference exists between adjacent layers, the two-dimensional array of carbon atoms in the first graphene structure 152 blocks charge carrier transfer between the layers.

Dielectric layer 154 is on first graphene structure 152. In some embodiments, the area of the dielectric layer 154 matches the area of the first graphene structure 152. In some embodiments, the first graphene structure 152 includes a portion that is exposed by the dielectric layer 154. In some embodiments, dielectric layer 154 includes hafnium oxide, tantalum nitride, or other suitable dielectric species. In some embodiments, the material of the dielectric layer 154 is the same as the dielectric material of the interconnect structure 154. In some embodiments, the material of the dielectric layer is different from the dielectric material of interconnect structure 104. In some embodiments, the thickness of the dielectric layer 154 ranges from about 100 angstroms (Å) to about 500 Å. If the thickness of the dielectric layer 154 is too small, in some embodiments, the dielectric layer is insufficient to insulate the first graphene structure 152 from the second graphene structure 156, and the charge is in the first graphene structure and the second graphite. Direct interchange between olefin structures. If the thickness of the dielectric layer 154 is too large, in some embodiments, the leakage of the capacitor 150 will increase beyond an acceptable range.

The second graphene structure 156 includes a plurality of graphene layers. In some embodiments, the area of the second graphene structure 156 is less than the area of the first graphene structure 152 or the area of the dielectric layer 154. In some embodiments, the area of the second graphene structure 156 is the same or larger than the area of the first graphene structure or the area of the dielectric layer 154. The number of graphene layers in the second graphene structure 156 is selected to range from about 2 to about 20 layers, depending on the desired storage capacity of the capacitor 150. In some embodiments, the number of layers is greater than 20 layers to further increase the overall storage capacity of capacitor 150. In some embodiments, the number of layers in the second graphene structure 156 is the same as the number of layers in the first graphene structure 152. In some embodiments, the number of layers in the second graphene structure 156 is not the same as the number of layers in the first graphene structure 152. Each layer in the second graphene structure 156 blocks charge carrier transfer to the first graphene Adjacent layers in the structure. Even when a charge difference exists between adjacent layers, a two-dimensional array of carbon atoms in the second graphene structure 156 can hinder charge carrier transfer between the layers.

The first contact structure 158 is used to electrically connect the first graphene structure 152. In some embodiments, the first contact structure 158 is a cathode. In some embodiments, the first contact structure 158 is an anode. In some embodiments, the first contact structure 158 comprises a conductive material, such as copper, aluminum, tungsten, or other suitable conductive material. In some embodiments, the first contact structure 158 further includes a barrier layer such as tantalum nitride, titanium nitride, or a suitable barrier layer thereof. The barrier layer helps to avoid or minimize diffusion of conductive species from the first contact structure to the first graphene structure 152. In some embodiments, the first contact structure 158 extends through the dielectric layer 154 to the first graphene structure 152. In some embodiments, the first contact structure 158 extends to a portion of the first graphene structure 152 that is exposed by the dielectric layer 154.

Since the transfer of charge between the spacer layers of the first graphene structure 152 is hindered, the first contact structure 158 extends to the first graphene structure to contact the plurality of layers of the graphene structure to enhance the first contact structure And transfer between the first graphene structure. In some embodiments, the first contact structure 158 contacts all of the graphene layers in the first graphene structure 152. In some embodiments, the first contact structure 158 contacts less than all of the graphene layers in the first graphene structure 152 in the first graphene structure 152.

The second contact structure 160 is used to electrically connect the second graphene structure 156. In some embodiments, the second contact structure 160 is a cathode. In some embodiments, the second contact structure 160 is an anode. In some embodiments, the second contact structure 160 comprises a conductive material, such as copper, aluminum, tungsten, or other suitable conductive material. In some embodiments, the first contact structure 158 further includes a barrier layer such as tantalum nitride, titanium nitride, or a suitable barrier layer thereof. The barrier layer helps to avoid or minimize diffusion of conductive species from the first contact structure to the second graphene structure 156.

Since the transfer of charge between the spacer layers of the second graphene structure 156 is hindered, the second contact structure 160 extends to the second graphene structure to contact the plurality of layers of the graphene structure to enhance the second contact structure And charge transfer between the second graphene structure. In some embodiments, the second contact structure 160 contacts all of the graphene layers in the second graphene structure 156. In some embodiments, the second contact structure 160 contacts a layer of less than all of the graphene layers in the second graphene structure 156. In some embodiments, the second contact structure 160 extends through the second graphene structure 156 to the dielectric layer 154.

FIG. 1B is a schematic cross-sectional view of a semiconductor device 100', in accordance with some embodiments. The semiconductor device 100' is similar to the semiconductor device 100 and like elements have the same reference numerals. In contrast to semiconductor device 100, semiconductor device 100' includes a growth layer 170 between dielectric layer 154 and a second graphene structure.

The growth layer 170 serves to enhance the ability to form the second graphene structure 156 on the dielectric layer 154. In order to form a second graphene structure of the semiconductor device 100 having a suitable resistance on the dielectric layer 154, a formation temperature of about 700 ° C is used to form the second graphene structure. This generation of temperatures can potentially damage structures, such as interconnect structure 104. This formation temperature causes the conductive material in the interconnect structure 104 to diffuse into the surrounding dielectric material. This diffusion will reduce the ability of the surrounding dielectric material to reduce crosstalk interference between adjacent conductive elements.

In contrast, the semiconductor device 100' includes a growth layer 170 between the dielectric layer 154 and the second graphene layer 156 to reduce the formation temperature of the second graphene structure of the semiconductor device 100'. In some embodiments, the formation temperature of the second graphene structure on the growth layer 170 ranges from about 400 °C to about 600 °C. This lower generation temperature helps reduce the risk of injury to the back-end process structure, such as interconnect structure 104.

In some embodiments, the growth layer 170 comprises copper, aluminum, tungsten, or other suitable electrically conductive material. In some embodiments, the growth layer 170 has a range from about 100 Nanometers (nm) to a thickness of about 500 nm. In some embodiments, if the thickness of the growth layer 170 is too thin, the growth layer is not effective in helping the formation of the second graphene structure 156. If the thickness of the growth layer 170 is too thick, the size of the semiconductor device 100' is increased without significantly increasing the ability to form the second graphene structure 156.

2 is a schematic cross-sectional view of a contact structure 200, in accordance with some embodiments. Contact structure 200 is indicated as an example of second contact structure 160 (Fig. 1A). Although discussed with respect to the contact structure 160, the details of the contact structure 200 can also be applied to the first contact structure 158. The contact structure 200 includes a conductive material 162 surrounded by a barrier layer 164. Contact structure 200 extends to the opening in second graphene structure 156. In some embodiments, the opening in the second graphene structure 156 has substantially vertical sidewalls. The term essentially used herein is used to describe the vertical deformation attributable to the production deformation during the manufacture of the contact structure 200. In some embodiments, the opening in the second graphene structure 156 has tapered sidewalls. The tapered sidewall of the opening means that the width of the opening closest to dielectric layer 154 (Fig. 1A) is less than the width of the opening furthest from the dielectric layer.

In some embodiments, the contact structure extends completely through the second graphene structure 156 to contact all of the graphene layers in the second graphene structure. In some embodiments, the contact structure 200 extends only partially through the second graphene structure 156.

Conductive material 162 can be used to transfer charge carriers to second graphene structure 156 or to transfer charge carriers from second graphene structure 156. In some embodiments, the electrically conductive material 162 comprises copper, aluminum, tungsten, or other suitable electrically conductive material.

The barrier layer 164 helps to avoid or minimize the diffusion of carbon atoms from the second graphene structure 156 to the conductive species 162 and helps to avoid or minimize diffusion of the conductive species 162 to the second graphene structure. In some embodiments, barrier layer 164 includes tantalum nitride, titanium nitride, or a suitable barrier layer thereof.

FIG. 3 illustrates a method 300 of fabricating a semiconductor device in accordance with some embodiments. flow chart. The method 300 begins at operation 302 where an interconnect structure is formed on a substrate. In some embodiments, the interconnect structure, for example, interconnect structure 104 (FIG. 1A) is formed on the substrate, such as substrate 102, by a dielectric material formed on the substrate. In some embodiments, the dielectric material is subjected to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and rotation. Coating method, or other suitable forming technique.

The conductive features are formed in the dielectric material by a dual damascene process, in some embodiments. The conductive features are electrically connected to the active device or the passive device in the substrate. In some embodiments, the electrically conductive features include copper, aluminum, tungsten, or other suitable electrically conductive material.

In operation 304, a first graphene structure is formed that contacts the conductive properties of the interconnect structure. The first graphene structure, such as the first graphene structure 152 (FIG. 1A), includes a plurality of graphene layers. In some embodiments, the number of graphene layers in the first graphene structure ranges from about 2 to about 20 layers. In some embodiments, the first graphene structure is formed over the conductive structure by CVD. In some embodiments, the first line by graphene structure formed using precursors include methane (CH ₄₎ and hydrogen (H ₂₎ is. During the CVD process, the gas stream and temperature are selected such that graphene is effectively grown on the conductive structure. In some embodiments, the CVD process includes multiple steps. In some embodiments, the CVD process includes four steps. The first step uses only H ₂ gas and heats the semiconductor device to the target deposition temperature for the first duration. The second step uses H ₂ gas and maintains the semiconductor device at the target deposition temperature for the second duration. The third step uses H ₂ and CH ₄ at the target deposition temperature to deposit graphene. The gases H ₂ and CH ₄ are maintained at a gas flow ratio of CH ₄ /H ₂ greater than one. In the fourth step, the semiconductor device is cooled. In some embodiments, maintaining the semiconductor device at the target deposition temperature in the second and third steps includes maintaining a pressure of the CVD deposition chamber ranging from about 1 Torr to about 4 Torr. In some embodiments, the target deposition temperature ranges from 400 °C to about 1000 °C.

In operation 306, a dielectric layer is formed on the first graphene structure. A dielectric layer, such as dielectric layer 154 (FIG. 1A), is formed by PVD, CVD, ALD, spin coating, or other suitable forming techniques, in some embodiments. In some embodiments, the dielectric layer comprises hafnium oxide, tantalum nitride, hafnium oxynitride, tantalum carbide or other suitable dielectric species. In some embodiments, the dielectric layer comprises the same material as the dielectric of the interconnect structure. In some embodiments, the dielectric layer comprises a substance different from the dielectric of the interconnect structure.

In some embodiments, a dielectric layer is formed over the entire first graphene structure. In some embodiments, a dielectric layer is formed to expose a portion of the first graphene structure. In some embodiments, a dielectric layer is formed over the entire first graphene structure and a portion of the dielectric is removed to expose a portion of the first graphene structure.

In an optional operation 308, a growth layer is formed on the dielectric layer. A growth layer, such as growth layer 170 (Fig. IB), is used to assist in the formation of the second graphene structure. Compared to the second graphene structure formed directly on the dielectric layer, the use of the growth layer can lower the formation temperature of the second graphene structure. In some embodiments, the growth layer comprises a conductive material. In some embodiments, the electrically conductive material comprises copper, aluminum, tungsten, or other suitable electrically conductive material. In some implementations, the growth layer includes the same materials as the conductive materials in the interconnect structure. In some embodiments, the growth layer comprises a substance that is different from the conductive material in the interconnect structure. In some embodiments, the growth layer is formed by PVD, ALD, sputtering, or other suitable formation methods. In some embodiments, the growth layer has a thickness ranging from about 100 nanometers (nm) to about 500 nm. In some embodiments, the growth layer is formed over the entire dielectric layer. In some embodiments, the growth layer is formed over less than the entire dielectric layer. In some embodiments, a growth layer is formed over the entire dielectric layer and then a portion of the growth layer is removed to expose the dielectric layer Part of the electrical layer. In some embodiments, the growth layer is ignored when the back-end process elements of the semiconductor device are capable of withstanding higher generation temperatures.

In operation 310, a second graphene structure is formed on the growth layer. The second graphene structure, such as the second graphene structure 156 (FIG. 1B), includes a plurality of graphene layers. In some embodiments, the number of graphene layers in the second graphene structure ranges from about 2 to about 20 layers. In some embodiments, the number of layers in the second graphene structure is the same as the number of layers in the first graphene structure. In some embodiments, the number of layers in the second graphene structure is not the same as the number of layers in the first graphene structure. In some embodiments, the second graphene layer is formed over the growth layer by a process similar to that described for the first graphene structure. In some embodiments, the second graphene structure is formed using a temperature that is the same as the first graphene structure. In some embodiments, the second graphene structure is formed using a temperature that is different from the first graphene structure. In some embodiments, the second graphene structure is formed over the entire dielectric layer. In some embodiments, the second graphene structure is formed less than the entire dielectric layer. In some embodiments, ignoring operation 308, the second graphene structure is formed directly on the dielectric layer.

In operation 312, a contact structure is formed in each of the first graphene structure and the second graphene structure. The contact structure includes a first contact structure in the first graphene structure, such as a first contact structure 158 (Fig. 1A). The contact structure further includes a second contact structure in the second graphene structure, such as a second contact structure 160 (Fig. 1A). The contact structure is formed by forming an opening in each of the first graphene structure and the second graphene structure. In some embodiments, the at least one opening comprises a substantially vertical sidewall. In some embodiments, the at least one opening comprises a tapered sidewall.

The contact structure includes a conductive material and a barrier layer. In some embodiments, the electrically conductive material comprises copper, aluminum, tungsten, or other suitable electrically conductive material. In some real In the embodiment, the conductive material of the first contact structure is the same as the conductive material of the second contact structure. In some embodiments, the conductive material of the first contact structure is different from the conductive material of the second contact structure. In some embodiments, the electrically conductive material comprises the same material as one of the growth layer or the electrically conductive material of the interconnect structure. In some embodiments, the electrically conductive material comprises a different material than the growth layer of the interconnect structure and the electrically conductive material.

The barrier layer is between the conductive material and the first graphene structure or the second graphene structure. In some embodiments, the barrier layer comprises tantalum nitride, titanium nitride, or a suitable barrier layer thereof. In some embodiments, the barrier layer of the first contact structure is the same as the barrier layer of the second contact structure. In some embodiments, the barrier layer of the first contact structure is not the same as the barrier layer of the second contact structure.

The contact structure extends at least partially through the first graphene structure and the second graphene structure to contact the plurality of graphene layers. In some embodiments, the first contact structure extends through all of the graphene layers of the first graphene structure. In some embodiments, the first contact structure extends through a layer of less than all of the graphene layers in the first graphene structure. In some embodiments, the second contact structure extends through all of the graphene layers in the second graphene structure. In some embodiments, the second contact structure extends through a layer of less than all of the graphene layers in the second graphene structure.

In some embodiments, the method includes additional operations. In some embodiments, the order of operations of method 300 is changed.

One of the points described here is about capacitors. The capacitor includes a first graphene structure having a plurality of first graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a plurality of second graphene layers.

Another aspect of the description relates to semiconductor devices. A semiconductor device includes a substrate and an interconnect structure over the substrate. Interconnect The structure has a plurality of conductive features. The semiconductor device further includes a capacitor in which the capacitor electrically contacts at least one of the conductive features of the conductive features. The capacitor includes a first graphene structure having a plurality of first graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure having a plurality of second graphene layers over the dielectric layer.

Yet another aspect of the present description relates to a method of making a capacitor. The method includes forming a first graphene structure having a plurality of first graphene layers. The method further includes forming a dielectric layer over the first graphene structure. The method further includes forming a second graphene structure over the dielectric layer, wherein the second graphene structure comprises a plurality of second graphene layers.

The features of some of the above-described embodiments are provided to enable those skilled in the art to better understand the various aspects of the invention. Those skilled in the art can easily design or modify other processes and structures based on the disclosure of the present application to achieve the same objectives and achieve the same advantages as the embodiments described herein. It should be understood by those skilled in the art that this <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

100‧‧‧Semiconductor device

102‧‧‧Substrate

104‧‧‧Interconnected structure

110‧‧‧Conducting components

150‧‧‧ capacitor

152‧‧‧First graphene structure

154‧‧‧ dielectric layer

156‧‧‧Second graphene structure

158‧‧‧First contact structure

160‧‧‧second junction structure

Claims (10)

A capacitor comprising: a first graphene structure having a plurality of first graphene layers; a dielectric layer over the first graphene structure; and a second graphene structure over the dielectric layer Wherein the second graphene structure has a plurality of second graphene layers, wherein the first graphene structure extends horizontally beyond a sidewall of the second graphene structure. The capacitor of claim 1, further comprising a first contact structure for transferring charge carriers into the first graphene structure or transferring charge carriers from the first graphene structure, Wherein the first contact structure is disposed adjacent to the second graphene structure. The capacitor of claim 2, wherein the first contact structure extends to the first graphene structure to contact the plurality of graphene layers of the plurality of first graphene layers. The capacitor of claim 2, wherein the first contact structure extends through the dielectric layer to the first graphene structure, wherein the dielectric layer extends horizontally beyond the second graphene structure The side wall. The capacitor of claim 2, wherein the first contact structure comprises: a conductive material; and a barrier layer separating the conductive material from the first graphene structure. The capacitor of claim 1, further comprising a second contact structure for transferring charge carriers into the second graphene structure or transferring charge carriers from the second graphene structure, Wherein the second contact structure extends to the second graphene structure to contact the plurality of graphene layers of the plurality of second graphene layers. The capacitor of claim 1, further comprising a growth layer between the dielectric layer and the second graphene structure. A semiconductor device comprising: a substrate; an interconnect structure above the substrate, the interconnect structure having a plurality of conductive features; and a capacitor in which the capacitor electrically contacts at least one of the conductive features a feature, wherein the capacitor comprises: a first graphene structure having a plurality of first graphene structures, the first graphene structure having a first horizontal dimension, the first horizontal dimension being from the first graphene structure Measured between opposite sidewalls; a dielectric layer over the first graphene structure; and a second graphene structure over the dielectric layer, wherein the second graphene structure has a plurality of second graphite An olefin layer and a second horizontal dimension, the second horizontal dimension being measured from between opposing sidewalls of the second graphene structure, wherein the first horizontal dimension is greater than the second horizontal dimension. The semiconductor device of claim 8, wherein the capacitor further comprises a growth layer between the dielectric layer and the second graphene layer. A method of fabricating a capacitor, comprising: forming a first graphene structure having a plurality of first graphene layers, wherein forming the first graphene structure comprises a first charge of the capacitor according to a desired charge storage amount of the capacitor Selecting a plurality of layers in the olefin layer; forming a dielectric layer over the first graphene structure; forming a second graphene structure over the dielectric layer, wherein the second graphene structure comprises a plurality of second Graphene layer.