TWI579895B - Line layout and method of spacer self-aligned quadruple patterning for the same - Google Patents

Description

Method for self-aligned quadruple patterning of gap layout and line layout

The present invention relates to a circuit layout and a circuit layout method, and more particularly to a spacer self-aligned quadruple patterning (SAQP) process and a line layout.

As semiconductor devices continue to shrink in size, exposure techniques using extreme ultraviolet (EUV) with a short wavelength of 13.5 nm have been proposed. However, the above exposure technique cannot be used for mass production and requires high equipment costs. Therefore, it is currently expected to adopt spacer self-aligned double patterning (SADP) technology to overcome the problems of the extreme ultraviolet light exposure technology.

The spacer self-aligned double patterning is a technique of finally removing the spacer by forming a spacer on the sidewall of the first mask pattern and forming a second mask pattern between the spacers. By self-aligned double patterning, the resulting line pitch can be reduced to half the line pitch of a typical lithography process.

In addition, on the basis of self-aligned double patterning, a spacer self-aligned quadruple patterning technique which can further reduce the line spacing is proposed. The spacer self-aligned quadruple patterning is a technique of performing two self-aligned double patterning. However, lines fabricated using self-aligned quadruple patterning techniques generally have too small a separation distance between the ends of the lines, resulting in an improper electrical connection between the lines. In order to solve the above problems, many lithography processes are currently used in the spacer self-aligned quadruple patterning process. Although the multiple lithography process can effectively increase the separation distance between the ends of the lines, it also increases the manufacturing cost and the complexity of the process.

Based on the above, there is a need for a process technique that can effectively increase the separation distance between the ends of the lines in the case of using a smaller number of lithography processes.

The present invention provides a method of line layout and line layout self-aligned quadruple patterning of a line layout that is capable of effectively increasing the separation distance between the ends of the lines in the case of using fewer lithography processes.

The present invention provides a method for self-aligned quadruple patterning of a spacer of a line layout, comprising: forming i core layers, each core layer comprising: a body layer extending along a first direction and having a first end and a first a second end; and an end layer connected to the first end of the main body layer and protruding toward the second direction; forming a first spacer wall on the sidewall of the core layer; removing the core layer; and forming 2i auxiliary a pattern, and i is an integer of 1 or more, each auxiliary pattern extending along the first direction and spaced apart in the first direction; wherein, in a region corresponding to the end layer, The portion not overlapping the auxiliary pattern exhibits the shape of the I-beam, and the I-beam is a first region adjacent to a region corresponding to the body layer, and a second region not adjacent to a region corresponding to the body layer And a third zone connecting the first zone and the second zone.

In an embodiment of the invention, the area of the first region increases from the second end toward the first direction, and the distance between the first region and the second end increases.

In an embodiment of the present invention, the method for the self-aligned quadruple patterning of the spacers of the line layout further includes: forming a stacked structure, the stacked structure includes a plurality of pattern receiving layers; forming the core layer on the stacked structure And transferring the pattern of the first spacers to one or more of the pattern receiving layers to form a first spacer pattern layer before forming the auxiliary pattern.

In an embodiment of the present invention, the method for self-aligning quadruple patterning of the spacers of the line layout further includes: forming a second spacer, sidewalls of the first spacer pattern layer and sidewalls of the auxiliary pattern; Forming a third gap wall and a fourth gap wall, wherein the third gap wall is located in the fourth gap wall of the second gap wall; removing the second gap wall and the auxiliary pattern to form a closed loop And removing part of the closed loop described above such that the closed loop is disconnected in a region corresponding to the auxiliary pattern and a region corresponding to the second end.

In an embodiment of the present invention, before the step of removing a portion of the closed loop, the method further includes: removing the first spacer pattern layer before forming the third spacer and the fourth spacer; Two gap walls and the above auxiliary The auxiliary pattern is a mask, and one or more layers of the pattern receiving layer are patterned to form a patterned layer; a second spacer pattern layer is formed at a position corresponding to the first spacer pattern layer; and removed The second spacer, the auxiliary pattern, and the patterned layer.

In an embodiment of the invention, the step of removing a portion of the closed loop includes removing a portion of the second spacer pattern layer and a portion of the third gap located in the first predetermined removal region and the second predetermined removal region. a wall and a portion of the fourth spacer; wherein the first predetermined removal region extends in the first direction, and covers a portion corresponding to the auxiliary pattern and a portion corresponding to the end layer, wherein the first predetermined The removal area does not cover an area corresponding to the main body layer; the second predetermined removal area covers an area corresponding to the second end of the main body layer, wherein the second predetermined removal area does not cover an area corresponding to the end layer And an area corresponding to the above auxiliary pattern.

The invention further provides a circuit layout, comprising: 4i+1 lines, i is an integer of 1 or more, each line includes: a main body portion extending along the first direction; and a connecting portion connected to the main body portion and along The second direction extends; wherein the main body portion of the above-mentioned line has a loop structure.

In an embodiment of the present invention, the main body of the odd-numbered strips of the line has the loop structure, wherein the first strip of the line is calculated from an end point of the main body portion of each line toward the first direction Does not have the above loop structure.

In an embodiment of the invention, the area enclosed by the loop structure increases with the distance between the loop structure and the end point of the body portion of each line. And increase.

In an embodiment of the invention, the length of the loop structure in the second direction is increased as the distance between the loop structure and the end point of the main body portion of each line increases, and in the first side The upward length is substantially fixed.

Based on the above, the present invention forms an auxiliary pattern in a region corresponding to the above-mentioned end layer, and causes a portion of the region corresponding to the end layer that does not overlap with the auxiliary pattern to assume the shape of the I-beam, whereby less use is possible In the case of the number of lithography processes, the separation distance between the ends of the lines is effectively increased.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧ Target layer

12‧‧‧Oxide layer

14‧‧‧First tantalum layer

16‧‧‧Polysilicon layer

16a‧‧‧patterned layer

18‧‧‧Second tantalum layer

20‧‧‧Organic material layer

22‧‧‧The third layer of tantalum nitride

24‧‧‧ body layer

24a‧‧‧ first end

24b‧‧‧second end

26‧‧‧End layer

28‧‧‧ core layer

30‧‧‧First gap

30a‧‧‧ clearance wall pattern

30b‧‧‧First gap pattern layer

32‧‧‧Auxiliary pattern material layer

34‧‧‧Auxiliary pattern

34a‧‧‧First District

34b‧‧‧Second District

34c‧‧‧Second District

36‧‧‧Second gap

40‧‧‧fourth gap

42‧‧‧Second gap pattern layer

44‧‧‧ third gap

45‧‧‧closed loop

46‧‧‧First scheduled removal area

48‧‧‧Second scheduled removal area

50, 52, 54, 56, 58, 60, 62, 64, 66‧‧‧ lines

50a, 52a, 54a, 56a, 58a, 60a, 62a, 64a, 66a‧‧‧ main body

50b, 52b, 54b, 56b, 58b, 60b, 62b, 64b, 66b‧‧‧ connection

50c‧‧‧protrusion

66c‧‧‧step structure

68a, 68b, 68c‧‧‧ loop structure

70‧‧‧ solder pads

D1‧‧‧ first direction

D2‧‧‧ second direction

L1, L2‧‧‧ length

1A-1M are schematic top views of a flow of a line layout method according to an embodiment of the invention.

2A to 2L are schematic cross-sectional views taken along line A-A of Figs. 1A to 1L, respectively.

1A-1M are schematic top views of a flow of a line layout method according to an embodiment of the invention. 2A to 2L are schematic cross-sectional views taken along line A-A of Figs. 1A to 1L, respectively.

Embodiments of the present invention utilize a gap wall self-aligned quadruple patterning approach to form a line layout.

Referring to FIG. 1A and FIG. 2A simultaneously, a stacked structure 11 is first formed on the substrate 8. The substrate 8 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide. The stacked structure 11 includes a target layer 10 and a plurality of pattern receiving layers on the target layer 10. The material of the plurality of pattern receiving layers may be an oxide, a nitride, a polysilicon, an organic material, or a combination thereof. In an embodiment, the stacked structure 11 may be, for example, sequentially stacking the target layer 10 from the bottom to the top, the oxide layer 12, the first tantalum nitride layer 14, the polysilicon layer 16, the second tantalum layer 18, and the organic material. The structure of the layer 20 and the third tantalum nitride layer 22. The material of the target layer 10 may be a conductor including a metal or a metal alloy such as copper, aluminum or a combination thereof. The material of the oxide layer 12 is, for example, an oxide of tetraethoxysilane, methane or a combination thereof. The formation method of each of the above layers is, for example, a chemical vapor deposition method or a physical vapor deposition method. In this embodiment, each layer on the target layer 10 can receive the pattern of the upper layer and serve as a mask for the next layer of pattern transfer. Therefore, although the materials of the respective layers in the stacked structure 11 and the order of lamination are enumerated above, the present invention is not limited thereto, and as long as there is a sufficient etching selectivity ratio between the layers in the etching process for pattern transfer, it is possible to The desired pattern is transferred to the target layer 10, and the materials, the number of layers, and the stacking order of the above layers are Adjust it yourself if you need it.

Referring again to FIG. 1A and FIG. 2A, i core layers 28 are then formed on the stacked structure 11. Each core layer 28 includes a body layer 24 and an end layer 26. The body layer 24 has a first end 24a and a second end 24b extending along the first direction D1. The end layer 26 is coupled to the first end 24a of the body layer 24 and projects toward the second direction D2. The first direction D1 is, for example, the X direction, and the second direction D2 is, for example, the Y direction, but the invention is not limited thereto. The material of the core layer 28 is, for example, an organic material, an inorganic material, or a combination thereof. The organic material is, for example, amorphous carbon, a hydrocarbon or a combination thereof, and the inorganic material is, for example, cerium oxide, cerium oxynitride or a combination thereof. The core layer 28 is formed by, for example, forming a core material layer (not shown), and then patterning the core material layer.

Referring to FIG. 1A, FIG. 1B, FIG. 2A, and FIG. 2B simultaneously, the first spacers 30 are formed on the sidewalls of the core layer 28. The width of the first spacer 30 is, for example, 10 nm to 40 nm. The material of the first spacers 30 is, for example, hafnium oxide, tantalum nitride or a combination thereof. The first spacers 30 are formed by, for example, forming a spacer material layer (not shown), and then performing an anisotropic etching process.

Referring to FIG. 1B, FIG. 1C, FIG. 1D, FIG. 2B, FIG. 2C, and FIG. 2D simultaneously, the core layer 28 is removed. The method of removing the core layer 28 may be a dry stripping process, a dry etching process, a wet stripping process, a wet etching process, or a combination thereof. Thereafter, the pattern of the first spacers 30 is transferred to one or more layers in the pattern receiving layer to form the first spacer pattern layer 30b. More specifically, the method for transferring the pattern is, for example, first using the first spacer 30 as a mask and performing an etching process. A pattern corresponding to the position of the first spacer 30 is formed in the pattern receiving layer in the stacked structure 11, and then the first spacer 30 as a mask is removed. In an embodiment, the first spacers 30 are used as a mask and an etching process is performed to transfer the pattern of the first spacers 30 to the third tantalum nitride layer 22 under the first spacers 30 and The organic material layer 20 is then removed from the first spacers 30 to form a spacer pattern 30a. Then, the spacer pattern 30a is used as a mask and an etching process is performed to transfer the formed pattern to the second layer of the second tantalum nitride layer 18, and the spacer pattern 30a is removed to form the first layer. The spacer pattern layer 30b. In other words, the step of transferring the pattern described above is performed twice to transfer the pattern of the first spacers 30 to the second layer of tantalum nitride 18. The method of removing the first spacers 30 and removing the spacer patterns 30a may be a dry etching process, a wet etching process, or a combination thereof.

Referring to FIG. 1E and FIG. 2E simultaneously, an auxiliary pattern material layer 32 is formed on the polysilicon layer 16 and covers the sidewall of the first spacer pattern layer 30b. The auxiliary pattern material layer 32 includes an oxide, a nitride, or a combination thereof. The oxide is, for example, cerium oxide, cerium oxynitride or a combination thereof. The method of forming the auxiliary pattern material layer 32 is, for example, a chemical vapor deposition method or a physical vapor deposition method.

Referring to FIG. 1E, FIG. 1F, FIG. 2E, and FIG. 2F simultaneously, the auxiliary pattern material layer 32 is patterned to form 2i auxiliary patterns 34 (i is an integer of 1 or more). Each of the auxiliary patterns 34 extends along the first direction D1 and is spaced apart in the first direction D1. In an embodiment, each of the auxiliary patterns 34 may be substantially aligned in the first direction D1, but may not be aligned as long as it does not affect the pitch of the subsequently formed line ends. In an embodiment, each auxiliary pattern The lengths of 34 in the second direction D2 are substantially equal. More specifically, the length of each auxiliary pattern 34 in the first direction D1 is, for example, 80 nm to 500 nm, the length in the second direction D2 is, for example, 80 nm to 500 nm, and the spacing between each auxiliary pattern 34 is, for example, 40 nm. ~500nm. The patterning process may first utilize yellow light, extreme ultraviolet light, ArF excimer laser, KrF excimer laser, etc., to expose the formed pattern material layer, and then develop.

In an embodiment, in the region corresponding to the end layer 26 (Fig. 1C), the portion that does not overlap the auxiliary pattern 34 assumes the shape of the I-beam. More specifically, the portion not overlapped with the auxiliary pattern 34 is composed of the first region 34a, the second region 34b, and the third region 34c. The first region 34a is located on the first side of the auxiliary pattern 34, adjacent to the region corresponding to the body layer 24 (FIG. 1A), and the second region 34b is positioned on the second side of the auxiliary pattern 34, not corresponding to the body layer 24 (Fig. The area of 1A) is adjacent. The third zone 34c is located between the adjacent two auxiliary patterns, connecting the first zone 34a and the second zone 34b. The portion of the above-mentioned portion that is not overlapped with the auxiliary pattern 34, that is, the combination of the first region 34a, the second region 34b, and the third region 34c, assumes the shape of the I-beam. In the present embodiment, the area of the first zone 34a increases as the distance between the first zone 34a and the second end 24b increases; the area of the second zone 34b remains substantially unchanged. The above distance is calculated toward the first direction D1 with the second end 24b as a starting point. In an embodiment, the length L1 of the first region 34a and the second region 34b in the first direction D1 and the length L3 of the second region 34b in the second direction D2 do not substantially change, but in the second direction D2 The upper length L2 is increased as the distance between the first zone 34a and the second end 24b increases.

Referring to FIG. 1G and FIG. 2G simultaneously, the second spacer 36 is formed on the sidewall of the first spacer pattern layer 30b and the sidewall of the auxiliary pattern 34. The width of the second spacer 36 is, for example, 10 nm to 40 nm. The material of the second spacer 36 is, for example, hafnium oxide, tantalum nitride or a combination thereof. The second spacer 36 is formed by, for example, forming a spacer material layer (not shown), and then performing an anisotropic etching process.

Referring to FIG. 1G, FIG. 1H, FIG. 2G, and FIG. 2H simultaneously, the first spacer pattern layer 30b is removed. The method of removing the first spacer pattern layer 30b may be the same as or different from the method of removing the core layer 28. The method of removing the first spacer pattern layer 30b may be a dry stripping process, a dry etching process, a wet stripping process, a wet etching process, or a combination thereof.

Referring to FIG. 1I and FIG. 2I simultaneously, next, one or more layers in the pattern receiving layer under the second spacer 36 and the auxiliary pattern 34 are patterned by using the second spacer 36 and the auxiliary pattern 34 as a mask. To form the patterned layer 16a. In an embodiment, the pattern of the second spacer 36 and the auxiliary pattern 34 is transferred to the polysilicon layer 16 under the second spacer 36 and the auxiliary pattern 34. The above patterning method may be a dry stripping process, a dry etching process, a wet stripping process, a wet etching process, or a combination thereof.

Referring to FIG. 1I and FIG. 2I simultaneously, the second spacer pattern layer 42 is formed at a position corresponding to the first spacer pattern layer 30b, and the third spacer 44 is formed on the sidewall of the second spacer 36. Four spacers 40. The third spacer 44 is located within the fourth spacer 40. The width of the third spacer 44 is, for example, 10 nm to 40 nm, and the width of the fourth spacer 40 is, for example, 10 nm to 40 nm. Third spacer 44 For example, the fourth spacer 40 is formed by first forming a spacer material layer (not shown), and then performing an anisotropic etching process. The widths and materials of the first spacers 30, the second spacers 36, the third spacers 44, and the fourth spacers 40 may be the same or different. The material of the third spacer 44 and the fourth spacer 40 is, for example, cerium oxide, tantalum nitride or a combination thereof. It is to be noted that the spacing between each of the auxiliary patterns 34 is smaller than twice the width of the third spacers 44.

Referring to FIG. 1I, FIG. 1J, FIG. 2I, and FIG. 2J simultaneously, the second spacer 36, the auxiliary pattern 34, and the patterned layer 16a are removed to form a closed loop 45. The method of removing the second spacer 36, the auxiliary pattern 34, and the patterned layer 16a may be a dry stripping process, a dry etching process, a wet stripping process, a wet etching process, or a combination thereof.

Referring to FIGS. 1J, 1K, 2J, and 2K, a portion of the closed loop 45 is then removed such that the closed loop 45 is broken in the region corresponding to the auxiliary pattern 34 and the region corresponding to the second end 24b. More specifically, the removed partial closed loop 45 includes a portion of the second spacer pattern layer 42, the third spacer 44, and the fourth spacer 40. In an embodiment, the removed portion is covered by the first predetermined removal zone 46 and the second predetermined removal zone 48. More specifically, the first predetermined removal region 46 extends in the first direction D1 and covers a portion corresponding to the auxiliary pattern 34 and a portion corresponding to the end layer 26, but does not cover an area corresponding to the body layer 24. . The second predetermined removal zone 48 encompasses a region corresponding to the second end 24b of the body layer 24, but does not encompass the region corresponding to the end layer 26 and the region corresponding to the auxiliary pattern 34. Method of removing partially closed loop 45 and method of removing core layer 28 the same. It should be noted that although the present embodiment exemplifies the closed closed loop 45 with the first predetermined removal zone 46 and the second predetermined removal zone 48 separated from each other, the present invention is not limited thereto, and the removed is closed. The loop 45 can of course also be covered by a complete area. More specifically, the closed loop 45 that is removed is, for example, covered by an L-shaped area.

Referring to FIG. 1K, FIG. 1L, FIG. 2K and FIG. 2L simultaneously, the pattern of the second spacer pattern layer 42, the third spacer 44, and the fourth spacer 40 is transferred to the target layer 10 to form a desired line. The method for transferring the pattern to the target layer 10 is, for example, first using the second spacer pattern layer 42, the third spacer 44, and the fourth spacer 40 as a mask and performing an etching process to apply the second spacer pattern layer 42. The pattern of the third spacer 44 and the fourth spacer 40 is transferred to the target layer 10 under the second spacer pattern layer 42, the third spacer 44, and the fourth spacer 40, and then the second spacer pattern is Layer 42, third spacer 44, and fourth spacer 40 are removed to form the desired lines 50, 52, 54, 56, 58, 60, 62, 64, 66.

Referring to FIG. 1M, a plurality of pads 70 are formed, and the pads 70 are connected to the closed closed loop. The material of the pad 70 includes a metal or a metal alloy such as copper or a copper-nickel alloy. The pad 70 is formed by first forming a material layer (not shown) of the pad 70 by chemical vapor deposition or physical vapor deposition, and then using a lithography and etching process.

The line layout structure formed by the above-described line layout method of the present invention will be described below.

Referring to FIG. 1L and FIG. 1M, the circuit layout of the present invention includes: 4i+1 Lines 50, 52, 54, 56, 58, 60, 62, 64, 66 (i is an integer of 1 or more). Lines 50, 52, 54, 56, 58, 60, 62, 64, 66 include body portions 50a, 52a, 54a, 56a, 58a, 60a, 62a, 64a, 66a and connections 50b, 52b, 54b, 56b, respectively. 58b, 60b, 62b, 64b, 66b. The body portions 50a, 52a, 54a, 56a, 58a, 60a, 62a, 64a, 66a extend along the first direction D1. The connecting portions 50b, 52b, 54b, 56b, 58b, 60b, 62b, 64b, 66b are connected to the main body portions 50a, 52a, 54a, 56a, 58a, 60a, 62a, 64a, 66a and extend in the second direction D2. In one embodiment, the spacing between the body portions 50a, 52a, 54a, 56a, 58a, 60a, 62a, 64a, 66a of the lines 50, 52, 54, 56, 58, 60, 62, 64, 66 is, for example, 10 nm to 40 nm, the spacing between the connecting portions 50b, 52b, 54b, 56b, 58b, 60b, 62b, 64b, 66b of each of the lines 50, 52, 54, 56, 58, 60, 62, 64, 66 is, for example, 40nm~500nm. It is to be noted that the main body portions 54a, 58a, 62a of the odd-numbered lines 54, 58 and 62 have the loop structures 68a, 68b, 68c, but the first line 50 does not have a loop structure. The number of the above lines is made at the end points of the main body portions 50a, 52a, 54a, 56a, 58a, 60a, 62a, 64a, 66a of each of the lines 50, 52, 54, 56, 58, 60, 62, 64, 66. Starting from the beginning, and starting from the first direction D1. The area enclosed by the loop structures 68a, 68b, 68c will follow the loop structures 68a, 68b, 68c and the body portions 50a, 52a of each of the lines 50, 52, 54, 56, 58, 60, 64, 64, 66, The distance between the endpoints of 54a, 56a, 58a, 60a, 62a, 64a, 66a increases and increases. In one embodiment, the length of the loop structures 68a, 68b, 68c in the first direction D1 is substantially fixed, while the length in the second direction D2 follows the loop structures 68a, 68b, 68c and each line. The distance between the end points of the body portions 50a, 52a, 54a, 56a, 58a, 60a, 62a, 64a, 66a of 50, 52, 54, 56, 58, 60, 62, 64, 66 increases and increases. In one embodiment, the length of the loop structures 68a, 68b, 68c in the first direction D1 is, for example, 80 nm to 800 nm. Further, the lengths of the connecting portions 50b, 54b, 58b, 62b of the odd-numbered lines 50, 54, 58, and 62 in the second direction D2 are substantially fixed. In one embodiment, the length of the connecting portions 50b, 54b, 58b, 62b of the odd-numbered lines 50, 54, 58, 62 in the second direction D2 is, for example, 20 nm to 500 nm. At the same time, the length of the connecting portions 52b, 56b, 60b, 64b of the even-numbered lines 52, 56, 60, 64 in the second direction D2 will follow the connecting portions 52b, 56b, 60b, 64b and each. The distance between the ends of the body portions 50a, 52a, 54a, 56a, 58a, 60a, 62a, 64a, 66a of the lines 50, 52, 54, 56, 58, 60, 62, 64, 66 increases and increases.

In addition to the configuration of the loop structures 68a, 68b, 68c, the wiring layout of the present invention also has a projection portion 52b protruding toward the adjacent line 52 at the intersection of the connecting portion 50b of the first line 50 and the main body portion 50a. Projection portion 50c. Additionally, the last line 66 will have a stepped structure 66c. Furthermore, the even-numbered lines 52, 56, 60, 64 exhibit an L-shape.

In summary, the present invention forms an auxiliary pattern in a region corresponding to the end layer, and causes a portion of the region corresponding to the end layer that does not overlap with the auxiliary pattern to assume the shape of an I-beam, thereby being usable In the case of a smaller number of lithography processes, the separation distance between the ends of the lines is effectively increased, thereby reducing the manufacturing cost and the complexity of the process. At the same time, it is also possible to provide enough in the horizontal direction. The distance can effectively improve the tolerance of patterning the lines and forming the pads.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

50, 52, 54, 56, 58, 60, 62, 64, 66‧‧‧ lines

50a, 52a, 54a, 56a, 58a, 60a, 62a, 64a, 66a‧‧‧ main body

50b, 52b, 54b, 56b, 58b, 60b, 62b, 64b, 66b‧‧‧ connection

50c‧‧‧protrusion

66c‧‧‧step structure

68a, 68b, 68c‧‧‧ loop structure

D1‧‧‧ first direction

D2‧‧‧ second direction

Claims (10)

A method for self-aligning quadruple patterning of a spacer of a line layout, comprising: forming i core layers, each core layer comprising: a body layer extending along a first direction and having a first end and a a second end; and an end layer connected to the first end of the main body layer and protruding toward a second direction; forming a first spacer wall on the sidewall of the core layer; removing the core layer And forming 2i auxiliary patterns, and i is an integer of 1 or more, each auxiliary pattern extending along the first direction and spaced apart in the first direction; wherein, in a region corresponding to the end layer, A portion that does not overlap the auxiliary patterns exhibits the shape of an I-beam, and the I-beam is a first region adjacent to a region corresponding to the body layer, and a region not adjacent to a region corresponding to the body layer The second zone is formed by a third zone connecting the first zone and the second zone. The method for self-aligning quadruple patterning of a spacer of a line layout according to claim 1, wherein the area of the first area is the same as the first direction from the second end toward the first direction The distance between the zone and the second end increases and increases. The method for self-aligned quadruple patterning of a spacer of a line layout according to claim 1, wherein the method further comprises: forming a stacked structure, the stacked structure comprising a plurality of pattern receiving layers; forming on the stacked structure The core layers; The pattern of the first spacer is transferred to one or more of the pattern receiving layers to form a first spacer pattern layer before the auxiliary patterns are formed. The method for self-aligning quadruple patterning of a spacer of a line layout according to claim 3, further comprising: forming a second spacer, a sidewall of the first spacer pattern layer, and the auxiliary patterns Forming a third gap wall and a fourth gap wall, the third gap wall is located in the fourth gap wall; removing the second gap wall and the auxiliary Patterning to form a closed loop; and removing a portion of the closed loop such that the closed loop is broken at a region corresponding to the auxiliary patterns and a region corresponding to the second end. A method of self-aligning quadruple patterning of a spacer of a line layout according to claim 4, wherein before the step of removing a portion of the closed loop, the method further comprises: forming the third spacer and the fourth Removing the first spacer pattern layer before the spacer; using the second spacer and the auxiliary patterns as masks, patterning one or more layers of the pattern receiving layers to form a patterned layer Forming a second spacer pattern layer at a position corresponding to the first spacer pattern layer; and removing the second spacer, the auxiliary patterns, and the patterned layer. The gap wall self-alignment of the line layout as described in claim 4 of the patent application scope The method of re-patterning, wherein the step of removing a portion of the closed loop comprises: removing a portion of the second spacer pattern layer, a portion of the third gap located in a first predetermined removal region and a second predetermined removal region a wall and a portion of the fourth spacer; wherein the first predetermined removal region extends in the first direction and covers a portion corresponding to the auxiliary patterns and a portion corresponding to the end layer, wherein the first The predetermined removal area does not cover an area corresponding to the body layer; the second predetermined removal area covers an area corresponding to the second end of the body layer, wherein the second predetermined removal area does not cover a layer corresponding to the end layer A region and a region corresponding to the auxiliary patterns. A circuit layout comprising: 4i+1 lines, i is an integer of 2 or more, each line includes: a body portion extending along a first direction; and a connecting portion connected to the body portion and along A second direction extends; wherein the body portions of the plurality of lines have a loop structure. The circuit layout of claim 7, wherein the main body of the odd-numbered strips of the lines has the loop structure, wherein the end portions of the main body portion of each of the lines are oriented toward the first direction, wherein The first line of the lines does not have the loop structure. The circuit layout of claim 8 wherein the area enclosed by the loop structure is increased as the distance between the loop structure and the end of the body portion of each line increases. The circuit layout as described in claim 9 of the patent scope, wherein the loop junction The length in the second direction increases as the distance between the loop structure and the end of the body portion of each line increases, and the length in the first direction is substantially fixed.